129 	void		(*top_write)(struct meson_dw_hdmi *dw_hdmi,  member
229 	dw_hdmi->data->top_write(dw_hdmi, addr, data);  in dw_hdmi_top_write_bits()
448 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET,  0);  in dw_hdmi_phy_init()
459 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));  in dw_hdmi_phy_init()
464 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,  in dw_hdmi_phy_init()
466 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,  in dw_hdmi_phy_init()
469 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,  in dw_hdmi_phy_init()
471 		dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23,  in dw_hdmi_phy_init()
476 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);  in dw_hdmi_phy_init()
478 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);  in dw_hdmi_phy_init()
568 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER,  in dw_hdmi_setup_hpd()
572 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,  in dw_hdmi_setup_hpd()
594 	dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat);  in dw_hdmi_top_irq()
869 	.top_write = dw_hdmi_top_write,
876 	.top_write = dw_hdmi_g12a_top_write,
927 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_init()
932 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_init()
936 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,  in meson_dw_hdmi_init()
939 	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,  in meson_dw_hdmi_init()
1122 	meson_dw_hdmi->data->top_write(meson_dw_hdmi,  in meson_dw_hdmi_pm_suspend()