Lines Matching +full:apb3 +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #include <linux/media-bus-format.h>
34 #define DRIVER_NAME "meson-dw-hdmi"
35 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
42 * - A Synopsys DesignWare HDMI Controller IP
43 * - A TOP control block controlling the Clocks and PHY
44 * - A custom HDMI PHY in order convert video to TMDS signal
81 * - HPD Rise & Fall interrupt
82 * - HDMI Controller Interrupt
83 * - HDMI PHY Init for 480i to 1080p60
84 * - VENC & HDMI Clock setup for 480i to 1080p60
85 * - VENC Mode setup for 480i to 1080p60
89 * - PHY, Clock and Mode setup for 2k && 4k modes
90 * - SDDC Scrambling mode for HDMI 2.0a
91 * - HDCP Setup
92 * - CEC Management
163 return of_device_is_compatible(dw_hdmi->dev->of_node, compat); in dw_hdmi_is_compatible()
177 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
178 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
181 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
182 data = readl(dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
192 return readl(dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_read()
203 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
204 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
207 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_DATA_REG); in dw_hdmi_top_write()
215 writel(data, dw_hdmi->hdmitx + HDMITX_TOP_G12A_OFFSET + (addr << 2)); in dw_hdmi_g12a_top_write()
224 unsigned int data = dw_hdmi->data->top_read(dw_hdmi, addr); in dw_hdmi_top_write_bits()
229 dw_hdmi->data->top_write(dw_hdmi, addr, data); in dw_hdmi_top_write_bits()
241 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
242 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
245 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
246 data = readl(dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
256 return readb(dw_hdmi->hdmitx + addr); in dw_hdmi_g12a_dwc_read()
267 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
268 writel(addr & 0xffff, dw_hdmi->hdmitx + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_write()
271 writel(data, dw_hdmi->hdmitx + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_write()
279 writeb(data, dw_hdmi->hdmitx + addr); in dw_hdmi_g12a_dwc_write()
288 unsigned int data = dw_hdmi->data->dwc_read(dw_hdmi, addr); in dw_hdmi_dwc_write_bits()
293 dw_hdmi->data->dwc_write(dw_hdmi, addr, data); in dw_hdmi_dwc_write_bits()
302 struct meson_drm *priv = dw_hdmi->priv; in meson_hdmi_phy_setup_mode()
303 unsigned int pixel_clock = mode->clock; in meson_hdmi_phy_setup_mode()
306 if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) in meson_hdmi_phy_setup_mode()
309 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || in meson_hdmi_phy_setup_mode()
310 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
313 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); in meson_hdmi_phy_setup_mode()
314 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); in meson_hdmi_phy_setup_mode()
317 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); in meson_hdmi_phy_setup_mode()
318 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); in meson_hdmi_phy_setup_mode()
321 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); in meson_hdmi_phy_setup_mode()
322 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); in meson_hdmi_phy_setup_mode()
325 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); in meson_hdmi_phy_setup_mode()
326 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); in meson_hdmi_phy_setup_mode()
329 "amlogic,meson-gxbb-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
332 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); in meson_hdmi_phy_setup_mode()
333 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); in meson_hdmi_phy_setup_mode()
336 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33634283); in meson_hdmi_phy_setup_mode()
337 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0xb000115b); in meson_hdmi_phy_setup_mode()
340 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33632122); in meson_hdmi_phy_setup_mode()
341 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2000115b); in meson_hdmi_phy_setup_mode()
344 "amlogic,meson-g12a-dw-hdmi")) { in meson_hdmi_phy_setup_mode()
347 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x37eb65c4); in meson_hdmi_phy_setup_mode()
348 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
349 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x0000080b); in meson_hdmi_phy_setup_mode()
352 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb6262); in meson_hdmi_phy_setup_mode()
353 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
354 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
357 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33eb4242); in meson_hdmi_phy_setup_mode()
358 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); in meson_hdmi_phy_setup_mode()
359 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL5, 0x00000003); in meson_hdmi_phy_setup_mode()
366 struct meson_drm *priv = dw_hdmi->priv; in meson_dw_hdmi_phy_reset()
369 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xf); in meson_dw_hdmi_phy_reset()
374 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0xe); in meson_dw_hdmi_phy_reset()
382 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_set_vclk()
389 vclk_freq = mode->clock; in dw_hdmi_set_vclk()
392 if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) in dw_hdmi_set_vclk()
405 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in dw_hdmi_set_vclk()
413 dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) in dw_hdmi_set_vclk()
418 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in dw_hdmi_set_vclk()
423 priv->venc.hdmi_use_enci); in dw_hdmi_set_vclk()
426 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); in dw_hdmi_set_vclk()
434 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_phy_init()
436 readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
438 DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name, in dw_hdmi_phy_init()
439 mode->clock > 340000 ? 40 : 10); in dw_hdmi_phy_init()
442 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in dw_hdmi_phy_init()
445 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in dw_hdmi_phy_init()
448 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0); in dw_hdmi_phy_init()
459 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12)); in dw_hdmi_phy_init()
462 if (mode->clock > 340000 && in dw_hdmi_phy_init()
463 dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_YUV8_1X24) { in dw_hdmi_phy_init()
464 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, in dw_hdmi_phy_init()
466 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, in dw_hdmi_phy_init()
469 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, in dw_hdmi_phy_init()
471 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, in dw_hdmi_phy_init()
476 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); in dw_hdmi_phy_init()
478 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); in dw_hdmi_phy_init()
484 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
488 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || in dw_hdmi_phy_init()
489 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || in dw_hdmi_phy_init()
490 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) in dw_hdmi_phy_init()
491 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
494 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, in dw_hdmi_phy_init()
498 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0); in dw_hdmi_phy_init()
510 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
511 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
513 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
515 /* Temporary Disable HDMI video stream to HDMI-TX */ in dw_hdmi_phy_init()
517 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
519 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
521 /* Re-Enable VENC video stream */ in dw_hdmi_phy_init()
522 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
523 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in dw_hdmi_phy_init()
525 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in dw_hdmi_phy_init()
529 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
531 /* Enable and Select HDMI video source for HDMI-TX */ in dw_hdmi_phy_init()
532 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
534 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
537 priv->io_base + _REG(VPU_HDMI_SETTING)); in dw_hdmi_phy_init()
546 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_phy_disable()
550 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); in dw_hdmi_phy_disable()
558 return !!dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_STAT0) ? in dw_hdmi_read_hpd()
568 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_HPD_FILTER, in dw_hdmi_setup_hpd()
572 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, in dw_hdmi_setup_hpd()
593 stat = dw_hdmi->data->top_read(dw_hdmi, HDMITX_TOP_INTR_STAT); in dw_hdmi_top_irq()
594 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, stat); in dw_hdmi_top_irq()
598 dw_hdmi->irq_stat = stat; in dw_hdmi_top_irq()
615 u32 stat = dw_hdmi->irq_stat; in dw_hdmi_top_thread_irq()
624 dw_hdmi_setup_rx_sense(dw_hdmi->hdmi, hpd_connected, in dw_hdmi_top_thread_irq()
627 drm_helper_hpd_irq_event(dw_hdmi->encoder.dev); in dw_hdmi_top_thread_irq()
639 struct meson_drm *priv = dw_hdmi->priv; in dw_hdmi_mode_valid()
640 bool is_hdmi2_sink = display_info->hdmi.scdc.supported; in dw_hdmi_mode_valid()
650 /* If sink does not support 540MHz, reject the non-420 HDMI2 modes */ in dw_hdmi_mode_valid()
651 if (display_info->max_tmds_clock && in dw_hdmi_mode_valid()
652 mode->clock > display_info->max_tmds_clock && in dw_hdmi_mode_valid()
657 /* Check against non-VIC supported modes */ in dw_hdmi_mode_valid()
663 return meson_vclk_dmt_supported_freq(priv, mode->clock); in dw_hdmi_mode_valid()
668 vclk_freq = mode->clock; in dw_hdmi_mode_valid()
680 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in dw_hdmi_mode_valid()
695 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in dw_hdmi_mode_valid()
698 dev_dbg(dw_hdmi->dev, "%s: vclk:%d phy=%d venc=%d hdmi=%d\n", in dw_hdmi_mode_valid()
758 dw_hdmi->output_bus_fmt = bridge_state->output_bus_cfg.format; in meson_venc_hdmi_encoder_atomic_check()
760 DRM_DEBUG_DRIVER("output_bus_fmt %lx\n", dw_hdmi->output_bus_fmt); in meson_venc_hdmi_encoder_atomic_check()
768 struct meson_drm *priv = dw_hdmi->priv; in meson_venc_hdmi_encoder_disable()
773 priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_venc_hdmi_encoder_disable()
775 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_encoder_disable()
776 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_encoder_disable()
782 struct meson_drm *priv = dw_hdmi->priv; in meson_venc_hdmi_encoder_enable()
784 DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); in meson_venc_hdmi_encoder_enable()
786 if (priv->venc.hdmi_use_enci) in meson_venc_hdmi_encoder_enable()
787 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_encoder_enable()
789 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_encoder_enable()
797 struct meson_drm *priv = dw_hdmi->priv; in meson_venc_hdmi_encoder_mode_set()
802 DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode->name, vic); in meson_venc_hdmi_encoder_mode_set()
804 if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { in meson_venc_hdmi_encoder_mode_set()
809 /* VENC + VENC-DVI Mode setup */ in meson_venc_hdmi_encoder_mode_set()
815 if (dw_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) in meson_venc_hdmi_encoder_mode_set()
816 /* Setup YUV420 to HDMI-TX, no 10bit diphering */ in meson_venc_hdmi_encoder_mode_set()
818 priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_venc_hdmi_encoder_mode_set()
820 /* Setup YUV444 to HDMI-TX, no 10bit diphering */ in meson_venc_hdmi_encoder_mode_set()
821 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); in meson_venc_hdmi_encoder_mode_set()
842 *result = dw_hdmi->data->dwc_read(dw_hdmi, reg); in meson_dw_hdmi_reg_read()
853 dw_hdmi->data->dwc_write(dw_hdmi, reg, val); in meson_dw_hdmi_reg_write()
886 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, 0); in meson_hdmi_connector_is_available()
905 struct meson_drm *priv = meson_dw_hdmi->priv; in meson_dw_hdmi_init()
908 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100); in meson_dw_hdmi_init()
911 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in meson_dw_hdmi_init()
914 reset_control_reset(meson_dw_hdmi->hdmitx_apb); in meson_dw_hdmi_init()
915 reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); in meson_dw_hdmi_init()
916 reset_control_reset(meson_dw_hdmi->hdmitx_phy); in meson_dw_hdmi_init()
918 /* Enable APB3 fail on error */ in meson_dw_hdmi_init()
921 meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); in meson_dw_hdmi_init()
923 meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG); in meson_dw_hdmi_init()
927 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_init()
932 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_init()
935 /* Enable HDMI-TX Interrupt */ in meson_dw_hdmi_init()
936 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR, in meson_dw_hdmi_init()
939 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN, in meson_dw_hdmi_init()
951 struct meson_drm *priv = drm->dev_private; in meson_dw_hdmi_bind()
962 dev_info(drm->dev, "HDMI Output connector not available\n"); in meson_dw_hdmi_bind()
963 return -ENODEV; in meson_dw_hdmi_bind()
966 match = of_device_get_match_data(&pdev->dev); in meson_dw_hdmi_bind()
968 dev_err(&pdev->dev, "failed to get match data\n"); in meson_dw_hdmi_bind()
969 return -ENODEV; in meson_dw_hdmi_bind()
975 return -ENOMEM; in meson_dw_hdmi_bind()
977 meson_dw_hdmi->priv = priv; in meson_dw_hdmi_bind()
978 meson_dw_hdmi->dev = dev; in meson_dw_hdmi_bind()
979 meson_dw_hdmi->data = match; in meson_dw_hdmi_bind()
980 dw_plat_data = &meson_dw_hdmi->dw_plat_data; in meson_dw_hdmi_bind()
981 encoder = &meson_dw_hdmi->encoder; in meson_dw_hdmi_bind()
983 meson_dw_hdmi->hdmi_supply = devm_regulator_get_optional(dev, "hdmi"); in meson_dw_hdmi_bind()
984 if (IS_ERR(meson_dw_hdmi->hdmi_supply)) { in meson_dw_hdmi_bind()
985 if (PTR_ERR(meson_dw_hdmi->hdmi_supply) == -EPROBE_DEFER) in meson_dw_hdmi_bind()
986 return -EPROBE_DEFER; in meson_dw_hdmi_bind()
987 meson_dw_hdmi->hdmi_supply = NULL; in meson_dw_hdmi_bind()
989 ret = regulator_enable(meson_dw_hdmi->hdmi_supply); in meson_dw_hdmi_bind()
994 meson_dw_hdmi->hdmitx_apb = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
996 if (IS_ERR(meson_dw_hdmi->hdmitx_apb)) { in meson_dw_hdmi_bind()
998 return PTR_ERR(meson_dw_hdmi->hdmitx_apb); in meson_dw_hdmi_bind()
1001 meson_dw_hdmi->hdmitx_ctrl = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
1003 if (IS_ERR(meson_dw_hdmi->hdmitx_ctrl)) { in meson_dw_hdmi_bind()
1005 return PTR_ERR(meson_dw_hdmi->hdmitx_ctrl); in meson_dw_hdmi_bind()
1008 meson_dw_hdmi->hdmitx_phy = devm_reset_control_get_exclusive(dev, in meson_dw_hdmi_bind()
1010 if (IS_ERR(meson_dw_hdmi->hdmitx_phy)) { in meson_dw_hdmi_bind()
1012 return PTR_ERR(meson_dw_hdmi->hdmitx_phy); in meson_dw_hdmi_bind()
1016 meson_dw_hdmi->hdmitx = devm_ioremap_resource(dev, res); in meson_dw_hdmi_bind()
1017 if (IS_ERR(meson_dw_hdmi->hdmitx)) in meson_dw_hdmi_bind()
1018 return PTR_ERR(meson_dw_hdmi->hdmitx); in meson_dw_hdmi_bind()
1020 meson_dw_hdmi->hdmi_pclk = devm_clk_get(dev, "isfr"); in meson_dw_hdmi_bind()
1021 if (IS_ERR(meson_dw_hdmi->hdmi_pclk)) { in meson_dw_hdmi_bind()
1023 return PTR_ERR(meson_dw_hdmi->hdmi_pclk); in meson_dw_hdmi_bind()
1025 clk_prepare_enable(meson_dw_hdmi->hdmi_pclk); in meson_dw_hdmi_bind()
1027 meson_dw_hdmi->venci_clk = devm_clk_get(dev, "venci"); in meson_dw_hdmi_bind()
1028 if (IS_ERR(meson_dw_hdmi->venci_clk)) { in meson_dw_hdmi_bind()
1030 return PTR_ERR(meson_dw_hdmi->venci_clk); in meson_dw_hdmi_bind()
1032 clk_prepare_enable(meson_dw_hdmi->venci_clk); in meson_dw_hdmi_bind()
1034 dw_plat_data->regm = devm_regmap_init(dev, NULL, meson_dw_hdmi, in meson_dw_hdmi_bind()
1036 if (IS_ERR(dw_plat_data->regm)) in meson_dw_hdmi_bind()
1037 return PTR_ERR(dw_plat_data->regm); in meson_dw_hdmi_bind()
1056 dev_err(priv->dev, "Failed to init HDMI encoder\n"); in meson_dw_hdmi_bind()
1060 meson_dw_hdmi->bridge.funcs = &meson_venc_hdmi_encoder_bridge_funcs; in meson_dw_hdmi_bind()
1061 drm_bridge_attach(encoder, &meson_dw_hdmi->bridge, NULL, 0); in meson_dw_hdmi_bind()
1063 encoder->possible_crtcs = BIT(0); in meson_dw_hdmi_bind()
1071 dw_plat_data->priv_data = meson_dw_hdmi; in meson_dw_hdmi_bind()
1072 dw_plat_data->mode_valid = dw_hdmi_mode_valid; in meson_dw_hdmi_bind()
1073 dw_plat_data->phy_ops = &meson_dw_hdmi_phy_ops; in meson_dw_hdmi_bind()
1074 dw_plat_data->phy_name = "meson_dw_hdmi_phy"; in meson_dw_hdmi_bind()
1075 dw_plat_data->phy_data = meson_dw_hdmi; in meson_dw_hdmi_bind()
1076 dw_plat_data->input_bus_encoding = V4L2_YCBCR_ENC_709; in meson_dw_hdmi_bind()
1077 dw_plat_data->ycbcr_420_allowed = true; in meson_dw_hdmi_bind()
1079 if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || in meson_dw_hdmi_bind()
1080 dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || in meson_dw_hdmi_bind()
1081 dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) in meson_dw_hdmi_bind()
1082 dw_plat_data->use_drm_infoframe = true; in meson_dw_hdmi_bind()
1086 meson_dw_hdmi->hdmi = dw_hdmi_probe(pdev, in meson_dw_hdmi_bind()
1087 &meson_dw_hdmi->dw_plat_data); in meson_dw_hdmi_bind()
1088 if (IS_ERR(meson_dw_hdmi->hdmi)) in meson_dw_hdmi_bind()
1089 return PTR_ERR(meson_dw_hdmi->hdmi); in meson_dw_hdmi_bind()
1091 next_bridge = of_drm_find_bridge(pdev->dev.of_node); in meson_dw_hdmi_bind()
1094 &meson_dw_hdmi->bridge, 0); in meson_dw_hdmi_bind()
1106 dw_hdmi_unbind(meson_dw_hdmi->hdmi); in meson_dw_hdmi_unbind()
1122 meson_dw_hdmi->data->top_write(meson_dw_hdmi, in meson_dw_hdmi_pm_suspend()
1137 dw_hdmi_resume(meson_dw_hdmi->hdmi); in meson_dw_hdmi_pm_resume()
1144 return component_add(&pdev->dev, &meson_dw_hdmi_ops); in meson_dw_hdmi_probe()
1149 component_del(&pdev->dev, &meson_dw_hdmi_ops); in meson_dw_hdmi_remove()
1160 { .compatible = "amlogic,meson-gxbb-dw-hdmi",
1162 { .compatible = "amlogic,meson-gxl-dw-hdmi",
1164 { .compatible = "amlogic,meson-gxm-dw-hdmi",
1166 { .compatible = "amlogic,meson-g12a-dw-hdmi",