62 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,  in sif_set_bit()  argument
65 	writel(readl(ddc->regs + offset) | val, ddc->regs + offset);  in sif_set_bit()
68 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset,  in sif_clr_bit()  argument
71 	writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset);  in sif_clr_bit()
74 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset,  in sif_bit_is_set()  argument
77 	return (readl(ddc->regs + offset) & val) == val;  in sif_bit_is_set()
80 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset,  in sif_write_mask()  argument
86 	tmp = readl(ddc->regs + offset);  in sif_write_mask()
89 	writel(tmp, ddc->regs + offset);  in sif_write_mask()
92 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc,  in sif_read_mask()  argument
96 	return (readl(ddc->regs + offset) & mask) >> shift;  in sif_read_mask()
99 static void ddcm_trigger_mode(struct mtk_hdmi_ddc *ddc, int mode)  in ddcm_trigger_mode()  argument
103 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_SIF_MODE_MASK,  in ddcm_trigger_mode()
105 	sif_set_bit(ddc, DDC_DDCMCTL1, DDCM_TRI);  in ddcm_trigger_mode()
106 	readl_poll_timeout(ddc->regs + DDC_DDCMCTL1, val,  in ddcm_trigger_mode()
110 static int mtk_hdmi_ddc_read_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)  in mtk_hdmi_ddc_read_msg()  argument
112 	struct device *dev = ddc->adap.dev.parent;  in mtk_hdmi_ddc_read_msg()
118 	ddcm_trigger_mode(ddc, DDCM_START);  in mtk_hdmi_ddc_read_msg()
119 	sif_write_mask(ddc, DDC_DDCMD0, 0xff, 0, (msg->addr << 1) | 0x01);  in mtk_hdmi_ddc_read_msg()
120 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,  in mtk_hdmi_ddc_read_msg()
122 	ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);  in mtk_hdmi_ddc_read_msg()
123 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);  in mtk_hdmi_ddc_read_msg()
144 		sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK,  in mtk_hdmi_ddc_read_msg()
146 		ddcm_trigger_mode(ddc, (ack_final == 1) ?  in mtk_hdmi_ddc_read_msg()
150 		ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK,  in mtk_hdmi_ddc_read_msg()
173 			msg->buf[index + i - 1] = sif_read_mask(ddc, offset,  in mtk_hdmi_ddc_read_msg()
185 static int mtk_hdmi_ddc_write_msg(struct mtk_hdmi_ddc *ddc, struct i2c_msg *msg)  in mtk_hdmi_ddc_write_msg()  argument
187 	struct device *dev = ddc->adap.dev.parent;  in mtk_hdmi_ddc_write_msg()
190 	ddcm_trigger_mode(ddc, DDCM_START);  in mtk_hdmi_ddc_write_msg()
191 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA0, 0, msg->addr << 1);  in mtk_hdmi_ddc_write_msg()
192 	sif_write_mask(ddc, DDC_DDCMD0, DDCM_DATA1, 8, msg->buf[0]);  in mtk_hdmi_ddc_write_msg()
193 	sif_write_mask(ddc, DDC_DDCMCTL1, DDCM_PGLEN_MASK, DDCM_PGLEN_OFFSET,  in mtk_hdmi_ddc_write_msg()
195 	ddcm_trigger_mode(ddc, DDCM_WRITE_DATA);  in mtk_hdmi_ddc_write_msg()
197 	ack = sif_read_mask(ddc, DDC_DDCMCTL1, DDCM_ACK_MASK, DDCM_ACK_OFFSET);  in mtk_hdmi_ddc_write_msg()
211 	struct mtk_hdmi_ddc *ddc = adapter->algo_data;  in mtk_hdmi_ddc_xfer()  local
216 	if (!ddc) {  in mtk_hdmi_ddc_xfer()
221 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SCL_STRECH);  in mtk_hdmi_ddc_xfer()
222 	sif_set_bit(ddc, DDC_DDCMCTL0, DDCM_SM0EN);  in mtk_hdmi_ddc_xfer()
223 	sif_clr_bit(ddc, DDC_DDCMCTL0, DDCM_ODRAIN);  in mtk_hdmi_ddc_xfer()
225 	if (sif_bit_is_set(ddc, DDC_DDCMCTL1, DDCM_TRI)) {  in mtk_hdmi_ddc_xfer()
226 		dev_err(dev, "ddc line is busy!\n");  in mtk_hdmi_ddc_xfer()
230 	sif_write_mask(ddc, DDC_DDCMCTL0, DDCM_CLK_DIV_MASK,  in mtk_hdmi_ddc_xfer()
240 			ret = mtk_hdmi_ddc_read_msg(ddc, msg);  in mtk_hdmi_ddc_xfer()
242 			ret = mtk_hdmi_ddc_write_msg(ddc, msg);  in mtk_hdmi_ddc_xfer()
247 	ddcm_trigger_mode(ddc, DDCM_STOP);  in mtk_hdmi_ddc_xfer()
252 	ddcm_trigger_mode(ddc, DDCM_STOP);  in mtk_hdmi_ddc_xfer()
253 	dev_err(dev, "ddc failed!\n");  in mtk_hdmi_ddc_xfer()
270 	struct mtk_hdmi_ddc *ddc;  in mtk_hdmi_ddc_probe()  local
274 	ddc = devm_kzalloc(dev, sizeof(struct mtk_hdmi_ddc), GFP_KERNEL);  in mtk_hdmi_ddc_probe()
275 	if (!ddc)  in mtk_hdmi_ddc_probe()
278 	ddc->clk = devm_clk_get(dev, "ddc-i2c");  in mtk_hdmi_ddc_probe()
279 	if (IS_ERR(ddc->clk)) {  in mtk_hdmi_ddc_probe()
280 		dev_err(dev, "get ddc_clk failed: %p ,\n", ddc->clk);  in mtk_hdmi_ddc_probe()
281 		return PTR_ERR(ddc->clk);  in mtk_hdmi_ddc_probe()
285 	ddc->regs = devm_ioremap_resource(&pdev->dev, mem);  in mtk_hdmi_ddc_probe()
286 	if (IS_ERR(ddc->regs))  in mtk_hdmi_ddc_probe()
287 		return PTR_ERR(ddc->regs);  in mtk_hdmi_ddc_probe()
289 	ret = clk_prepare_enable(ddc->clk);  in mtk_hdmi_ddc_probe()
291 		dev_err(dev, "enable ddc clk failed!\n");  in mtk_hdmi_ddc_probe()
295 	strlcpy(ddc->adap.name, "mediatek-hdmi-ddc", sizeof(ddc->adap.name));  in mtk_hdmi_ddc_probe()
296 	ddc->adap.owner = THIS_MODULE;  in mtk_hdmi_ddc_probe()
297 	ddc->adap.class = I2C_CLASS_DDC;  in mtk_hdmi_ddc_probe()
298 	ddc->adap.algo = &mtk_hdmi_ddc_algorithm;  in mtk_hdmi_ddc_probe()
299 	ddc->adap.retries = 3;  in mtk_hdmi_ddc_probe()
300 	ddc->adap.dev.of_node = dev->of_node;  in mtk_hdmi_ddc_probe()
301 	ddc->adap.algo_data = ddc;  in mtk_hdmi_ddc_probe()
302 	ddc->adap.dev.parent = &pdev->dev;  in mtk_hdmi_ddc_probe()
304 	ret = i2c_add_adapter(&ddc->adap);  in mtk_hdmi_ddc_probe()
310 	platform_set_drvdata(pdev, ddc);  in mtk_hdmi_ddc_probe()
312 	dev_dbg(dev, "ddc->adap: %p\n", &ddc->adap);  in mtk_hdmi_ddc_probe()
313 	dev_dbg(dev, "ddc->clk: %p\n", ddc->clk);  in mtk_hdmi_ddc_probe()
320 	clk_disable_unprepare(ddc->clk);  in mtk_hdmi_ddc_probe()
326 	struct mtk_hdmi_ddc *ddc = platform_get_drvdata(pdev);  in mtk_hdmi_ddc_remove()  local
328 	i2c_del_adapter(&ddc->adap);  in mtk_hdmi_ddc_remove()
329 	clk_disable_unprepare(ddc->clk);  in mtk_hdmi_ddc_remove()
335 	{ .compatible = "mediatek,mt8173-hdmi-ddc", },
343 		.name = "mediatek-hdmi-ddc",
349 MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");