Lines Matching full:bit
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
17 #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(9)
18 #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC BIT(10)
19 #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM BIT(11)
20 #define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN BIT(12)
21 #define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN BIT(13)
22 #define DSI_MCTL_MAIN_DATA_CTL_DLX_REMAP_EN BIT(14)
23 #define DSI_MCTL_MAIN_DATA_CTL_TE_POLLING_EN BIT(15)
26 #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0)
27 #define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE BIT(1)
28 #define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS BIT(2)
29 #define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN BIT(3)
30 #define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN BIT(4)
31 #define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN BIT(5)
34 #define DSI_MCTL_MAIN_PHY_CTL_CLOCK_FORCE_STOP_MODE BIT(10)
54 #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK BIT(0)
55 #define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK BIT(1)
56 #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1 BIT(2)
57 #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1 BIT(3)
58 #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2 BIT(4)
59 #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2 BIT(5)
64 #define DSI_MCTL_MAIN_EN_PLL_START BIT(0)
65 #define DSI_MCTL_MAIN_EN_CKLANE_EN BIT(3)
66 #define DSI_MCTL_MAIN_EN_DAT1_EN BIT(4)
67 #define DSI_MCTL_MAIN_EN_DAT2_EN BIT(5)
68 #define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ BIT(6)
69 #define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ BIT(7)
70 #define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ BIT(8)
71 #define DSI_MCTL_MAIN_EN_IF1_EN BIT(9)
72 #define DSI_MCTL_MAIN_EN_IF2_EN BIT(10)
75 #define DSI_MCTL_MAIN_STS_PLL_LOCK BIT(0)
76 #define DSI_MCTL_MAIN_STS_CLKLANE_READY BIT(1)
77 #define DSI_MCTL_MAIN_STS_DAT1_READY BIT(2)
78 #define DSI_MCTL_MAIN_STS_DAT2_READY BIT(3)
79 #define DSI_MCTL_MAIN_STS_HSTX_TO_ERR BIT(4)
80 #define DSI_MCTL_MAIN_STS_LPRX_TO_ERR BIT(5)
81 #define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK BIT(6)
82 #define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK BIT(7)
96 #define DSI_CMD_MODE_CTL_IF1_LP_EN BIT(4)
97 #define DSI_CMD_MODE_CTL_IF2_LP_EN BIT(5)
98 #define DSI_CMD_MODE_CTL_ARB_MODE BIT(6)
99 #define DSI_CMD_MODE_CTL_ARB_PRI BIT(7)
106 #define DSI_CMD_MODE_STS_ERR_NO_TE BIT(0)
107 #define DSI_CMD_MODE_STS_ERR_TE_MISS BIT(1)
108 #define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN BIT(2)
109 #define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN BIT(3)
110 #define DSI_CMD_MODE_STS_ERR_UNWANTED_RD BIT(4)
111 #define DSI_CMD_MODE_STS_CSM_RUNNING BIT(5)
123 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT BIT(3)
128 #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN BIT(21)
133 #define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION BIT(0)
134 #define DSI_DIRECT_CMD_STS_WRITE_COMPLETED BIT(1)
135 #define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED BIT(2)
136 #define DSI_DIRECT_CMD_STS_READ_COMPLETED BIT(3)
137 #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT BIT(4)
138 #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED BIT(5)
139 #define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED BIT(6)
140 #define DSI_DIRECT_CMD_STS_TE_RECEIVED BIT(7)
141 #define DSI_DIRECT_CMD_STS_BTA_COMPLETED BIT(8)
142 #define DSI_DIRECT_CMD_STS_BTA_FINISHED BIT(9)
143 #define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR BIT(10)
180 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS BIT(12)
181 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE BIT(13)
182 #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS (BIT(12) | BIT(13))
183 #define DSI_VID_MAIN_CTL_BURST_MODE BIT(14)
184 #define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE BIT(15)
185 #define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL BIT(16)
187 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING BIT(17)
188 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 BIT(18)
189 #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 (BIT(17) | BIT(18))
191 #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING BIT(19)
192 #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 BIT(20)
193 #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 (BIT(19) | BIT(20))
240 #define DSI_VID_MODE_STS_VSG_RUNNING BIT(0)
241 #define DSI_VID_MODE_STS_ERR_MISSING_DATA BIT(1)
242 #define DSI_VID_MODE_STS_ERR_MISSING_HSYNC BIT(2)
243 #define DSI_VID_MODE_STS_ERR_MISSING_VSYNC BIT(3)
244 #define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH BIT(4)
245 #define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT BIT(5)
246 #define DSI_VID_MODE_STS_ERR_BURSTWRITE BIT(6)
247 #define DSI_VID_MODE_STS_ERR_LINEWRITE BIT(7)
248 #define DSI_VID_MODE_STS_ERR_LONGREAD BIT(8)
249 #define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH BIT(9)
250 #define DSI_VID_MODE_STS_VSG_RECOVERY BIT(10)
255 #define DSI_VID_VCA_SETTING1_BURST_LP BIT(16)
264 #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN BIT(0)
265 #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN BIT(1)
266 #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN BIT(2)
267 #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN BIT(3)
268 #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN BIT(4)
269 #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN BIT(5)
270 #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE BIT(16)
271 #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE BIT(17)
272 #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE BIT(18)
273 #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE BIT(19)
274 #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE BIT(20)
275 #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE BIT(21)
278 #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN BIT(0)
279 #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN BIT(1)
280 #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN BIT(2)
281 #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN BIT(3)
282 #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN BIT(4)
283 #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN BIT(5)
284 #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN BIT(6)
285 #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN BIT(7)
286 #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN BIT(8)
287 #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN BIT(9)
288 #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN BIT(10)
289 #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE BIT(16)
290 #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE BIT(17)
291 #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE BIT(18)
292 #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE BIT(19)
293 #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE BIT(20)
294 #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE BIT(21)
295 #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE BIT(22)
296 #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE BIT(23)
297 #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE BIT(24)
298 #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE BIT(25)
299 #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE BIT(26)
302 #define DSI_VID_MODE_STS_CTL_VSG_RUNNING BIT(0)
303 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA BIT(1)
304 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC BIT(2)
305 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC BIT(3)
306 #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH BIT(4)
307 #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT BIT(5)
308 #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE BIT(6)
309 #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE BIT(7)
310 #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD BIT(8)
311 #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH BIT(9)
312 #define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE BIT(16)
313 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE BIT(17)
314 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE BIT(18)
315 #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE BIT(19)
316 #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE BIT(20)
317 #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE BIT(21)
318 #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE BIT(22)
319 #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE BIT(23)
320 #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE BIT(24)
321 #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE BIT(25)
322 #define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE BIT(26)
329 #define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR BIT(0)
330 #define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR BIT(1)
331 #define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR BIT(2)
332 #define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR BIT(3)
333 #define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR BIT(4)
334 #define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR BIT(5)
337 #define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR BIT(0)
338 #define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR BIT(1)
339 #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR BIT(2)
340 #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR BIT(3)
341 #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR BIT(4)
342 #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR BIT(5)
343 #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR BIT(6)
344 #define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR BIT(7)
345 #define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR BIT(8)
346 #define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR BIT(9)
347 #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR BIT(10)
363 #define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1 BIT(2)
364 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1 BIT(3)
365 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1 BIT(4)
366 #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1 BIT(5)
374 #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 BIT(12)
375 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK BIT(13)
376 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK BIT(14)
377 #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK BIT(15)
378 #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2 BIT(16)
379 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2 BIT(18)
380 #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2 BIT(19)
381 #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2 BIT(20)