Lines Matching refs:val
70 u32 val; in mcde_dsi_irq() local
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
78 if (val) in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
80 if (val & DSI_DIRECT_CMD_STS_WRITE_COMPLETED) in mcde_dsi_irq()
82 if (val & DSI_DIRECT_CMD_STS_TE_RECEIVED) { in mcde_dsi_irq()
86 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) in mcde_dsi_irq()
88 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) in mcde_dsi_irq()
91 writel(val, d->regs + DSI_DIRECT_CMD_STS_CLR); in mcde_dsi_irq()
93 val = readl(d->regs + DSI_CMD_MODE_STS_FLAG); in mcde_dsi_irq()
94 if (val) in mcde_dsi_irq()
95 dev_dbg(d->dev, "DSI_CMD_MODE_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
96 if (val & DSI_CMD_MODE_STS_ERR_NO_TE) in mcde_dsi_irq()
99 if (val & DSI_CMD_MODE_STS_ERR_TE_MISS) in mcde_dsi_irq()
102 if (val & DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN) in mcde_dsi_irq()
104 if (val & DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN) in mcde_dsi_irq()
106 if (val & DSI_CMD_MODE_STS_ERR_UNWANTED_RD) in mcde_dsi_irq()
108 writel(val, d->regs + DSI_CMD_MODE_STS_CLR); in mcde_dsi_irq()
110 val = readl(d->regs + DSI_DIRECT_CMD_RD_STS_FLAG); in mcde_dsi_irq()
111 if (val) in mcde_dsi_irq()
112 dev_dbg(d->dev, "DSI_DIRECT_CMD_RD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
113 writel(val, d->regs + DSI_DIRECT_CMD_RD_STS_CLR); in mcde_dsi_irq()
115 val = readl(d->regs + DSI_TG_STS_FLAG); in mcde_dsi_irq()
116 if (val) in mcde_dsi_irq()
117 dev_dbg(d->dev, "DSI_TG_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
118 writel(val, d->regs + DSI_TG_STS_CLR); in mcde_dsi_irq()
120 val = readl(d->regs + DSI_VID_MODE_STS_FLAG); in mcde_dsi_irq()
121 if (val) in mcde_dsi_irq()
122 dev_dbg(d->dev, "DSI_VID_MODE_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
123 if (val & DSI_VID_MODE_STS_VSG_RUNNING) in mcde_dsi_irq()
125 if (val & DSI_VID_MODE_STS_ERR_MISSING_DATA) in mcde_dsi_irq()
127 if (val & DSI_VID_MODE_STS_ERR_MISSING_HSYNC) in mcde_dsi_irq()
129 if (val & DSI_VID_MODE_STS_ERR_MISSING_VSYNC) in mcde_dsi_irq()
131 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH) in mcde_dsi_irq()
133 if (val & DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT) in mcde_dsi_irq()
135 if (val & (DSI_VID_MODE_STS_ERR_BURSTWRITE | in mcde_dsi_irq()
139 if (val & DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH) in mcde_dsi_irq()
141 if (val & DSI_VID_MODE_STS_VSG_RECOVERY) in mcde_dsi_irq()
143 writel(val, d->regs + DSI_VID_MODE_STS_CLR); in mcde_dsi_irq()
219 u32 val; in mcde_dsi_execute_transfer() local
254 val = readl(d->regs + DSI_DIRECT_CMD_STS); in mcde_dsi_execute_transfer()
255 if (val & DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR) { in mcde_dsi_execute_transfer()
260 if (val & DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED) { in mcde_dsi_execute_transfer()
261 val >>= DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT; in mcde_dsi_execute_transfer()
263 val); in mcde_dsi_execute_transfer()
302 u32 val; in mcde_dsi_host_transfer() local
324 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ; in mcde_dsi_host_transfer()
326 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE; in mcde_dsi_host_transfer()
334 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT; in mcde_dsi_host_transfer()
335 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; in mcde_dsi_host_transfer()
336 val |= txlen << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; in mcde_dsi_host_transfer()
337 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; in mcde_dsi_host_transfer()
338 val |= msg->type << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT; in mcde_dsi_host_transfer()
339 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); in mcde_dsi_host_transfer()
343 val = 0; in mcde_dsi_host_transfer()
345 val |= tx[i] << (i * 8); in mcde_dsi_host_transfer()
347 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT0); in mcde_dsi_host_transfer()
349 val = 0; in mcde_dsi_host_transfer()
351 val |= tx[i + 4] << (i * 8); in mcde_dsi_host_transfer()
352 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT1); in mcde_dsi_host_transfer()
355 val = 0; in mcde_dsi_host_transfer()
357 val |= tx[i + 8] << (i * 8); in mcde_dsi_host_transfer()
358 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT2); in mcde_dsi_host_transfer()
361 val = 0; in mcde_dsi_host_transfer()
363 val |= tx[i + 12] << (i * 8); in mcde_dsi_host_transfer()
364 writel(val, d->regs + DSI_DIRECT_CMD_WRDAT3); in mcde_dsi_host_transfer()
393 u32 val; in mcde_dsi_te_request() local
398 val = DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ; in mcde_dsi_te_request()
399 val |= 0 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT; in mcde_dsi_te_request()
400 val |= 2 << DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT; in mcde_dsi_te_request()
401 val |= DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN; in mcde_dsi_te_request()
402 val |= MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM << in mcde_dsi_te_request()
404 writel(val, d->regs + DSI_DIRECT_CMD_MAIN_SETTINGS); in mcde_dsi_te_request()
410 val = readl(d->regs + DSI_DIRECT_CMD_STS_CTL); in mcde_dsi_te_request()
411 val |= DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN; in mcde_dsi_te_request()
412 val |= DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN; in mcde_dsi_te_request()
413 writel(val, d->regs + DSI_DIRECT_CMD_STS_CTL); in mcde_dsi_te_request()
419 val = readl(d->regs + DSI_CMD_MODE_STS_CTL); in mcde_dsi_te_request()
420 val |= DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN; in mcde_dsi_te_request()
421 val |= DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN; in mcde_dsi_te_request()
422 writel(val, d->regs + DSI_CMD_MODE_STS_CTL); in mcde_dsi_te_request()
439 u32 val; in mcde_dsi_setup_video_mode() local
441 val = 0; in mcde_dsi_setup_video_mode()
443 val |= DSI_VID_MAIN_CTL_BURST_MODE; in mcde_dsi_setup_video_mode()
445 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE; in mcde_dsi_setup_video_mode()
446 val |= DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL; in mcde_dsi_setup_video_mode()
451 val |= MIPI_DSI_PACKED_PIXEL_STREAM_16 << in mcde_dsi_setup_video_mode()
453 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS; in mcde_dsi_setup_video_mode()
456 val |= MIPI_DSI_PACKED_PIXEL_STREAM_18 << in mcde_dsi_setup_video_mode()
458 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS; in mcde_dsi_setup_video_mode()
461 val |= MIPI_DSI_PIXEL_STREAM_3BYTE_18 in mcde_dsi_setup_video_mode()
463 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE; in mcde_dsi_setup_video_mode()
466 val |= MIPI_DSI_PACKED_PIXEL_STREAM_24 << in mcde_dsi_setup_video_mode()
468 val |= DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS; in mcde_dsi_setup_video_mode()
485 val |= DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0; in mcde_dsi_setup_video_mode()
490 val |= DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0; in mcde_dsi_setup_video_mode()
492 val |= 1 << DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT; in mcde_dsi_setup_video_mode()
494 writel(val, d->regs + DSI_VID_MAIN_CTL); in mcde_dsi_setup_video_mode()
497 val = mode->vdisplay << DSI_VID_VSIZE_VACT_LENGTH_SHIFT; in mcde_dsi_setup_video_mode()
499 val |= (mode->vsync_start - mode->vdisplay) in mcde_dsi_setup_video_mode()
502 val |= (mode->vsync_end - mode->vsync_start) in mcde_dsi_setup_video_mode()
505 val |= (mode->vtotal - mode->vsync_end) in mcde_dsi_setup_video_mode()
507 writel(val, d->regs + DSI_VID_VSIZE); in mcde_dsi_setup_video_mode()
562 val = hsa << DSI_VID_HSIZE1_HSA_LENGTH_SHIFT; in mcde_dsi_setup_video_mode()
564 val |= hbp << DSI_VID_HSIZE1_HBP_LENGTH_SHIFT; in mcde_dsi_setup_video_mode()
566 val |= hfp << DSI_VID_HSIZE1_HFP_LENGTH_SHIFT; in mcde_dsi_setup_video_mode()
567 writel(val, d->regs + DSI_VID_HSIZE1); in mcde_dsi_setup_video_mode()
570 val = mode->hdisplay * cpp; in mcde_dsi_setup_video_mode()
571 writel(val, d->regs + DSI_VID_HSIZE2); in mcde_dsi_setup_video_mode()
572 dev_dbg(d->dev, "RGB length, visible area on a line: %u bytes\n", val); in mcde_dsi_setup_video_mode()
626 val = blkline_pck << DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT; in mcde_dsi_setup_video_mode()
627 writel(val, d->regs + DSI_VID_BLKSIZE2); in mcde_dsi_setup_video_mode()
636 val = blkline_pck << DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT; in mcde_dsi_setup_video_mode()
637 val &= DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK; in mcde_dsi_setup_video_mode()
638 writel(val, d->regs + DSI_VID_BLKSIZE1); in mcde_dsi_setup_video_mode()
657 val = line_duration << DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT; in mcde_dsi_setup_video_mode()
664 val |= 48 << DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT; in mcde_dsi_setup_video_mode()
665 writel(val, d->regs + DSI_VID_DPHY_TIME); in mcde_dsi_setup_video_mode()
696 val = readl(d->regs + DSI_VID_BLKSIZE1); in mcde_dsi_setup_video_mode()
697 val &= ~DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK; in mcde_dsi_setup_video_mode()
698 val |= blkeol_pck << DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT; in mcde_dsi_setup_video_mode()
699 writel(val, d->regs + DSI_VID_BLKSIZE1); in mcde_dsi_setup_video_mode()
701 val = blkeol_pck << in mcde_dsi_setup_video_mode()
703 val &= DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK; in mcde_dsi_setup_video_mode()
704 writel(val, d->regs + DSI_VID_VCA_SETTING2); in mcde_dsi_setup_video_mode()
726 val = readl(d->regs + DSI_VID_PCK_TIME); in mcde_dsi_setup_video_mode()
727 val &= ~DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK; in mcde_dsi_setup_video_mode()
728 val |= blkeol_duration << in mcde_dsi_setup_video_mode()
730 writel(val, d->regs + DSI_VID_PCK_TIME); in mcde_dsi_setup_video_mode()
733 val = readl(d->regs + DSI_VID_VCA_SETTING1); in mcde_dsi_setup_video_mode()
734 val &= ~DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK; in mcde_dsi_setup_video_mode()
735 val |= (blkeol_pck - 6) << in mcde_dsi_setup_video_mode()
737 writel(val, d->regs + DSI_VID_VCA_SETTING1); in mcde_dsi_setup_video_mode()
741 val = readl(d->regs + DSI_VID_VCA_SETTING2); in mcde_dsi_setup_video_mode()
742 val &= ~DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK; in mcde_dsi_setup_video_mode()
743 val |= (blkline_pck - 6) << in mcde_dsi_setup_video_mode()
745 writel(val, d->regs + DSI_VID_VCA_SETTING2); in mcde_dsi_setup_video_mode()
752 u32 val; in mcde_dsi_start() local
759 val = DSI_MCTL_MAIN_DATA_CTL_LINK_EN | in mcde_dsi_start()
764 val |= DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN; in mcde_dsi_start()
765 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_start()
768 val = 0x3ff << DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT; in mcde_dsi_start()
769 writel(val, d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_start()
778 val = 4000 / hs_freq; in mcde_dsi_start()
779 dev_dbg(d->dev, "UI value: %d\n", val); in mcde_dsi_start()
780 val <<= DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT; in mcde_dsi_start()
781 val &= DSI_MCTL_DPHY_STATIC_UI_X4_MASK; in mcde_dsi_start()
782 writel(val, d->regs + DSI_MCTL_DPHY_STATIC); in mcde_dsi_start()
790 val = 0x0f << DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT; in mcde_dsi_start()
792 val |= DSI_MCTL_MAIN_PHY_CTL_LANE2_EN; in mcde_dsi_start()
794 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS; in mcde_dsi_start()
795 val |= DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN | in mcde_dsi_start()
798 writel(val, d->regs + DSI_MCTL_MAIN_PHY_CTL); in mcde_dsi_start()
800 val = (1 << DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT) | in mcde_dsi_start()
802 writel(val, d->regs + DSI_MCTL_ULPOUT_TIME); in mcde_dsi_start()
808 val = (0x0f << DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT) | in mcde_dsi_start()
811 writel(val, d->regs + DSI_MCTL_DPHY_TIMEOUT); in mcde_dsi_start()
813 val = DSI_MCTL_MAIN_EN_PLL_START | in mcde_dsi_start()
818 val |= DSI_MCTL_MAIN_EN_DAT2_EN; in mcde_dsi_start()
819 writel(val, d->regs + DSI_MCTL_MAIN_EN); in mcde_dsi_start()
823 val = DSI_MCTL_MAIN_STS_PLL_LOCK | in mcde_dsi_start()
827 val |= DSI_MCTL_MAIN_STS_DAT2_READY; in mcde_dsi_start()
828 while ((readl(d->regs + DSI_MCTL_MAIN_STS) & val) != val) { in mcde_dsi_start()
840 val = readl(d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_start()
846 val |= DSI_CMD_MODE_CTL_IF1_LP_EN; in mcde_dsi_start()
847 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; in mcde_dsi_start()
848 writel(val, d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_start()
863 u32 val; in mcde_dsi_enable() local
923 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_enable()
924 val |= DSI_MCTL_MAIN_DATA_CTL_IF1_MODE; in mcde_dsi_enable()
925 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_enable()
928 val = readl(d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_enable()
929 val &= ~DSI_CMD_MODE_CTL_IF1_LP_EN; in mcde_dsi_enable()
930 writel(val, d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_enable()
933 val = readl(d->regs + DSI_VID_MODE_STS_CTL); in mcde_dsi_enable()
934 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; in mcde_dsi_enable()
935 val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; in mcde_dsi_enable()
936 writel(val, d->regs + DSI_VID_MODE_STS_CTL); in mcde_dsi_enable()
939 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_enable()
940 val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; in mcde_dsi_enable()
941 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_enable()
944 val = readl(d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_enable()
950 val |= DSI_CMD_MODE_CTL_IF1_LP_EN; in mcde_dsi_enable()
951 val &= ~DSI_CMD_MODE_CTL_IF1_ID_MASK; in mcde_dsi_enable()
952 writel(val, d->regs + DSI_CMD_MODE_CTL); in mcde_dsi_enable()
979 u32 val; in mcde_dsi_wait_for_command_mode_stop() local
987 val = DSI_CMD_MODE_STS_CSM_RUNNING; in mcde_dsi_wait_for_command_mode_stop()
988 while ((readl(d->regs + DSI_CMD_MODE_STS) & val) == val) { in mcde_dsi_wait_for_command_mode_stop()
1001 u32 val; in mcde_dsi_wait_for_video_mode_stop() local
1006 val = DSI_VID_MODE_STS_VSG_RUNNING; in mcde_dsi_wait_for_video_mode_stop()
1007 while ((readl(d->regs + DSI_VID_MODE_STS) & val) == val) { in mcde_dsi_wait_for_video_mode_stop()
1025 u32 val; in mcde_dsi_disable() local
1029 val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_disable()
1030 val &= ~DSI_MCTL_MAIN_DATA_CTL_VID_EN; in mcde_dsi_disable()
1031 writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); in mcde_dsi_disable()