103 				 u32 guc_wopcm_base, u32 guc_wopcm_size)  in gen9_check_dword_gap()  argument
112 	offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;  in gen9_check_dword_gap()
145 				  u32 guc_wopcm_base, u32 guc_wopcm_size,  in check_hw_restrictions()  argument
148 	if (IS_GEN(i915, 9) && !gen9_check_dword_gap(i915, guc_wopcm_base,  in check_hw_restrictions()
160 			   u32 guc_wopcm_base, u32 guc_wopcm_size,  in __check_layout()  argument
167 	if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {  in __check_layout()
170 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,  in __check_layout()
184 	if (unlikely(guc_wopcm_base < size)) {  in __check_layout()
187 			guc_wopcm_base / SZ_1K, size / SZ_1K);  in __check_layout()
191 	return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,  in __check_layout()
196 				u32 *guc_wopcm_base, u32 *guc_wopcm_size)  in __wopcm_regs_locked()  argument
205 	*guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;  in __wopcm_regs_locked()
227 	u32 guc_wopcm_base;  in intel_wopcm_init()  local
243 	if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {  in intel_wopcm_init()
245 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);  in intel_wopcm_init()
253 	guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;  in intel_wopcm_init()
254 	guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);  in intel_wopcm_init()
260 	guc_wopcm_base = min(guc_wopcm_base, wopcm->size - ctx_rsvd);  in intel_wopcm_init()
263 	guc_wopcm_size = wopcm->size - ctx_rsvd - guc_wopcm_base;  in intel_wopcm_init()
267 		guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);  in intel_wopcm_init()
270 	if (__check_layout(i915, wopcm->size, guc_wopcm_base, guc_wopcm_size,  in intel_wopcm_init()
272 		wopcm->guc.base = guc_wopcm_base;  in intel_wopcm_init()