821 	return dev_priv->wm.max_level + 1;  in intel_wm_num_levels()
1087 	dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;  in g4x_setup_wm_latency()
1319 	if (level > dev_priv->wm.max_level)  in g4x_raw_crtc_wm_is_valid()
1647 	dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;  in vlv_setup_wm_latency()
1653 		dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;  in vlv_setup_wm_latency()
2152 	wm->level = dev_priv->wm.max_level;  in vlv_merge_wm()
2856 		int level, max_level = ilk_wm_max_level(dev_priv);  in intel_read_wm_latency()  local
2902 		for (level = 1; level <= max_level; level++) {  in intel_read_wm_latency()
2904 				for (i = level + 1; i <= max_level; i++)  in intel_read_wm_latency()
2919 			for (level = 1; level <= max_level; level++) {  in intel_read_wm_latency()
2997 	int level, max_level = ilk_wm_max_level(dev_priv);  in intel_print_wm_latency()  local
2999 	for (level = 0; level <= max_level; level++) {  in intel_print_wm_latency()
3027 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_increase_wm_latency()  local
3033 	for (level = 1; level <= max_level; level++)  in ilk_increase_wm_latency()
3152 	int level, max_level = ilk_wm_max_level(dev_priv), usable_level;  in ilk_compute_pipe_wm()  local
3174 	usable_level = max_level;  in ilk_compute_pipe_wm()
3228 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_compute_intermediate_wm()  local
3244 	for (level = 0; level <= max_level; level++) {  in ilk_compute_intermediate_wm()
3315 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_wm_merge()  local
3316 	int last_enabled_level = max_level;  in ilk_wm_merge()
3327 	for (level = 1; level <= max_level; level++) {  in ilk_wm_merge()
3357 		for (level = 2; level <= max_level; level++) {  in ilk_wm_merge()
3453 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_find_best_result()  local
3456 	for (level = 1; level <= max_level; level++) {  in ilk_find_best_result()
4262 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_cursor_allocation()  local
4274 	for (level = 0; level <= max_level; level++) {  in skl_cursor_allocation()
5384 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_compute_wm_levels()  local
5387 	for (level = 0; level <= max_level; level++) {  in skl_compute_wm_levels()
5645 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_plane_wm()  local
5655 	for (level = 0; level <= max_level; level++) {  in skl_write_plane_wm()
5685 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_cursor_wm()  local
5693 	for (level = 0; level <= max_level; level++) {  in skl_write_cursor_wm()
5719 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_plane_wm_equals()  local
5721 	for (level = 0; level <= max_level; level++) {  in skl_plane_wm_equals()
6232 	int level, max_level;  in skl_pipe_wm_get_hw_state()  local
6236 	max_level = ilk_wm_max_level(dev_priv);  in skl_pipe_wm_get_hw_state()
6241 		for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
6316 		int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_pipe_wm_get_hw_state()  local
6323 		for (level = 0; level <= max_level; level++)  in ilk_pipe_wm_get_hw_state()
6453 		int level, max_level;  in g4x_wm_get_hw_state()  local
6468 			max_level = G4X_WM_LEVEL_HPLL;  in g4x_wm_get_hw_state()
6470 			max_level = G4X_WM_LEVEL_SR;  in g4x_wm_get_hw_state()
6472 			max_level = G4X_WM_LEVEL_NORMAL;  in g4x_wm_get_hw_state()
6479 		if (++level > max_level)  in g4x_wm_get_hw_state()
6488 		if (++level > max_level)  in g4x_wm_get_hw_state()
6616 			dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;  in vlv_wm_get_hw_state()