Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
4 * Permission is hereby granted, free of charge, to any person obtaining a
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
35 * macros. Do **not** mass change existing definitions just to update the style.
44 * registers that are defined solely for the use by function-like macros.
47 * exceptions, but keep them to a minimum.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
62 * significant to least significant bit. Indent the register content macros
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
123 * Local wrapper for BIT() to force u32, with compile time checks.
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
135 * @__low: 0-based low bit
137 * Local wrapper for GENMASK() to force u32, with compile time checks.
139 * @return: Continuous bitmask from @__high to @__low, inclusive.
150 #define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
153 * REG_FIELD_PREP() - Prepare a u32 bitfield value
155 * @__val: value to put in the field
157 * Local copy of FIELD_PREP() to generate an integer constant expression, force
170 * REG_FIELD_GET() - Extract a u32 bitfield value
172 * @__val: value to extract the bitfield value from
174 * Local wrapper for FIELD_GET() to force u32 and for consistency with
208 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
212 * numbers, pick the 0-based __index'th value.
216 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
251 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
254 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
258 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
403 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
405 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
409 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
411 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
413 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
596 /* There are the 4 64-bit counter registers, one for each stream output */
614 /* There are the 16 64-bit CS General Purpose Registers */
1013 /* 11-bit array 0: pass-through, 1: negated */
1057 /* Same layout as CECX_Y + negate 11-bit array */
1394 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1413 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1414 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1740 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1743 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1744 (reg_ch1) - _BXT_PHY0_BASE))
1868 * CNL/ICL Port/COMBO-PHY Registers
2044 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
2092 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
2441 * [0-7] @ 0x2000 gen2,gen3
2442 * [8-15] @ 0x3000 945,g33,pnv
2444 * [0-15] @ 0x3000 gen4,gen5
2446 * [0-15] @ 0x100000 gen6,vlv,chv
2447 * [0-31] @ 0x100000 gen7+
2452 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2460 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2489 #define PRB0_BASE (0x2030 - 0x30)
2490 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
2491 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
2492 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
2493 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
2494 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
2495 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
2512 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2559 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
2607 /* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */
2761 /* GM45+ chicken bits -- debug workaround bits that may be required
2763 * the enables for writing to the corresponding low bit.
2772 /* Disables pipelining of read flushes past the SF-WIZ interface.
2773 * Required on all Ironlake steppings according to the B-Spec, but the
2860 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
2943 * set to a finite value.
2951 /* Enable render writes to complete in C2/C3/C4 power states.
2953 * power states. That seems bad to me.
2962 /* Enables non-sequential data reads through arbiter
2971 /* Arbiter time slice for non-isoch streams */
3116 * of registers. The first set pertains to the ring generating the
3121 * GT interrupt bits, so we don't need to duplicate the defines.
3123 * These defines should cover us well from SNB->HSW with minor exceptions
3162 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
3197 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
3297 /* The bit 28-8 is reserved */
3342 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3360 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3369 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3384 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3392 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3393 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3399 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3463 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
3464 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
3473 /* i830, required in DVO non-gang */
3485 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
3490 * Parallel to Serial Load Pulse phase selection.
3492 * digital display port. The range is 4 to 13; 10 or more
3512 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3528 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3529 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3530 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3540 * This best be set to the default value (3) or the CRT won't work. No,
3587 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3588 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3589 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3590 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3591 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3592 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3593 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3594 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3595 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3596 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3597 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3598 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3604 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3605 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3609 * This bit must be set on the 830 to prevent hangs when turning off the
3706 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3751 /* 915-945 and GM965 MCH register controlling DRAM channel access */
3827 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3831 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3847 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3867 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3913 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3923 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3925 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3927 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3938 #define SWFREQ_MASK 0x0380 /* P0-7 */
3953 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */
3954 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */
3966 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */
3980 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */
3981 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */
4006 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */
4025 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
4063 * - Power context is saved elsewhere (LLC or stolen)
4064 * - Ring/execlist context is saved on SNB, not on IVB
4065 * - Extended context size already includes render context size
4066 * - We always need to follow the extended context size.
4070 * - Pipelined/VF state is saved on SNB/IVB respectively
4071 * - GT1 size just indicates how much of render context
4431 * HSW+ eDP PSR registers
4433 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4439 #define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4468 * to transcoder and bits defined for each one as if using no shift (i.e. as if
4478 0 : ((trans) - TRANSCODER_A + 1) * 8)
4552 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
4555 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << …
4558 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
4561 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
4636 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4689 /* must use period 64 on GM45 according to docs */
4707 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4744 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4746 * bits here (and the comment!) to help any other lost wanderers back onto the
4801 * Programmed value is multiplier - 1, up to 5x.
4813 /* Bits to be preserved when writing */
4827 /* VSYNC/HSYNC bits new with 965, default is to be set */
4889 * the DPLL semantics change when the LVDS is assigned to that pipe.
4892 /* Selects pipe B for LVDS data. Must be set on pre-965. */
4901 /* LVDS sync polarity flags. Set to invert (i.e. negative) */
4905 /* Enable border for unscaled (or aspect-scaled) display */
4908 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4930 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4931 * setting for whether we are in dual-channel mode. The B3 pair will
4941 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4942 * of the infoframe structure specified by CEA-861. */
4988 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4998 * - PLL enabled
4999 * - pipe enabled
5000 * - LVDS/DVOB/DVOC on
5071 /* Pre-965 */
5148 /* New registers for PCH-split platforms. Safe where new bits show up, the
5229 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
5231 /* Field for setting delay of Y compared to C */
5244 /* Read-only state that reports all features enabled */
5246 /* Read-only state that reports that Macrovision is disabled in hardware*/
5248 /* Read-only state that reports that TV-out is disabled in hardware. */
5252 /* Encoder test pattern 1 - combo pattern */
5254 /* Encoder test pattern 2 - full screen vertical 75% color bars */
5256 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
5258 /* Encoder test pattern 4 - random noise */
5260 /* Encoder test pattern 5 - linear color ramps */
5263 * This test mode forces the DACs to 50% of full output.
5286 * Enables DAC state detection logic, for load-based TV detection.
5289 * to off, for load detection to work.
5292 /* Sets the DAC A sense value to high */
5294 /* Sets the DAC B sense value to high */
5296 /* Sets the DAC C sense value to high */
5317 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
5318 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
5319 * -1 (0x3) being the only legal negative value.
5373 /* 2s-complement brightness adjustment */
5403 /* Enables the colorburst (needed for non-component color) */
5467 * Offset to start of vertical colorburst, measured in one less than the
5473 * Offset to the end of vertical colorburst, measured in one less than the
5481 * Offset to start of vertical colorburst, measured in one less than the
5487 * Offset to the end of vertical colorburst, measured in one less than the
5495 * Offset to start of vertical colorburst, measured in one less than the
5501 * Offset to the end of vertical colorburst, measured in one less than the
5509 * Offset to start of vertical colorburst, measured in one less than the
5515 * Offset to the end of vertical colorburst, measured in one less than the
5528 /* Sets the subcarrier DDA to reset frequency every other field */
5530 /* Sets the subcarrier DDA to reset frequency every fourth field */
5532 /* Sets the subcarrier DDA to reset frequency every eighth field */
5534 /* Sets the subcarrier DDA to never reset the frequency */
5605 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5607 * (src width - 1) / ((oversample * dest width) - 1)
5614 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5616 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5621 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5630 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5632 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5634 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5639 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5641 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5651 * Specifies which field to send the CC data in.
5666 /* Second word of CC data to be transmitted. */
5669 /* First word of CC data to be transmitted. */
5679 #define DP_A _MMIO(0x64000) /* eDP */
5699 /* Link training mode - select a suitable mode for each stage */
5723 /* Signal pre-emphasis levels, like voltages, the other end tells us what
5733 /* How many wires to use. I guess 3 was too hard */
5734 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5741 /* eDP */
5749 /* eDP */
5758 /* limit RGB values to avoid confusing TVs */
5771 /* The aux channel provides a way to talk to the
5811 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5812 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5830 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5831 #define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */
5850 * Attributes and VB-ID.
5878 #define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
5879 #define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
5885 #define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
5886 #define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
5887 #define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
5888 #define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
5894 /* Note that pre-gen3 does not support interlaced display directly. Panel
5895 * fitting must be disabled on pre-ilk for interlaced. */
5913 #define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
5914 #define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
5915 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
5916 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
5947 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
5970 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
5986 * There's actually no pipe EDP. Some pipe registers have
5987 * simply shifted from the pipe to the transcoder, while
5989 * to access such registers in transcoder EDP.
6139 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
6368 /* the unit of memory self-refresh latency time is 0.5us */
6403 /* GM45+ just has to be different */
6415 #define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
6528 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8…
6671 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 …
6819 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6836 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)…
6846 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6880 #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6884 * expanded to include bit 23 as well. However, the shift-24 based values
6885 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6900 #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6922 #define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6930 #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6984 #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
6987 #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
7206 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
7212 _SEL_FETCH_PLANE_CTL_1_A - \
7218 _SEL_FETCH_PLANE_POS_1_A - \
7223 _SEL_FETCH_PLANE_SIZE_1_A - \
7228 _SEL_FETCH_PLANE_OFFSET_1_A - \
7250 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
7251 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
7252 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
7253 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
7254 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
7518 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
7529 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7797 #define GEN11_VECS(x) (31 - (x))
7840 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
7908 #define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8042 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
8043 * Using the formula in BSpec leads to a hang, while the formula here works
8045 * request has been filed to clarify this.
8163 /* south display engine interrupt: CPT - CNP */
8249 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
8250 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
8251 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
8252 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
8253 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
8260 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
8261 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
8262 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
8263 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
8264 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
8271 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
8272 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
8273 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
8274 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
8275 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
8323 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8326 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8329 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8332 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8351 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8354 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8357 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8360 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8376 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8379 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8382 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8385 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8401 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8404 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8407 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8410 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8520 /* Per-transcoder DIP controls (PCH) */
8536 /* Per-transcoder DIP controls (VLV) */
8590 * These are available for transcoders B,C and eDP.
8591 * Adding the _A so as to reuse the _MMIO_TRANS2
8592 * definition, with which it offsets to the right location.
8661 #define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
8682 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
8689 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
8690 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
8735 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8737 /* SNB A-stepping */
8742 /* SNB B-stepping */
8750 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
8752 /* Ironlake: hardwired to 1 */
8767 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
8868 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AU…
8869 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
8879 #define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29)
8893 /* SNB eDP training params */
8894 /* SNB A-stepping */
8899 /* SNB B-stepping */
8954 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
9189 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
9399 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
9400 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
9418 /* These are the 4 32-bit write offset registers for each stream
9420 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
9508 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
9523 * HSW - ICL power wells
9525 * Platforms have up to 3 power well control register sets, each set
9526 * controlling up to 16 power wells via a request/status HW flag tuple:
9527 * - main (HSW_PWR_WELL_CTL[1-4])
9528 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
9529 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
9530 * Each control register set consists of up to 4 registers used by different
9531 * sources that can request a power well to be enabled:
9532 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
9533 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
9534 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
9535 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
9563 /* ICL/TGL - power wells */
9612 /* HSW - power well misc debug registers */
9632 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
9635 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
9638 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
9641 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
9642 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
9644 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B)
9657 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
9886 /* Per-pipe DDI Function Control */
9897 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
9905 …DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1)
9917 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */
9921 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */
10000 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
10098 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
10139 /* For each transcoder, we need to select the corresponding port clock */
10262 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
10263 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
10281 (tc_port) - PORT_TC4 + 21))
10676 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address
10722 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
10786 * since on HSW we can't write to it using I915_WRITE. */
10793 /* Pipe WM_LINETIME - watermark line time */
10833 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
11033 /* MIPI DSI registers */
11039 #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \
11129 /* BXT MIPI clock controls */
11139 /* TX control divider to select actual TX clock output from (8x/var) */
11152 /* RX upper control divider to select actual RX clock output from 8x */
11165 /* 8/3X divider to select the actual 8/3X clock output from 8x */
11178 /* RX lower control divider to select actual RX clock output from 8x */
11195 /* BXT MIPI mode configure */
11276 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11285 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
11344 /* MIPI DSI Controller and D-PHY registers */
11346 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
11347 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
11349 #define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
11356 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
11357 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
11359 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
11360 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
11395 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
11396 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
11418 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
11419 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
11423 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
11424 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
11428 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
11429 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
11433 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
11434 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
11438 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
11439 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
11446 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
11447 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
11454 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
11455 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
11458 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
11459 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
11462 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
11463 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
11466 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
11467 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
11470 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
11471 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
11474 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
11475 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
11478 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
11479 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
11482 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
11483 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
11488 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
11489 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
11499 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
11500 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
11505 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
11506 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
11511 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
11512 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
11518 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
11519 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
11528 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
11529 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
11542 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
11543 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
11548 #define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
11549 #define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
11552 #define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
11553 #define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
11557 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
11558 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
11562 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
11563 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
11566 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
11567 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
11569 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
11570 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
11582 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
11583 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
11600 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
11601 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
11607 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
11608 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
11857 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
11858 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
11861 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
11862 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
11869 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
11870 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
11875 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
11876 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
11878 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
11879 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
11884 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
11896 /* MIPI adapter registers */
11898 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
11899 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
11931 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
11932 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
11938 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
11939 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
11944 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
11945 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
11953 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
11954 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
11959 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
11960 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
11963 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
11964 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
12016 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12019 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12037 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12040 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12051 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12054 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12066 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12069 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12081 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12084 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12096 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12099 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12111 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12114 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12128 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12131 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12143 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12146 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12158 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12161 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12173 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12176 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12190 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12193 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12203 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12206 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12216 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12219 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12229 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12232 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12242 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12245 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12255 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12258 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12278 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12281 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12284 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12287 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12303 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12306 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12309 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
12312 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \