Lines Matching +full:0 +full:x209c

106  *  #define _FOO_A                      0xf000
107  *  #define _FOO_B                      0xf001
111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
121  * @__n: 0-based bit number
130 				 ((__n) < 0 || (__n) > 31))))
134  * @__high: 0-based high bit
135  * @__low: 0-based low bit
145 				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
150 #define IS_POWER_OF_2(__x)		((__x) && (((__x) & ((__x) - 1)) == 0))
165 	       BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) +		\
167 …ERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
187 #define INVALID_MMIO_REG _MMIO(0)
204 #define VLV_DISPLAY_BASE		0x180000
206 #define BXT_MIPI_BASE			0x60000
212  * numbers, pick the 0-based __index'th value.
219  * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
265 		BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
267 		BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
273 #define _MASKED_BIT_DISABLE(a)	(_MASKED_FIELD((a), 0))
277 #define MCHBAR_I915 0x44
278 #define MCHBAR_I965 0x48
281 #define DEVEN 0x54
286 #define HPLLCC	0xc0 /* 85x only */
287 #define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)
288 #define   GC_CLOCK_133_200		(0 << 0)
289 #define   GC_CLOCK_100_200		(1 << 0)
290 #define   GC_CLOCK_100_133		(2 << 0)
291 #define   GC_CLOCK_133_266		(3 << 0)
292 #define   GC_CLOCK_133_200_2		(4 << 0)
293 #define   GC_CLOCK_133_266_2		(5 << 0)
294 #define   GC_CLOCK_166_266		(6 << 0)
295 #define   GC_CLOCK_166_250		(7 << 0)
297 #define I915_GDRST 0xc0 /* PCI config register */
298 #define   GRDOM_FULL		(0 << 2)
303 #define   GRDOM_RESET_ENABLE	(1 << 0)
306 #define I830_CLOCK_GATE	0xc8 /* device 0 */
309 #define GCDGMBUS 0xcc
311 #define GCFGC2	0xda
312 #define GCFGC	0xf0 /* 915+ only */
314 #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
316 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
323 #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
324 #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
325 #define   GM45_GC_RENDER_CLOCK_320_MHZ	(9 << 0)
326 #define   GM45_GC_RENDER_CLOCK_400_MHZ	(0xb << 0)
327 #define   GM45_GC_RENDER_CLOCK_533_MHZ	(0xc << 0)
328 #define   I965_GC_RENDER_CLOCK_MASK	(0xf << 0)
329 #define   I965_GC_RENDER_CLOCK_267_MHZ	(2 << 0)
330 #define   I965_GC_RENDER_CLOCK_333_MHZ	(3 << 0)
331 #define   I965_GC_RENDER_CLOCK_444_MHZ	(4 << 0)
332 #define   I965_GC_RENDER_CLOCK_533_MHZ	(5 << 0)
333 #define   I945_GC_RENDER_CLOCK_MASK	(7 << 0)
334 #define   I945_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
335 #define   I945_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
336 #define   I945_GC_RENDER_CLOCK_250_MHZ	(3 << 0)
337 #define   I945_GC_RENDER_CLOCK_400_MHZ	(5 << 0)
338 #define   I915_GC_RENDER_CLOCK_MASK	(7 << 0)
339 #define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)
340 #define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)
341 #define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)
343 #define ASLE	0xe4
344 #define ASLS	0xfc
346 #define SWSCI	0xe8
348 #define   SWSCI_GSSCIE	(1 << 0)
350 #define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
353 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
354 #define  ILK_GRDOM_FULL		(0 << 1)
358 #define  ILK_GRDOM_RESET_ENABLE (1 << 0)
360 #define GEN6_MBCUNIT_SNPCR	_MMIO(0x900c) /* for LLC config */
363 #define   GEN6_MBC_SNPCR_MAX	(0 << 21)
368 #define VLV_G3DCTL		_MMIO(0x9024)
369 #define VLV_GSCKGCTL		_MMIO(0x9028)
371 #define GEN6_MBCTL		_MMIO(0x0907c)
376 #define   GEN6_MBCTL_BOOT_FETCH_MECH	(1 << 0)
378 #define GEN6_GDRST	_MMIO(0x941c)
379 #define  GEN6_GRDOM_FULL		(1 << 0)
403 #define GEN11_VCS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x88C)
404 #define   GEN11_VCS_SFC_FORCED_LOCK_BIT		(1 << 0)
405 #define GEN11_VCS_SFC_LOCK_STATUS(engine)	_MMIO((engine)->mmio_base + 0x890)
406 #define   GEN11_VCS_SFC_USAGE_BIT		(1 << 0)
409 #define GEN11_VECS_SFC_FORCED_LOCK(engine)	_MMIO((engine)->mmio_base + 0x201C)
410 #define   GEN11_VECS_SFC_FORCED_LOCK_BIT	(1 << 0)
411 #define GEN11_VECS_SFC_LOCK_ACK(engine)		_MMIO((engine)->mmio_base + 0x2018)
412 #define   GEN11_VECS_SFC_LOCK_ACK_BIT		(1 << 0)
413 #define GEN11_VECS_SFC_USAGE(engine)		_MMIO((engine)->mmio_base + 0x2014)
414 #define   GEN11_VECS_SFC_USAGE_BIT		(1 << 0)
416 #define GEN12_SFC_DONE(n)		_MMIO(0x1cc00 + (n) * 0x100)
419 #define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)
420 #define RING_PP_DIR_BASE_READ(base)	_MMIO((base) + 0x518)
421 #define RING_PP_DIR_DCLV(base)		_MMIO((base) + 0x220)
422 #define   PP_DIR_DCLV_2G		0xffffffff
424 #define GEN8_RING_PDP_UDW(base, n)	_MMIO((base) + 0x270 + (n) * 8 + 4)
425 #define GEN8_RING_PDP_LDW(base, n)	_MMIO((base) + 0x270 + (n) * 8)
427 #define GEN8_R_PWR_CLK_STATE		_MMIO(0x20C8)
431 #define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
433 #define   GEN11_RPCS_S_CNT_MASK		(0x3f << GEN11_RPCS_S_CNT_SHIFT)
436 #define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
438 #define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
439 #define   GEN8_RPCS_EU_MIN_SHIFT	0
440 #define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
442 #define WAIT_FOR_RC6_EXIT		_MMIO(0x20CC)
445 #define   HSW_SELECTIVE_READ_ADDRESSING_MASK		(0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
447 #define   HSW_SELECTIVE_WRITE_ADDRESS_MASK		(0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
449 #define   HSW_WAIT_FOR_RC6_EXIT_ENABLE			(1 << 0)
454 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
456 #define   GEN8_SELECTIVE_WRITE_ADDRESS_MASK		(0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
459 #define   GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK	(0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIF…
461 #define   GEN8_SELECTIVE_READ_SLICE_SELECT_MASK		(0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
464 #define GAM_ECOCHK			_MMIO(0x4090)
469 #define   ECOCHK_PPGTT_CACHE64B		(0x3 << 3)
470 #define   ECOCHK_PPGTT_CACHE4B		(0x0 << 3)
471 #define   ECOCHK_PPGTT_GFDT_IVB		(0x1 << 4)
472 #define   ECOCHK_PPGTT_LLC_IVB		(0x1 << 3)
473 #define   ECOCHK_PPGTT_UC_HSW		(0x1 << 3)
474 #define   ECOCHK_PPGTT_WT_HSW		(0x2 << 3)
475 #define   ECOCHK_PPGTT_WB_HSW		(0x3 << 3)
477 #define GEN8_RC6_CTX_INFO		_MMIO(0x8504)
479 #define GAC_ECO_BITS			_MMIO(0x14090)
482 #define   ECOBITS_PPGTT_CACHE4B		(0 << 8)
484 #define GAB_CTL				_MMIO(0x24000)
487 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
488 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
489 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
491 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
496 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
499 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
503 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
504 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
508 #define VGA_ST01_MDA 0x3ba
509 #define VGA_ST01_CGA 0x3da
511 #define _VGA_MSR_WRITE _MMIO(0x3c2)
512 #define VGA_MSR_WRITE 0x3c2
513 #define VGA_MSR_READ 0x3cc
515 #define   VGA_MSR_CGA_MODE (1 << 0)
517 #define VGA_SR_INDEX 0x3c4
519 #define VGA_SR_DATA 0x3c5
521 #define VGA_AR_INDEX 0x3c0
523 #define VGA_AR_DATA_WRITE 0x3c0
524 #define VGA_AR_DATA_READ 0x3c1
526 #define VGA_GR_INDEX 0x3ce
527 #define VGA_GR_DATA 0x3cf
532 #define   VGA_GR_MEM_MODE_MASK 0xc
534 #define   VGA_GR_MEM_A0000_AFFFF 0
539 #define VGA_DACMASK 0x3c6
540 #define VGA_DACRX 0x3c7
541 #define VGA_DACWX 0x3c8
542 #define VGA_DACDATA 0x3c9
544 #define VGA_CR_INDEX_MDA 0x3b4
545 #define VGA_CR_DATA_MDA 0x3b5
546 #define VGA_CR_INDEX_CGA 0x3d4
547 #define VGA_CR_DATA_CGA 0x3d5
549 #define MI_PREDICATE_SRC0	_MMIO(0x2400)
550 #define MI_PREDICATE_SRC0_UDW	_MMIO(0x2400 + 4)
551 #define MI_PREDICATE_SRC1	_MMIO(0x2408)
552 #define MI_PREDICATE_SRC1_UDW	_MMIO(0x2408 + 4)
553 #define MI_PREDICATE_DATA       _MMIO(0x2410)
554 #define MI_PREDICATE_RESULT     _MMIO(0x2418)
555 #define MI_PREDICATE_RESULT_1   _MMIO(0x241c)
556 #define MI_PREDICATE_RESULT_2	_MMIO(0x2214)
557 #define  LOWER_SLICE_ENABLED	(1 << 0)
558 #define  LOWER_SLICE_DISABLED	(0 << 0)
563 #define BCS_SWCTRL _MMIO(0x22200)
564 #define   BCS_SRC_Y REG_BIT(0)
568 #define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)
569 #define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)
571 #define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)
572 #define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)
573 #define HS_INVOCATION_COUNT             _MMIO(0x2300)
574 #define HS_INVOCATION_COUNT_UDW		_MMIO(0x2300 + 4)
575 #define DS_INVOCATION_COUNT             _MMIO(0x2308)
576 #define DS_INVOCATION_COUNT_UDW		_MMIO(0x2308 + 4)
577 #define IA_VERTICES_COUNT               _MMIO(0x2310)
578 #define IA_VERTICES_COUNT_UDW		_MMIO(0x2310 + 4)
579 #define IA_PRIMITIVES_COUNT             _MMIO(0x2318)
580 #define IA_PRIMITIVES_COUNT_UDW		_MMIO(0x2318 + 4)
581 #define VS_INVOCATION_COUNT             _MMIO(0x2320)
582 #define VS_INVOCATION_COUNT_UDW		_MMIO(0x2320 + 4)
583 #define GS_INVOCATION_COUNT             _MMIO(0x2328)
584 #define GS_INVOCATION_COUNT_UDW		_MMIO(0x2328 + 4)
585 #define GS_PRIMITIVES_COUNT             _MMIO(0x2330)
586 #define GS_PRIMITIVES_COUNT_UDW		_MMIO(0x2330 + 4)
587 #define CL_INVOCATION_COUNT             _MMIO(0x2338)
588 #define CL_INVOCATION_COUNT_UDW		_MMIO(0x2338 + 4)
589 #define CL_PRIMITIVES_COUNT             _MMIO(0x2340)
590 #define CL_PRIMITIVES_COUNT_UDW		_MMIO(0x2340 + 4)
591 #define PS_INVOCATION_COUNT             _MMIO(0x2348)
592 #define PS_INVOCATION_COUNT_UDW		_MMIO(0x2348 + 4)
593 #define PS_DEPTH_COUNT                  _MMIO(0x2350)
594 #define PS_DEPTH_COUNT_UDW		_MMIO(0x2350 + 4)
597 #define GEN7_SO_NUM_PRIMS_WRITTEN(n)		_MMIO(0x5200 + (n) * 8)
598 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n)	_MMIO(0x5200 + (n) * 8 + 4)
600 #define GEN7_SO_PRIM_STORAGE_NEEDED(n)		_MMIO(0x5240 + (n) * 8)
601 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n)	_MMIO(0x5240 + (n) * 8 + 4)
603 #define GEN7_3DPRIM_END_OFFSET          _MMIO(0x2420)
604 #define GEN7_3DPRIM_START_VERTEX        _MMIO(0x2430)
605 #define GEN7_3DPRIM_VERTEX_COUNT        _MMIO(0x2434)
606 #define GEN7_3DPRIM_INSTANCE_COUNT      _MMIO(0x2438)
607 #define GEN7_3DPRIM_START_INSTANCE      _MMIO(0x243C)
608 #define GEN7_3DPRIM_BASE_VERTEX         _MMIO(0x2440)
610 #define GEN7_GPGPU_DISPATCHDIMX         _MMIO(0x2500)
611 #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
612 #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
615 #define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
616 #define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
618 #define GEN7_OACONTROL _MMIO(0x2360)
619 #define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000
620 #define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
623 #define  GEN7_OACONTROL_FORMAT_A13	    (0 << 2)
633 #define  GEN7_OACONTROL_ENABLE		    (1 << 0)
635 #define GEN8_OACTXID _MMIO(0x2364)
637 #define GEN8_OA_DEBUG _MMIO(0x2B04)
643 #define GEN8_OACONTROL _MMIO(0x2B00)
644 #define  GEN8_OA_REPORT_FORMAT_A12	    (0 << 2)
650 #define  GEN8_OA_COUNTER_ENABLE             (1 << 0)
652 #define GEN8_OACTXCONTROL _MMIO(0x2360)
653 #define  GEN8_OA_TIMER_PERIOD_MASK	    0x3F
656 #define  GEN8_OA_COUNTER_RESUME		    (1 << 0)
658 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
662 #define  GEN7_OABUFFER_RESUME		    (1 << 0)
664 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
665 #define GEN8_OABUFFER _MMIO(0x2b14)
666 #define  GEN8_OABUFFER_MEM_SELECT_GGTT      (1 << 0)  /* 0: PPGTT, 1: GGTT */
668 #define GEN7_OASTATUS1 _MMIO(0x2364)
669 #define  GEN7_OASTATUS1_TAIL_MASK	    0xffffffc0
672 #define  GEN7_OASTATUS1_REPORT_LOST	    (1 << 0)
674 #define GEN7_OASTATUS2 _MMIO(0x2368)
675 #define  GEN7_OASTATUS2_HEAD_MASK           0xffffffc0
676 #define  GEN7_OASTATUS2_MEM_SELECT_GGTT     (1 << 0) /* 0: PPGTT, 1: GGTT */
678 #define GEN8_OASTATUS _MMIO(0x2b08)
684 #define  GEN8_OASTATUS_REPORT_LOST	    (1 << 0)
686 #define GEN8_OAHEADPTR _MMIO(0x2B0C)
687 #define GEN8_OAHEADPTR_MASK    0xffffffc0
688 #define GEN8_OATAILPTR _MMIO(0x2B10)
689 #define GEN8_OATAILPTR_MASK    0xffffffc0
691 #define OABUFFER_SIZE_128K  (0 << 3)
700 #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
703 #define GEN12_OAR_OACONTROL _MMIO(0x2960)
705 #define  GEN12_OAR_OACONTROL_COUNTER_ENABLE       (1 << 0)
707 #define GEN12_OACTXCONTROL _MMIO(0x2360)
708 #define GEN12_OAR_OASTATUS _MMIO(0x2968)
711 #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00)
712 #define  GEN12_OAG_OAHEADPTR_MASK 0xffffffc0
713 #define GEN12_OAG_OATAILPTR _MMIO(0xdb04)
714 #define  GEN12_OAG_OATAILPTR_MASK 0xffffffc0
716 #define GEN12_OAG_OABUFFER  _MMIO(0xdb08)
717 #define  GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK  (0x7)
719 #define  GEN12_OAG_OABUFFER_MEMORY_SELECT     (1 << 0) /* 0: PPGTT, 1: GGTT */
721 #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28)
724 #define  GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME     (1 << 0)
726 #define GEN12_OAG_OACONTROL _MMIO(0xdaf4)
728 #define  GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE       (1 << 0)
730 #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8)
736 #define GEN12_OAG_OASTATUS _MMIO(0xdafc)
739 #define  GEN12_OAG_OASTATUS_REPORT_LOST      (1 << 0)
745 #define EU_PERF_CNTL0	    _MMIO(0xe458)
746 #define EU_PERF_CNTL1	    _MMIO(0xe558)
747 #define EU_PERF_CNTL2	    _MMIO(0xe658)
748 #define EU_PERF_CNTL3	    _MMIO(0xe758)
749 #define EU_PERF_CNTL4	    _MMIO(0xe45c)
750 #define EU_PERF_CNTL5	    _MMIO(0xe55c)
751 #define EU_PERF_CNTL6	    _MMIO(0xe65c)
757 #define OASTARTTRIG1 _MMIO(0x2710)
758 #define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
759 #define OASTARTTRIG1_THRESHOLD_MASK	      0xffff
761 #define OASTARTTRIG2 _MMIO(0x2714)
762 #define OASTARTTRIG2_INVERT_A_0 (1 << 0)
792 #define OASTARTTRIG3 _MMIO(0x2718)
793 #define OASTARTTRIG3_NOA_SELECT_MASK	   0xf
794 #define OASTARTTRIG3_NOA_SELECT_8_SHIFT    0
803 #define OASTARTTRIG4 _MMIO(0x271c)
804 #define OASTARTTRIG4_NOA_SELECT_MASK	    0xf
805 #define OASTARTTRIG4_NOA_SELECT_0_SHIFT    0
814 #define OASTARTTRIG5 _MMIO(0x2720)
815 #define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
816 #define OASTARTTRIG5_THRESHOLD_MASK	      0xffff
818 #define OASTARTTRIG6 _MMIO(0x2724)
819 #define OASTARTTRIG6_INVERT_A_0 (1 << 0)
849 #define OASTARTTRIG7 _MMIO(0x2728)
850 #define OASTARTTRIG7_NOA_SELECT_MASK	   0xf
851 #define OASTARTTRIG7_NOA_SELECT_8_SHIFT    0
860 #define OASTARTTRIG8 _MMIO(0x272c)
861 #define OASTARTTRIG8_NOA_SELECT_MASK	   0xf
862 #define OASTARTTRIG8_NOA_SELECT_0_SHIFT    0
871 #define OAREPORTTRIG1 _MMIO(0x2740)
872 #define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
873 #define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
875 #define OAREPORTTRIG2 _MMIO(0x2744)
876 #define OAREPORTTRIG2_INVERT_A_0  (1 << 0)
902 #define OAREPORTTRIG3 _MMIO(0x2748)
903 #define OAREPORTTRIG3_NOA_SELECT_MASK	    0xf
904 #define OAREPORTTRIG3_NOA_SELECT_8_SHIFT    0
913 #define OAREPORTTRIG4 _MMIO(0x274c)
914 #define OAREPORTTRIG4_NOA_SELECT_MASK	    0xf
915 #define OAREPORTTRIG4_NOA_SELECT_0_SHIFT    0
924 #define OAREPORTTRIG5 _MMIO(0x2750)
925 #define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
926 #define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */
928 #define OAREPORTTRIG6 _MMIO(0x2754)
929 #define OAREPORTTRIG6_INVERT_A_0  (1 << 0)
955 #define OAREPORTTRIG7 _MMIO(0x2758)
956 #define OAREPORTTRIG7_NOA_SELECT_MASK	    0xf
957 #define OAREPORTTRIG7_NOA_SELECT_8_SHIFT    0
966 #define OAREPORTTRIG8 _MMIO(0x275c)
967 #define OAREPORTTRIG8_NOA_SELECT_MASK	    0xf
968 #define OAREPORTTRIG8_NOA_SELECT_0_SHIFT    0
978 #define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
979 #define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
980 #define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908)
981 #define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c)
982 #define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910)
983 #define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914)
984 #define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918)
985 #define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c)
988 #define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920)
989 #define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924)
990 #define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928)
991 #define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c)
992 #define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930)
993 #define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934)
994 #define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938)
995 #define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c)
1004 #define OACEC_COMPARE_ANY_EQUAL		0
1006 #define OACEC_COMPARE_VALUE_MASK    0xffff
1009 #define OACEC_SELECT_NOA	(0 << 19)
1013 /* 11-bit array 0: pass-through, 1: negated */
1014 #define GEN12_OASCEC_NEGATE_MASK  0x7ff
1018 #define OACEC_MASK_MASK		    0xffff
1019 #define OACEC_CONSIDERATIONS_MASK   0xffff
1022 #define OACEC0_0 _MMIO(0x2770)
1023 #define OACEC0_1 _MMIO(0x2774)
1024 #define OACEC1_0 _MMIO(0x2778)
1025 #define OACEC1_1 _MMIO(0x277c)
1026 #define OACEC2_0 _MMIO(0x2780)
1027 #define OACEC2_1 _MMIO(0x2784)
1028 #define OACEC3_0 _MMIO(0x2788)
1029 #define OACEC3_1 _MMIO(0x278c)
1030 #define OACEC4_0 _MMIO(0x2790)
1031 #define OACEC4_1 _MMIO(0x2794)
1032 #define OACEC5_0 _MMIO(0x2798)
1033 #define OACEC5_1 _MMIO(0x279c)
1034 #define OACEC6_0 _MMIO(0x27a0)
1035 #define OACEC6_1 _MMIO(0x27a4)
1036 #define OACEC7_0 _MMIO(0x27a8)
1037 #define OACEC7_1 _MMIO(0x27ac)
1040 #define GEN12_OAG_CEC0_0 _MMIO(0xd940)
1041 #define GEN12_OAG_CEC0_1 _MMIO(0xd944)
1042 #define GEN12_OAG_CEC1_0 _MMIO(0xd948)
1043 #define GEN12_OAG_CEC1_1 _MMIO(0xd94c)
1044 #define GEN12_OAG_CEC2_0 _MMIO(0xd950)
1045 #define GEN12_OAG_CEC2_1 _MMIO(0xd954)
1046 #define GEN12_OAG_CEC3_0 _MMIO(0xd958)
1047 #define GEN12_OAG_CEC3_1 _MMIO(0xd95c)
1048 #define GEN12_OAG_CEC4_0 _MMIO(0xd960)
1049 #define GEN12_OAG_CEC4_1 _MMIO(0xd964)
1050 #define GEN12_OAG_CEC5_0 _MMIO(0xd968)
1051 #define GEN12_OAG_CEC5_1 _MMIO(0xd96c)
1052 #define GEN12_OAG_CEC6_0 _MMIO(0xd970)
1053 #define GEN12_OAG_CEC6_1 _MMIO(0xd974)
1054 #define GEN12_OAG_CEC7_0 _MMIO(0xd978)
1055 #define GEN12_OAG_CEC7_1 _MMIO(0xd97c)
1058 #define GEN12_OAG_SCEC0_0 _MMIO(0xdc00)
1059 #define GEN12_OAG_SCEC0_1 _MMIO(0xdc04)
1060 #define GEN12_OAG_SCEC1_0 _MMIO(0xdc08)
1061 #define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c)
1062 #define GEN12_OAG_SCEC2_0 _MMIO(0xdc10)
1063 #define GEN12_OAG_SCEC2_1 _MMIO(0xdc14)
1064 #define GEN12_OAG_SCEC3_0 _MMIO(0xdc18)
1065 #define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c)
1066 #define GEN12_OAG_SCEC4_0 _MMIO(0xdc20)
1067 #define GEN12_OAG_SCEC4_1 _MMIO(0xdc24)
1068 #define GEN12_OAG_SCEC5_0 _MMIO(0xdc28)
1069 #define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c)
1070 #define GEN12_OAG_SCEC6_0 _MMIO(0xdc30)
1071 #define GEN12_OAG_SCEC6_1 _MMIO(0xdc34)
1072 #define GEN12_OAG_SCEC7_0 _MMIO(0xdc38)
1073 #define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c)
1076 #define OA_PERFCNT1_LO      _MMIO(0x91B8)
1077 #define OA_PERFCNT1_HI      _MMIO(0x91BC)
1078 #define OA_PERFCNT2_LO      _MMIO(0x91C0)
1079 #define OA_PERFCNT2_HI      _MMIO(0x91C4)
1080 #define OA_PERFCNT3_LO      _MMIO(0x91C8)
1081 #define OA_PERFCNT3_HI      _MMIO(0x91CC)
1082 #define OA_PERFCNT4_LO      _MMIO(0x91D8)
1083 #define OA_PERFCNT4_HI      _MMIO(0x91DC)
1085 #define OA_PERFMATRIX_LO    _MMIO(0x91C8)
1086 #define OA_PERFMATRIX_HI    _MMIO(0x91CC)
1089 #define RPM_CONFIG0	    _MMIO(0x0D00)
1092 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
1095 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHI…
1096 #define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
1101 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_S…
1103 #define RPM_CONFIG1	    _MMIO(0x0D04)
1107 #define CTC_MODE			_MMIO(0xA26C)
1109 #define  CTC_SOURCE_CRYSTAL_CLOCK	0
1112 #define  CTC_SHIFT_PARAMETER_MASK	(0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1115 #define RCP_CONFIG	    _MMIO(0x0D08)
1118 #define HSW_MBVID2_NOA0		_MMIO(0x9E80)
1119 #define HSW_MBVID2_NOA1		_MMIO(0x9E84)
1120 #define HSW_MBVID2_NOA2		_MMIO(0x9E88)
1121 #define HSW_MBVID2_NOA3		_MMIO(0x9E8C)
1122 #define HSW_MBVID2_NOA4		_MMIO(0x9E90)
1123 #define HSW_MBVID2_NOA5		_MMIO(0x9E94)
1124 #define HSW_MBVID2_NOA6		_MMIO(0x9E98)
1125 #define HSW_MBVID2_NOA7		_MMIO(0x9E9C)
1126 #define HSW_MBVID2_NOA8		_MMIO(0x9EA0)
1127 #define HSW_MBVID2_NOA9		_MMIO(0x9EA4)
1129 #define HSW_MBVID2_MISR0	_MMIO(0x9EC0)
1132 #define NOA_CONFIG(i)	    _MMIO(0x0D0C + (i) * 4)
1134 #define MICRO_BP0_0	    _MMIO(0x9800)
1135 #define MICRO_BP0_2	    _MMIO(0x9804)
1136 #define MICRO_BP0_1	    _MMIO(0x9808)
1138 #define MICRO_BP1_0	    _MMIO(0x980C)
1139 #define MICRO_BP1_2	    _MMIO(0x9810)
1140 #define MICRO_BP1_1	    _MMIO(0x9814)
1142 #define MICRO_BP2_0	    _MMIO(0x9818)
1143 #define MICRO_BP2_2	    _MMIO(0x981C)
1144 #define MICRO_BP2_1	    _MMIO(0x9820)
1146 #define MICRO_BP3_0	    _MMIO(0x9824)
1147 #define MICRO_BP3_2	    _MMIO(0x9828)
1148 #define MICRO_BP3_1	    _MMIO(0x982C)
1150 #define MICRO_BP_TRIGGER		_MMIO(0x9830)
1151 #define MICRO_BP3_COUNT_STATUS01	_MMIO(0x9834)
1152 #define MICRO_BP3_COUNT_STATUS23	_MMIO(0x9838)
1153 #define MICRO_BP_FIRED_ARMED		_MMIO(0x983C)
1155 #define GEN12_OAA_DBG_REG _MMIO(0xdc44)
1156 #define GEN12_OAG_OA_PESS _MMIO(0x2b2c)
1157 #define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40)
1159 #define GDT_CHICKEN_BITS    _MMIO(0x9840)
1160 #define   GT_NOA_ENABLE	    0x00000080
1162 #define NOA_DATA	    _MMIO(0x986C)
1163 #define NOA_WRITE	    _MMIO(0x9888)
1164 #define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
1166 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
1167 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
1173 #define DEBUG_RESET_I830		_MMIO(0x6070)
1181 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
1187 #define   IOSF_SB_BUSY				(1 << 0)
1188 #define   IOSF_PORT_BUNIT			0x03
1189 #define   IOSF_PORT_PUNIT			0x04
1190 #define   IOSF_PORT_NC				0x11
1191 #define   IOSF_PORT_DPIO			0x12
1192 #define   IOSF_PORT_GPIO_NC			0x13
1193 #define   IOSF_PORT_CCK				0x14
1194 #define   IOSF_PORT_DPIO_2			0x1a
1195 #define   IOSF_PORT_FLISDSI			0x1b
1196 #define   IOSF_PORT_GPIO_SC			0x48
1197 #define   IOSF_PORT_GPIO_SUS			0xa8
1198 #define   IOSF_PORT_CCU				0xa9
1199 #define   CHV_IOSF_PORT_GPIO_N			0x13
1200 #define   CHV_IOSF_PORT_GPIO_SE			0x48
1201 #define   CHV_IOSF_PORT_GPIO_E			0xa8
1202 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
1203 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
1204 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
1207 #define BUNIT_REG_BISOC				0x11
1210 #define   _SSPM0_SSC(val)			((val) << 0)
1211 #define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
1212 #define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
1213 #define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
1214 #define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
1215 #define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
1217 #define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
1218 #define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
1219 #define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
1220 #define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
1221 #define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)
1225 #define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
1227 #define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
1228 #define   SSPM1_FREQ_SHIFT			0
1229 #define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)
1231 #define PUNIT_REG_VEDSSPM0			0x32
1232 #define PUNIT_REG_VEDSSPM1			0x33
1234 #define PUNIT_REG_DSPSSPM			0x36
1236 #define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
1238 #define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
1240 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
1242 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
1247 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
1248 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
1249 #define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
1250 #define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
1251 #define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
1253 #define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
1254 #define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
1255 #define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
1256 #define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
1257 #define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))
1259 #define PUNIT_REG_ISPSSPM0			0x39
1260 #define PUNIT_REG_ISPSSPM1			0x3a
1262 #define PUNIT_REG_PWRGT_CTRL			0x60
1263 #define PUNIT_REG_PWRGT_STATUS			0x61
1265 #define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
1270 #define PUNIT_PWGT_IDX_RENDER			0
1282 #define PUNIT_REG_GPU_LFM			0xd3
1283 #define PUNIT_REG_GPU_FREQ_REQ			0xd4
1284 #define PUNIT_REG_GPU_FREQ_STS			0xd8
1286 #define   GENFREQSTATUS				(1 << 0)
1287 #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
1288 #define PUNIT_REG_CZ_TIMESTAMP			0xce
1290 #define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
1291 #define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
1293 #define FB_GFX_FMAX_AT_VMAX_FUSE		0x136
1294 #define FB_GFX_FREQ_FUSE_MASK			0xff
1299 #define FB_GFX_FMIN_AT_VMIN_FUSE		0x137
1302 #define PUNIT_REG_DDR_SETUP2			0x139
1305 #define   FORCE_DDR_HIGH_FREQ			(1 << 0)
1307 #define PUNIT_GPU_STATUS_REG			0xdb
1309 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK		0xff
1311 #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK	0xff
1313 #define PUNIT_GPU_DUTYCYCLE_REG		0xdf
1315 #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK	0xff
1317 #define IOSF_NC_FB_GFX_FREQ_FUSE		0x1c
1319 #define   FB_GFX_MAX_FREQ_FUSE_MASK		0x000007f8
1321 #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK	0x0007f800
1322 #define IOSF_NC_FB_GFX_FMAX_FUSE_HI		0x34
1323 #define   FB_FMAX_VMIN_FREQ_HI_MASK		0x00000007
1324 #define IOSF_NC_FB_GFX_FMAX_FUSE_LO		0x30
1326 #define   FB_FMAX_VMIN_FREQ_LO_MASK		0xf8000000
1328 #define VLV_TURBO_SOC_OVERRIDE		0x04
1335 #define CCK_FUSE_REG				0x8
1336 #define  CCK_FUSE_HPLL_FREQ_MASK		0x3
1337 #define CCK_REG_DSI_PLL_FUSE			0x44
1338 #define CCK_REG_DSI_PLL_CONTROL			0x48
1342 #define  DSI_PLL_P1_POST_DIV_MASK		(0x1ff << 17)
1346 #define  DSI_PLL_MUX_DSI0_DSIPLL		(0 << 10)
1348 #define  DSI_PLL_MUX_DSI1_DSIPLL		(0 << 9)
1350 #define  DSI_PLL_CLK_GATE_MASK			(0xf << 5)
1355 #define  DSI_PLL_LOCK				(1 << 0)
1356 #define CCK_REG_DSI_PLL_DIVIDER			0x4c
1362 #define  DSI_PLL_USYNC_CNT_MASK			(0x1ff << 18)
1365 #define  DSI_PLL_M1_DIV_SHIFT			0
1366 #define  DSI_PLL_M1_DIV_MASK			(0x1ff << 0)
1367 #define CCK_CZ_CLOCK_CONTROL			0x62
1368 #define CCK_GPLL_CLOCK_CONTROL			0x67
1369 #define CCK_DISPLAY_CLOCK_CONTROL		0x6b
1370 #define CCK_DISPLAY_REF_CLOCK_CONTROL		0x6c
1373 #define  CCK_FREQUENCY_STATUS			(0x1f << 8)
1375 #define  CCK_FREQUENCY_VALUES			(0x1f << 0)
1378 #define DPIO_DEVFN			0
1380 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
1384 #define  DPIO_CMNRST			(1 << 0)
1391 #define _VLV_PLL_DW3_CH0		0x800c
1393 #define   DPIO_POST_DIV_DAC		0
1403 #define   DPIO_M2DIV_MASK		0xff
1404 #define _VLV_PLL_DW3_CH1		0x802c
1407 #define _VLV_PLL_DW5_CH0		0x8014
1410 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
1413 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
1414 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
1415 #define _VLV_PLL_DW5_CH1		0x8034
1418 #define _VLV_PLL_DW7_CH0		0x801c
1419 #define _VLV_PLL_DW7_CH1		0x803c
1422 #define _VLV_PLL_DW8_CH0		0x8040
1423 #define _VLV_PLL_DW8_CH1		0x8060
1426 #define VLV_PLL_DW9_BCAST		0xc044
1427 #define _VLV_PLL_DW9_CH0		0x8044
1428 #define _VLV_PLL_DW9_CH1		0x8064
1431 #define _VLV_PLL_DW10_CH0		0x8048
1432 #define _VLV_PLL_DW10_CH1		0x8068
1435 #define _VLV_PLL_DW11_CH0		0x804c
1436 #define _VLV_PLL_DW11_CH1		0x806c
1440 #define VLV_REF_DW13			0x80ac
1442 #define VLV_CMN_DW0			0x8100
1448 #define _VLV_PCS_DW0_CH0		0x8200
1449 #define _VLV_PCS_DW0_CH1		0x8400
1456 #define _VLV_PCS01_DW0_CH0		0x200
1457 #define _VLV_PCS23_DW0_CH0		0x400
1458 #define _VLV_PCS01_DW0_CH1		0x2600
1459 #define _VLV_PCS23_DW0_CH1		0x2800
1463 #define _VLV_PCS_DW1_CH0		0x8204
1464 #define _VLV_PCS_DW1_CH1		0x8404
1472 #define _VLV_PCS01_DW1_CH0		0x204
1473 #define _VLV_PCS23_DW1_CH0		0x404
1474 #define _VLV_PCS01_DW1_CH1		0x2604
1475 #define _VLV_PCS23_DW1_CH1		0x2804
1479 #define _VLV_PCS_DW8_CH0		0x8220
1480 #define _VLV_PCS_DW8_CH1		0x8420
1485 #define _VLV_PCS01_DW8_CH0		0x0220
1486 #define _VLV_PCS23_DW8_CH0		0x0420
1487 #define _VLV_PCS01_DW8_CH1		0x2620
1488 #define _VLV_PCS23_DW8_CH1		0x2820
1492 #define _VLV_PCS_DW9_CH0		0x8224
1493 #define _VLV_PCS_DW9_CH1		0x8424
1494 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
1495 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
1497 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
1498 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
1502 #define _VLV_PCS01_DW9_CH0		0x224
1503 #define _VLV_PCS23_DW9_CH0		0x424
1504 #define _VLV_PCS01_DW9_CH1		0x2624
1505 #define _VLV_PCS23_DW9_CH1		0x2824
1509 #define _CHV_PCS_DW10_CH0		0x8228
1510 #define _CHV_PCS_DW10_CH1		0x8428
1513 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
1514 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
1516 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
1517 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
1521 #define _VLV_PCS01_DW10_CH0		0x0228
1522 #define _VLV_PCS23_DW10_CH0		0x0428
1523 #define _VLV_PCS01_DW10_CH1		0x2628
1524 #define _VLV_PCS23_DW10_CH1		0x2828
1528 #define _VLV_PCS_DW11_CH0		0x822c
1529 #define _VLV_PCS_DW11_CH1		0x842c
1533 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
1536 #define _VLV_PCS01_DW11_CH0		0x022c
1537 #define _VLV_PCS23_DW11_CH0		0x042c
1538 #define _VLV_PCS01_DW11_CH1		0x262c
1539 #define _VLV_PCS23_DW11_CH1		0x282c
1543 #define _VLV_PCS01_DW12_CH0		0x0230
1544 #define _VLV_PCS23_DW12_CH0		0x0430
1545 #define _VLV_PCS01_DW12_CH1		0x2630
1546 #define _VLV_PCS23_DW12_CH1		0x2830
1550 #define _VLV_PCS_DW12_CH0		0x8230
1551 #define _VLV_PCS_DW12_CH1		0x8430
1556 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
1559 #define _VLV_PCS_DW14_CH0		0x8238
1560 #define _VLV_PCS_DW14_CH1		0x8438
1563 #define _VLV_PCS_DW23_CH0		0x825c
1564 #define _VLV_PCS_DW23_CH1		0x845c
1567 #define _VLV_TX_DW2_CH0			0x8288
1568 #define _VLV_TX_DW2_CH1			0x8488
1570 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
1574 #define _VLV_TX_DW3_CH0			0x828c
1575 #define _VLV_TX_DW3_CH1			0x848c
1579 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
1582 #define _VLV_TX_DW4_CH0			0x8290
1583 #define _VLV_TX_DW4_CH1			0x8490
1585 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1587 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1590 #define _VLV_TX3_DW4_CH0		0x690
1591 #define _VLV_TX3_DW4_CH1		0x2a90
1594 #define _VLV_TX_DW5_CH0			0x8294
1595 #define _VLV_TX_DW5_CH1			0x8494
1599 #define _VLV_TX_DW11_CH0		0x82ac
1600 #define _VLV_TX_DW11_CH1		0x84ac
1603 #define _VLV_TX_DW14_CH0		0x82b8
1604 #define _VLV_TX_DW14_CH1		0x84b8
1608 #define _CHV_PLL_DW0_CH0		0x8000
1609 #define _CHV_PLL_DW0_CH1		0x8180
1612 #define _CHV_PLL_DW1_CH0		0x8004
1613 #define _CHV_PLL_DW1_CH1		0x8184
1615 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
1618 #define _CHV_PLL_DW2_CH0		0x8008
1619 #define _CHV_PLL_DW2_CH1		0x8188
1622 #define _CHV_PLL_DW3_CH0		0x800c
1623 #define _CHV_PLL_DW3_CH1		0x818c
1625 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
1627 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
1628 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
1631 #define _CHV_PLL_DW6_CH0		0x8018
1632 #define _CHV_PLL_DW6_CH1		0x8198
1635 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
1638 #define _CHV_PLL_DW8_CH0		0x8020
1639 #define _CHV_PLL_DW8_CH1		0x81A0
1640 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1641 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
1644 #define _CHV_PLL_DW9_CH0		0x8024
1645 #define _CHV_PLL_DW9_CH1		0x81A4
1648 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
1651 #define _CHV_CMN_DW0_CH0               0x8100
1655 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
1657 #define _CHV_CMN_DW5_CH0               0x8114
1658 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
1662 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
1667 #define _CHV_CMN_DW13_CH0		0x8134
1668 #define _CHV_CMN_DW0_CH1		0x8080
1674 #define   DPIO_PLL_LOCK			(1 << 0)
1677 #define _CHV_CMN_DW14_CH0		0x8138
1678 #define _CHV_CMN_DW1_CH1		0x8084
1681 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
1685 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
1691 #define _CHV_CMN_DW19_CH0		0x814c
1692 #define _CHV_CMN_DW6_CH1		0x8098
1700 #define CHV_CMN_DW28			0x8170
1703 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
1704 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
1705 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
1706 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
1708 #define CHV_CMN_DW30			0x8178
1712 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1713 					(lane) * 0x200 + (offset))
1715 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1716 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1717 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1718 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1719 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1720 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1721 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1722 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1723 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1724 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1725 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1726 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1728 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1732 #define _BXT_PHY0_BASE			0x6C000
1733 #define _BXT_PHY1_BASE			0x162000
1734 #define _BXT_PHY2_BASE			0x163000
1748 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
1751 #define _BXT_PHY_CTL_DDI_A		0x64C00
1752 #define _BXT_PHY_CTL_DDI_B		0x64C10
1753 #define _BXT_PHY_CTL_DDI_C		0x64C20
1760 #define _PHY_CTL_FAMILY_EDP		0x64C80
1761 #define _PHY_CTL_FAMILY_DDI		0x64C90
1762 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
1769 #define _PORT_PLL_A			0x46074
1770 #define _PORT_PLL_B			0x46078
1771 #define _PORT_PLL_C			0x4607c
1779 #define _PORT_PLL_EBB_0_A		0x162034
1780 #define _PORT_PLL_EBB_0_B		0x6C034
1781 #define _PORT_PLL_EBB_0_C		0x6C340
1783 #define   PORT_PLL_P1_MASK		(0x07 << PORT_PLL_P1_SHIFT)
1786 #define   PORT_PLL_P2_MASK		(0x1f << PORT_PLL_P2_SHIFT)
1792 #define _PORT_PLL_EBB_4_A		0x162038
1793 #define _PORT_PLL_EBB_4_B		0x6C038
1794 #define _PORT_PLL_EBB_4_C		0x6C344
1801 #define _PORT_PLL_0_A			0x162100
1802 #define _PORT_PLL_0_B			0x6C100
1803 #define _PORT_PLL_0_C			0x6C380
1805 #define   PORT_PLL_M2_MASK		0xFF
1808 #define   PORT_PLL_N_MASK		(0x0F << PORT_PLL_N_SHIFT)
1811 #define   PORT_PLL_M2_FRAC_MASK		0x3FFFFF
1815 #define   PORT_PLL_PROP_COEFF_MASK	0xF
1816 #define   PORT_PLL_INT_COEFF_MASK	(0x1F << 8)
1818 #define   PORT_PLL_GAIN_CTL_MASK	(0x07 << 16)
1821 #define   PORT_PLL_TARGET_CNT_MASK	0x3FF
1824 #define  PORT_PLL_LOCK_THRESHOLD_MASK	(0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1828 #define  PORT_PLL_DCO_AMP_MASK		0x3c00
1837 #define _PORT_CL1CM_DW0_A		0x162000
1838 #define _PORT_CL1CM_DW0_BC		0x6C000
1843 #define _PORT_CL1CM_DW9_A		0x162024
1844 #define _PORT_CL1CM_DW9_BC		0x6C024
1846 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
1849 #define _PORT_CL1CM_DW10_A		0x162028
1850 #define _PORT_CL1CM_DW10_BC		0x6C028
1852 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
1855 #define _PORT_CL1CM_DW28_A		0x162070
1856 #define _PORT_CL1CM_DW28_BC		0x6C070
1859 #define   SUS_CLK_CONFIG		0x3
1862 #define _PORT_CL1CM_DW30_A		0x162078
1863 #define _PORT_CL1CM_DW30_BC		0x6C078
1870 #define _ICL_COMBOPHY_A			0x162000
1871 #define _ICL_COMBOPHY_B			0x6C000
1872 #define _EHL_COMBOPHY_C			0x160000
1873 #define _RKL_COMBOPHY_D			0x161000
1883 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
1886 #define   SUS_CLOCK_CONFIG		(3 << 0)
1892 #define  PWR_UP_ALL_LANES		(0x0 << 4)
1893 #define  PWR_DOWN_LN_3_2_1		(0xe << 4)
1894 #define  PWR_DOWN_LN_3_2		(0xc << 4)
1895 #define  PWR_DOWN_LN_3			(0x8 << 4)
1896 #define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
1897 #define  PWR_DOWN_LN_1_0		(0x3 << 4)
1898 #define  PWR_DOWN_LN_3_1		(0xa << 4)
1899 #define  PWR_DOWN_LN_3_1_0		(0xb << 4)
1900 #define  PWR_DOWN_LN_MASK		(0xf << 4)
1906 #define   ICL_LANE_ENABLE_AUX		(1 << 0)
1909 #define _ICL_PORT_COMP			0x100
1913 #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
1914 #define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
1917 #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
1920 #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
1922 #define   PROCESS_INFO_DOT_0		(0 << 26)
1927 #define   VOLTAGE_INFO_0_85V		(0 << 24)
1936 #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
1939 #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
1943 #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
1944 #define _CNL_PORT_PCS_DW1_GRP_B		0x162384
1945 #define _CNL_PORT_PCS_DW1_GRP_C		0x162B04
1946 #define _CNL_PORT_PCS_DW1_GRP_D		0x162B84
1947 #define _CNL_PORT_PCS_DW1_GRP_F		0x162A04
1948 #define _CNL_PORT_PCS_DW1_LN0_AE	0x162404
1949 #define _CNL_PORT_PCS_DW1_LN0_B		0x162604
1950 #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
1951 #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
1952 #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
1968 #define _ICL_PORT_PCS_AUX		0x300
1969 #define _ICL_PORT_PCS_GRP		0x600
1970 #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
1979 #define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
1980 #define   DCC_MODE_SELECT_MASK		(0x3 << 20)
1981 #define   DCC_MODE_SELECT_CONTINUOSLY	(0x3 << 20)
1983 #define   LATENCY_OPTIM_MASK		(0x3 << 2)
1987 #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
1988 #define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
1989 #define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
1990 #define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
1991 #define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
1992 #define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
1993 #define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
1994 #define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
1995 #define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
1996 #define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
2014 #define _ICL_PORT_TX_AUX		0x380
2015 #define _ICL_PORT_TX_GRP		0x680
2016 #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
2029 #define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
2032 #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
2033 #define   SWING_SEL_LOWER_MASK		(0x7 << 11)
2034 #define   FRC_LATENCY_OPTIM_MASK	(0x7 << 8)
2036 #define   RCOMP_SCALAR(x)		((x) << 0)
2037 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
2039 #define _CNL_PORT_TX_DW4_LN0_AE		0x162450
2040 #define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
2048 #define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
2052 #define   POST_CURSOR_1_MASK		(0x3F << 12)
2054 #define   POST_CURSOR_2_MASK		(0x3F << 6)
2055 #define   CURSOR_COEFF(x)		((x) << 0)
2056 #define   CURSOR_COEFF_MASK		(0x3F << 0)
2062 #define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
2067 #define   SCALING_MODE_SEL_MASK		(0x7 << 18)
2069 #define   RTERM_SELECT_MASK		(0x7 << 3)
2075 #define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
2078 #define   N_SCALAR_MASK			(0x7F << 24)
2082 #define ICL_PORT_TX_DW8_LN0(phy)		_MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
2085 …   ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2	REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
2087 #define _ICL_DPHY_CHKN_REG			0x194
2094 #define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
2095 #define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
2096 #define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
2097 #define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
2098 #define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
2099 #define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
2100 #define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
2101 #define MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
2107 #define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
2108 #define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
2109 #define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
2110 #define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
2111 #define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
2112 #define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
2113 #define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
2114 #define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
2121 #define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
2122 #define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
2123 #define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
2124 #define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
2125 #define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
2126 #define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
2127 #define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
2128 #define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
2134 #define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
2135 #define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
2136 #define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
2137 #define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
2138 #define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
2139 #define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
2140 #define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
2141 #define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
2148 #define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
2149 #define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
2150 #define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
2151 #define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
2152 #define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
2153 #define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
2154 #define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
2155 #define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
2161 #define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
2162 #define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
2163 #define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
2164 #define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
2165 #define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
2166 #define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
2167 #define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
2168 #define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
2173 #define   CRI_TXDEEMPH_OVERRIDE_17_12(x)		((x) << 0)
2174 #define   CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
2176 #define MG_TX_DRVCTRL_TX1LN0_TXPORT1			0x168144
2177 #define MG_TX_DRVCTRL_TX1LN1_TXPORT1			0x168544
2178 #define MG_TX_DRVCTRL_TX1LN0_TXPORT2			0x169144
2179 #define MG_TX_DRVCTRL_TX1LN1_TXPORT2			0x169544
2180 #define MG_TX_DRVCTRL_TX1LN0_TXPORT3			0x16A144
2181 #define MG_TX_DRVCTRL_TX1LN1_TXPORT3			0x16A544
2182 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4			0x16B144
2183 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4			0x16B544
2189 #define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
2190 #define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
2191 #define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
2192 #define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
2193 #define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
2194 #define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
2195 #define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
2196 #define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
2202 #define   CRI_TXDEEMPH_OVERRIDE_11_6_MASK		(0x3F << 24)
2205 #define   CRI_TXDEEMPH_OVERRIDE_5_0_MASK		(0x3F << 16)
2207 #define   CRI_LOADGEN_SEL_MASK				(0x3 << 12)
2209 #define MG_CLKHUB_LN0_PORT1			0x16839C
2210 #define MG_CLKHUB_LN1_PORT1			0x16879C
2211 #define MG_CLKHUB_LN0_PORT2			0x16939C
2212 #define MG_CLKHUB_LN1_PORT2			0x16979C
2213 #define MG_CLKHUB_LN0_PORT3			0x16A39C
2214 #define MG_CLKHUB_LN1_PORT3			0x16A79C
2215 #define MG_CLKHUB_LN0_PORT4			0x16B39C
2216 #define MG_CLKHUB_LN1_PORT4			0x16B79C
2223 #define MG_TX_DCC_TX1LN0_PORT1			0x168110
2224 #define MG_TX_DCC_TX1LN1_PORT1			0x168510
2225 #define MG_TX_DCC_TX1LN0_PORT2			0x169110
2226 #define MG_TX_DCC_TX1LN1_PORT2			0x169510
2227 #define MG_TX_DCC_TX1LN0_PORT3			0x16A110
2228 #define MG_TX_DCC_TX1LN1_PORT3			0x16A510
2229 #define MG_TX_DCC_TX1LN0_PORT4			0x16B110
2230 #define MG_TX_DCC_TX1LN1_PORT4			0x16B510
2235 #define MG_TX_DCC_TX2LN0_PORT1			0x168090
2236 #define MG_TX_DCC_TX2LN1_PORT1			0x168490
2237 #define MG_TX_DCC_TX2LN0_PORT2			0x169090
2238 #define MG_TX_DCC_TX2LN1_PORT2			0x169490
2239 #define MG_TX_DCC_TX2LN0_PORT3			0x16A090
2240 #define MG_TX_DCC_TX2LN1_PORT3			0x16A490
2241 #define MG_TX_DCC_TX2LN0_PORT4			0x16B090
2242 #define MG_TX_DCC_TX2LN1_PORT4			0x16B490
2248 #define   CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK	(0x3 << 25)
2251 #define MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
2252 #define MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
2253 #define MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
2254 #define MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
2255 #define MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
2256 #define MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
2257 #define MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
2258 #define MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
2269 #define _PORT_CL2CM_DW6_A		0x162358
2270 #define _PORT_CL2CM_DW6_BC		0x6C358
2274 #define FIA1_BASE			0x163000
2275 #define FIA2_BASE			0x16E000
2276 #define FIA3_BASE			0x16F000
2281 #define PORT_TX_DFLEXDPMLE1(fia)		_MMIO_FIA((fia),  0x008C0)
2282 #define   DFLEXDPMLE1_DPMLETC_MASK(idx)		(0xf << (4 * (idx)))
2290 #define _PORT_REF_DW3_A			0x16218C
2291 #define _PORT_REF_DW3_BC		0x6C18C
2295 #define _PORT_REF_DW6_A			0x162198
2296 #define _PORT_REF_DW6_BC		0x6C198
2298 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
2300 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
2302 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
2303 #define   GRC_CODE_NOM_MASK		0xFF
2306 #define _PORT_REF_DW8_A			0x1621A0
2307 #define _PORT_REF_DW8_BC		0x6C1A0
2313 #define _PORT_PCS_DW10_LN01_A		0x162428
2314 #define _PORT_PCS_DW10_LN01_B		0x6C428
2315 #define _PORT_PCS_DW10_LN01_C		0x6C828
2316 #define _PORT_PCS_DW10_GRP_A		0x162C28
2317 #define _PORT_PCS_DW10_GRP_B		0x6CC28
2318 #define _PORT_PCS_DW10_GRP_C		0x6CE28
2329 #define _PORT_PCS_DW12_LN01_A		0x162430
2330 #define _PORT_PCS_DW12_LN01_B		0x6C430
2331 #define _PORT_PCS_DW12_LN01_C		0x6C830
2332 #define _PORT_PCS_DW12_LN23_A		0x162630
2333 #define _PORT_PCS_DW12_LN23_B		0x6C630
2334 #define _PORT_PCS_DW12_LN23_C		0x6CA30
2335 #define _PORT_PCS_DW12_GRP_A		0x162c30
2336 #define _PORT_PCS_DW12_GRP_B		0x6CC30
2337 #define _PORT_PCS_DW12_GRP_C		0x6CE30
2339 #define   LANE_STAGGER_MASK		0x1F
2351 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
2352 					  ((lane) & 1) * 0x80)
2354 #define _PORT_TX_DW2_LN0_A		0x162508
2355 #define _PORT_TX_DW2_LN0_B		0x6C508
2356 #define _PORT_TX_DW2_LN0_C		0x6C908
2357 #define _PORT_TX_DW2_GRP_A		0x162D08
2358 #define _PORT_TX_DW2_GRP_B		0x6CD08
2359 #define _PORT_TX_DW2_GRP_C		0x6CF08
2367 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
2369 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
2371 #define _PORT_TX_DW3_LN0_A		0x16250C
2372 #define _PORT_TX_DW3_LN0_B		0x6C50C
2373 #define _PORT_TX_DW3_LN0_C		0x6C90C
2374 #define _PORT_TX_DW3_GRP_A		0x162D0C
2375 #define _PORT_TX_DW3_GRP_B		0x6CD0C
2376 #define _PORT_TX_DW3_GRP_C		0x6CF0C
2386 #define _PORT_TX_DW4_LN0_A		0x162510
2387 #define _PORT_TX_DW4_LN0_B		0x6C510
2388 #define _PORT_TX_DW4_LN0_C		0x6C910
2389 #define _PORT_TX_DW4_GRP_A		0x162D10
2390 #define _PORT_TX_DW4_GRP_B		0x6CD10
2391 #define _PORT_TX_DW4_GRP_C		0x6CF10
2399 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
2401 #define _PORT_TX_DW5_LN0_A		0x162514
2402 #define _PORT_TX_DW5_LN0_B		0x6C514
2403 #define _PORT_TX_DW5_LN0_C		0x6C914
2404 #define _PORT_TX_DW5_GRP_A		0x162D14
2405 #define _PORT_TX_DW5_GRP_B		0x6CD14
2406 #define _PORT_TX_DW5_GRP_C		0x6CF14
2416 #define _PORT_TX_DW14_LN0_A		0x162538
2417 #define _PORT_TX_DW14_LN0_B		0x6C538
2418 #define _PORT_TX_DW14_LN0_C		0x6C938
2427 #define UAIMI_SPR1			_MMIO(0x4F074)
2429 #define SKL_VCCIO_MASK			0x1
2431 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
2441  * [0-7]  @ 0x2000 gen2,gen3
2442  * [8-15] @ 0x3000 945,g33,pnv
2444  * [0-15] @ 0x3000 gen4,gen5
2446  * [0-15] @ 0x100000 gen6,vlv,chv
2447  * [0-31] @ 0x100000 gen7+
2449 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2450 #define   I830_FENCE_START_MASK		0x07f80000
2454 #define   I830_FENCE_REG_VALID		(1 << 0)
2459 #define   I915_FENCE_START_MASK		0x0ff00000
2462 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
2463 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
2466 #define   I965_FENCE_REG_VALID		(1 << 0)
2467 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
2469 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
2470 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
2472 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
2476 #define TILECTL				_MMIO(0x101000)
2477 #define   TILECTL_SWZCTL			(1 << 0)
2485 #define PGTBL_CTL	_MMIO(0x02020)
2486 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
2487 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
2488 #define PGTBL_ER	_MMIO(0x02024)
2489 #define PRB0_BASE	(0x2030 - 0x30)
2490 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
2491 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
2492 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
2493 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
2494 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
2495 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
2496 #define RENDER_RING_BASE	0x02000
2497 #define BSD_RING_BASE		0x04000
2498 #define GEN6_BSD_RING_BASE	0x12000
2499 #define GEN8_BSD2_RING_BASE	0x1c000
2500 #define GEN11_BSD_RING_BASE	0x1c0000
2501 #define GEN11_BSD2_RING_BASE	0x1c4000
2502 #define GEN11_BSD3_RING_BASE	0x1d0000
2503 #define GEN11_BSD4_RING_BASE	0x1d4000
2504 #define VEBOX_RING_BASE		0x1a000
2505 #define GEN11_VEBOX_RING_BASE		0x1c8000
2506 #define GEN11_VEBOX2_RING_BASE		0x1d8000
2507 #define BLT_RING_BASE		0x22000
2508 #define RING_TAIL(base)		_MMIO((base) + 0x30)
2509 #define RING_HEAD(base)		_MMIO((base) + 0x34)
2510 #define RING_START(base)	_MMIO((base) + 0x38)
2511 #define RING_CTL(base)		_MMIO((base) + 0x3c)
2513 #define RING_SYNC_0(base)	_MMIO((base) + 0x40)
2514 #define RING_SYNC_1(base)	_MMIO((base) + 0x44)
2515 #define RING_SYNC_2(base)	_MMIO((base) + 0x48)
2529 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
2530 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
2531 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
2532 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
2533 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
2536 #define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
2538 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
2540 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
2541 #define   GTT_CACHE_EN_ALL	0xF0007FFF
2542 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
2543 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
2544 #define ARB_MODE		_MMIO(0x4030)
2547 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
2548 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
2550 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
2552 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
2553 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
2555 #define GAMTARBMODE		_MMIO(0x04a08)
2558 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
2559 #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100 * (engine)->hw_id)
2560 #define GEN8_RING_FAULT_REG	_MMIO(0x4094)
2561 #define GEN12_RING_FAULT_REG	_MMIO(0xcec4)
2562 #define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
2564 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
2565 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2566 #define   RING_FAULT_VALID	(1 << 0)
2567 #define DONE_REG		_MMIO(0x40b0)
2568 #define GEN12_GAM_DONE		_MMIO(0xcf68)
2569 #define GEN8_PRIVATE_PAT_LO	_MMIO(0x40e0)
2570 #define GEN8_PRIVATE_PAT_HI	_MMIO(0x40e0 + 4)
2571 #define GEN10_PAT_INDEX(index)	_MMIO(0x40e0 + (index) * 4)
2572 #define GEN12_PAT_INDEX(index)	_MMIO(0x4800 + (index) * 4)
2573 #define BSD_HWS_PGA_GEN7	_MMIO(0x04180)
2574 #define GEN12_GFX_CCS_AUX_NV	_MMIO(0x4208)
2575 #define GEN12_VD0_AUX_NV	_MMIO(0x4218)
2576 #define GEN12_VD1_AUX_NV	_MMIO(0x4228)
2577 #define GEN12_VD2_AUX_NV	_MMIO(0x4298)
2578 #define GEN12_VD3_AUX_NV	_MMIO(0x42A8)
2579 #define GEN12_VE0_AUX_NV	_MMIO(0x4238)
2580 #define GEN12_VE1_AUX_NV	_MMIO(0x42B8)
2581 #define   AUX_INV		REG_BIT(0)
2582 #define BLT_HWS_PGA_GEN7	_MMIO(0x04280)
2583 #define VEBOX_HWS_PGA_GEN7	_MMIO(0x04380)
2584 #define RING_ACTHD(base)	_MMIO((base) + 0x74)
2585 #define RING_ACTHD_UDW(base)	_MMIO((base) + 0x5c)
2586 #define RING_NOPID(base)	_MMIO((base) + 0x94)
2587 #define RING_IMR(base)		_MMIO((base) + 0xa8)
2588 #define RING_HWSTAM(base)	_MMIO((base) + 0x98)
2589 #define RING_TIMESTAMP(base)		_MMIO((base) + 0x358)
2590 #define RING_TIMESTAMP_UDW(base)	_MMIO((base) + 0x358 + 4)
2591 #define   TAIL_ADDR		0x001FFFF8
2592 #define   HEAD_WRAP_COUNT	0xFFE00000
2593 #define   HEAD_WRAP_ONE		0x00200000
2594 #define   HEAD_ADDR		0x001FFFFC
2595 #define   RING_NR_PAGES		0x001FF000
2596 #define   RING_REPORT_MASK	0x00000006
2597 #define   RING_REPORT_64K	0x00000002
2598 #define   RING_REPORT_128K	0x00000004
2599 #define   RING_NO_REPORT	0x00000000
2600 #define   RING_VALID_MASK	0x00000001
2601 #define   RING_VALID		0x00000001
2602 #define   RING_INVALID		0x00000000
2603 #define   RING_WAIT_I8XX	(1 << 0) /* gen2, PRBx_HEAD */
2608 #define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)
2609 #define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)
2611 #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
2613 #define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
2618 #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
2619 #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
2620 #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
2621 #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
2622 #define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
2628 #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
2630 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2633 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2634 #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2637 #define GAMT_CHKN_BIT_REG	_MMIO(0x4ab8)
2642 #if 0
2643 #define PRB0_TAIL	_MMIO(0x2030)
2644 #define PRB0_HEAD	_MMIO(0x2034)
2645 #define PRB0_START	_MMIO(0x2038)
2646 #define PRB0_CTL	_MMIO(0x203c)
2647 #define PRB1_TAIL	_MMIO(0x2040) /* 915+ only */
2648 #define PRB1_HEAD	_MMIO(0x2044) /* 915+ only */
2649 #define PRB1_START	_MMIO(0x2048) /* 915+ only */
2650 #define PRB1_CTL	_MMIO(0x204c) /* 915+ only */
2652 #define IPEIR_I965	_MMIO(0x2064)
2653 #define IPEHR_I965	_MMIO(0x2068)
2654 #define GEN7_SC_INSTDONE	_MMIO(0x7100)
2655 #define GEN12_SC_INSTDONE_EXTRA		_MMIO(0x7104)
2656 #define GEN12_SC_INSTDONE_EXTRA2	_MMIO(0x7108)
2657 #define GEN7_SAMPLER_INSTDONE	_MMIO(0xe160)
2658 #define GEN7_ROW_INSTDONE	_MMIO(0xe164)
2659 #define GEN8_MCR_SELECTOR		_MMIO(0xfdc)
2664 #define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
2665 #define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
2666 #define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
2667 #define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
2668 #define RING_IPEIR(base)	_MMIO((base) + 0x64)
2669 #define RING_IPEHR(base)	_MMIO((base) + 0x68)
2670 #define RING_EIR(base)		_MMIO((base) + 0xb0)
2671 #define RING_EMR(base)		_MMIO((base) + 0xb4)
2672 #define RING_ESR(base)		_MMIO((base) + 0xb8)
2678 #define RING_INSTDONE(base)	_MMIO((base) + 0x6c)
2679 #define RING_INSTPS(base)	_MMIO((base) + 0x70)
2680 #define RING_DMA_FADD(base)	_MMIO((base) + 0x78)
2681 #define RING_DMA_FADD_UDW(base)	_MMIO((base) + 0x60) /* gen8+ */
2682 #define RING_INSTPM(base)	_MMIO((base) + 0xc0)
2683 #define RING_MI_MODE(base)	_MMIO((base) + 0x9c)
2684 #define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84)
2685 #define INSTPS		_MMIO(0x2070) /* 965+ only */
2686 #define GEN4_INSTDONE1	_MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2687 #define ACTHD_I965	_MMIO(0x2074)
2688 #define HWS_PGA		_MMIO(0x2080)
2689 #define HWS_ADDRESS_MASK	0xfffff000
2691 #define PWRCTXA		_MMIO(0x2088) /* 965GM+ only */
2692 #define   PWRCTX_EN	(1 << 0)
2693 #define IPEIR(base)	_MMIO((base) + 0x88)
2694 #define IPEHR(base)	_MMIO((base) + 0x8c)
2695 #define GEN2_INSTDONE	_MMIO(0x2090)
2696 #define NOPID		_MMIO(0x2094)
2697 #define HWSTAM		_MMIO(0x2098)
2698 #define DMA_FADD_I8XX(base)	_MMIO((base) + 0xd0)
2699 #define RING_BBSTATE(base)	_MMIO((base) + 0x110)
2701 #define RING_SBBADDR(base)	_MMIO((base) + 0x114) /* hsw+ */
2702 #define RING_SBBSTATE(base)	_MMIO((base) + 0x118) /* hsw+ */
2703 #define RING_SBBADDR_UDW(base)	_MMIO((base) + 0x11c) /* gen8+ */
2704 #define RING_BBADDR(base)	_MMIO((base) + 0x140)
2705 #define RING_BBADDR_UDW(base)	_MMIO((base) + 0x168) /* gen8+ */
2706 #define RING_BB_PER_CTX_PTR(base)	_MMIO((base) + 0x1c0) /* gen8+ */
2707 #define RING_INDIRECT_CTX(base)		_MMIO((base) + 0x1c4) /* gen8+ */
2708 #define RING_INDIRECT_CTX_OFFSET(base)	_MMIO((base) + 0x1c8) /* gen8+ */
2709 #define RING_CTX_TIMESTAMP(base)	_MMIO((base) + 0x3a8) /* gen8+ */
2711 #define ERROR_GEN6	_MMIO(0x40a0)
2712 #define GEN7_ERR_INT	_MMIO(0x44040)
2721 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
2724 #define GEN8_FAULT_TLB_DATA0		_MMIO(0x4b10)
2725 #define GEN8_FAULT_TLB_DATA1		_MMIO(0x4b14)
2726 #define GEN12_FAULT_TLB_DATA0		_MMIO(0xceb8)
2727 #define GEN12_FAULT_TLB_DATA1		_MMIO(0xcebc)
2728 #define   FAULT_VA_HIGH_BITS		(0xf << 0)
2731 #define GEN12_AUX_ERR_DBG		_MMIO(0x43f4)
2733 #define FPGA_DBG		_MMIO(0x42300)
2736 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
2739 #define   CLAIM_ER_CTR_MASK	0xffff
2741 #define DERRMR		_MMIO(0x44050)
2743 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
2765 #define _3D_CHICKEN	_MMIO(0x2084)
2767 #define _3D_CHICKEN2	_MMIO(0x208c)
2769 #define FF_SLICE_CHICKEN	_MMIO(0x2088)
2777 #define _3D_CHICKEN3	_MMIO(0x2090)
2785 #define MI_MODE		_MMIO(0x209c)
2792 #define GEN6_GT_MODE	_MMIO(0x20d0)
2793 #define GEN7_GT_MODE	_MMIO(0x7008)
2795 #define   GEN6_WIZ_HASHING_8x8				GEN6_WIZ_HASHING(0, 0)
2796 #define   GEN6_WIZ_HASHING_8x4				GEN6_WIZ_HASHING(0, 1)
2797 #define   GEN6_WIZ_HASHING_16x4				GEN6_WIZ_HASHING(1, 0)
2800 #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
2804 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2809 #define GEN8_STATE_ACK		_MMIO(0x20F0)
2810 #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
2811 #define GEN9_STATE_ACK_SLICE2	_MMIO(0x2100)
2820 #define GFX_MODE	_MMIO(0x2520)
2821 #define GFX_MODE_GEN7	_MMIO(0x229c)
2822 #define RING_MODE_GEN7(base)	_MMIO((base) + 0x29c)
2833 #define   GFX_FORWARD_VBLANK_NEVER	(0 << 5)
2839 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
2840 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
2841 #define SCPD0		_MMIO(0x209c) /* 915+ only */
2844 #define GEN2_IER	_MMIO(0x20a0)
2845 #define GEN2_IIR	_MMIO(0x20a4)
2846 #define GEN2_IMR	_MMIO(0x20a8)
2847 #define GEN2_ISR	_MMIO(0x20ac)
2848 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
2851 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
2852 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
2853 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
2854 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
2855 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
2856 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
2857 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
2861 #define EIR		_MMIO(0x20b0)
2862 #define EMR		_MMIO(0x20b4)
2863 #define ESR		_MMIO(0x20b8)
2869 #define   I915_ERROR_INSTRUCTION			(1 << 0)
2870 #define INSTPM	        _MMIO(0x20c0)
2878 #define ACTHD(base)	_MMIO((base) + 0xc8)
2879 #define MEM_MODE	_MMIO(0x20cc)
2883 #define FW_BLC		_MMIO(0x20d8)
2884 #define FW_BLC2		_MMIO(0x20dc)
2885 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
2889 #define MM_BURST_LENGTH     0x00700000
2890 #define MM_FIFO_WATERMARK   0x0001F000
2891 #define LM_BURST_LENGTH     0x00000700
2892 #define LM_FIFO_WATERMARK   0x0000001F
2893 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
2895 #define _MBUS_ABOX0_CTL			0x45038
2896 #define _MBUS_ABOX1_CTL			0x45048
2897 #define _MBUS_ABOX2_CTL			0x4504C
2903 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
2905 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
2907 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
2908 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
2910 #define _PIPEA_MBUS_DBOX_CTL		0x7003C
2911 #define _PIPEB_MBUS_DBOX_CTL		0x7103C
2916 #define MBUS_DBOX_B_CREDIT_MASK		(0x1F << 8)
2918 #define MBUS_DBOX_A_CREDIT_MASK		(0xF << 0)
2919 #define MBUS_DBOX_A_CREDIT(x)		((x) << 0)
2921 #define MBUS_UBOX_CTL			_MMIO(0x4503C)
2922 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
2923 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
2925 #define HDPORT_STATE			_MMIO(0x45050)
2929 #define   HDPORT_ENABLED		REG_BIT(0)
2946 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
2973 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
2983 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
2990 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
2991 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
2993 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
2995 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
2997 #define CACHE_MODE_0	_MMIO(0x2120) /* 915+ only */
3005 #define   CM0_RC_OP_FLUSH_DISABLE (1 << 0)
3006 #define GFX_FLSH_CNTL	_MMIO(0x2170) /* 915+ only */
3007 #define GFX_FLSH_CNTL_GEN6	_MMIO(0x101008)
3008 #define   GFX_FLSH_CNTL_EN	(1 << 0)
3009 #define ECOSKPD		_MMIO(0x21d0)
3012 #define   ECO_FLIP_DONE		(1 << 0)
3014 #define CACHE_MODE_0_GEN7	_MMIO(0x7000) /* IVB+ */
3015 #define RC_OP_FLUSH_ENABLE (1 << 0)
3017 #define CACHE_MODE_1		_MMIO(0x7004) /* IVB+ */
3022 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
3026 #define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)
3027 #define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)
3032 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
3033 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
3035 #define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
3039 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
3041 #define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
3042 #define   HSW_F1_EU_DIS_10EUS		0
3046 #define CHV_FUSE_GT			_MMIO(VLV_DISPLAY_BASE + 0x2168)
3050 #define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
3052 #define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
3054 #define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
3056 #define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
3058 #define GEN8_FUSE2			_MMIO(0x9120)
3060 #define   GEN8_F2_SS_DIS_MASK		(0x7 << GEN8_F2_SS_DIS_SHIFT)
3062 #define   GEN8_F2_S_ENA_MASK		(0x7 << GEN8_F2_S_ENA_SHIFT)
3065 #define   GEN9_F2_SS_DIS_MASK		(0xf << GEN9_F2_SS_DIS_SHIFT)
3068 #define   GEN10_F2_S_ENA_MASK		(0x3f << GEN10_F2_S_ENA_SHIFT)
3070 #define   GEN10_F2_SS_DIS_MASK		(0xf << GEN10_F2_SS_DIS_SHIFT)
3072 #define	GEN10_MIRROR_FUSE3		_MMIO(0x9118)
3074 #define GEN10_L3BANK_MASK   0x0F
3076 #define GEN8_EU_DISABLE0		_MMIO(0x9134)
3077 #define   GEN8_EU_DIS0_S0_MASK		0xffffff
3079 #define   GEN8_EU_DIS0_S1_MASK		(0xff << GEN8_EU_DIS0_S1_SHIFT)
3081 #define GEN8_EU_DISABLE1		_MMIO(0x9138)
3082 #define   GEN8_EU_DIS1_S1_MASK		0xffff
3084 #define   GEN8_EU_DIS1_S2_MASK		(0xffff << GEN8_EU_DIS1_S2_SHIFT)
3086 #define GEN8_EU_DISABLE2		_MMIO(0x913c)
3087 #define   GEN8_EU_DIS2_S2_MASK		0xff
3089 #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice) * 0x4)
3091 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
3092 #define   GEN10_EU_DIS_SS_MASK		0xff
3094 #define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
3095 #define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
3097 #define   GEN11_GT_VEBOX_DISABLE_MASK	(0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT)
3099 #define GEN11_EU_DISABLE _MMIO(0x9134)
3100 #define GEN11_EU_DIS_MASK 0xFF
3102 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
3103 #define GEN11_GT_S_ENA_MASK 0xFF
3105 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
3107 #define GEN12_GT_DSS_ENABLE _MMIO(0x913C)
3109 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
3110 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
3139 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
3146 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
3184 #define I915_ASLE_INTERRUPT				(1 << 0)
3187 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
3188 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
3191 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
3192 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
3194 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
3195 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
3196 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
3203 #define GEN6_BSD_RNCID			_MMIO(0x12198)
3205 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
3206 #define   GEN7_FF_SCHED_MASK		0x0077070
3209 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
3210 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
3211 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
3212 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
3214 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
3215 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
3216 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
3217 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
3218 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
3219 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
3220 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
3221 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
3227 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
3228 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
3229 #define FBC_CONTROL		_MMIO(0x3208)
3239 #define   FBC_CTL_FENCENO_MASK	REG_GENMASK(3, 0)
3241 #define FBC_COMMAND		_MMIO(0x320c)
3242 #define   FBC_CMD_COMPRESS	(1 << 0)
3243 #define FBC_STATUS		_MMIO(0x3210)
3247 #define   FBC_STAT_CURRENT_LINE_SHIFT	(0)
3248 #define FBC_CONTROL2		_MMIO(0x3214)
3249 #define   FBC_CTL_FENCE_DBL	(0 << 4)
3250 #define   FBC_CTL_IDLE_IMM	(0 << 2)
3255 #define   FBC_CTL_PLANE(plane)	((plane) << 0)
3256 #define FBC_FENCE_OFF		_MMIO(0x3218) /* BSpec typo has 321Bh */
3257 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4)
3261 #define FBC_LLC_READ_CTRL	_MMIO(0x9044)
3265 #define DPFC_CB_BASE		_MMIO(0x3200)
3266 #define DPFC_CONTROL		_MMIO(0x3208)
3274 #define   DPFC_CTL_LIMIT_1X	(0 << 6)
3277 #define DPFC_RECOMP_CTL		_MMIO(0x320c)
3280 #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3281 #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3282 #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3283 #define DPFC_STATUS		_MMIO(0x3210)
3285 #define   DPFC_INVAL_SEG_MASK	(0x07ff0000)
3286 #define   DPFC_COMP_SEG_SHIFT	(0)
3287 #define   DPFC_COMP_SEG_MASK	(0x000007ff)
3288 #define DPFC_STATUS2		_MMIO(0x3214)
3289 #define DPFC_FENCE_YOFF		_MMIO(0x3218)
3290 #define DPFC_CHICKEN		_MMIO(0x3224)
3294 #define ILK_DPFC_CB_BASE	_MMIO(0x43200)
3295 #define ILK_DPFC_CONTROL	_MMIO(0x43208)
3298 #define   DPFC_RESERVED		(0x1FFFFF00)
3299 #define ILK_DPFC_RECOMP_CTL	_MMIO(0x4320c)
3300 #define ILK_DPFC_STATUS		_MMIO(0x43210)
3301 #define  ILK_DPFC_COMP_SEG_MASK	0x7ff
3302 #define IVB_FBC_STATUS2		_MMIO(0x43214)
3303 #define  IVB_FBC_COMP_SEG_MASK	0x7ff
3304 #define  BDW_FBC_COMP_SEG_MASK	0xfff
3305 #define ILK_DPFC_FENCE_YOFF	_MMIO(0x43218)
3306 #define ILK_DPFC_CHICKEN	_MMIO(0x43224)
3310 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
3311 #define   ILK_FBC_RT_VALID	(1 << 0)
3314 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
3324 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
3326 #define DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
3329 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
3330 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
3332 #define IPS_CTL		_MMIO(0x43408)
3335 #define MSG_FBC_REND_STATE	_MMIO(0x50380)
3342 #define GPIO(gpio)		_MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
3345 # define GPIO_CLOCK_DIR_MASK		(1 << 0)
3346 # define GPIO_CLOCK_DIR_IN		(0 << 1)
3353 # define GPIO_DATA_DIR_IN		(0 << 9)
3360 #define GMBUS0			_MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3362 #define   GMBUS_RATE_100KHZ	(0 << 8)
3369 #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3373 #define   GMBUS_CYCLE_NONE	(0 << 25)
3382 #define   GMBUS_SLAVE_READ	(1 << 0)
3383 #define   GMBUS_SLAVE_WRITE	(0 << 0)
3384 #define GMBUS2			_MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3392 #define GMBUS3			_MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3393 #define GMBUS4			_MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3398 #define   GMBUS_HW_RDY_EN	(1 << 0)
3399 #define GMBUS5			_MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3405 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
3406 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
3407 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
3410 #define VGA0	_MMIO(0x6000)
3411 #define VGA1	_MMIO(0x6004)
3412 #define VGA_PD	_MMIO(0x6010)
3415 #define   VGA0_PD_P1_SHIFT	0
3416 #define   VGA0_PD_P1_MASK	(0x1f << 0)
3420 #define   VGA1_PD_P1_MASK	(0x1f << 8)
3431 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3433 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
3435 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
3436 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
3437 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
3442 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
3443 #define   DPLL_PORTB_READY_MASK		(0xf)
3445 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
3448 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
3449 #define   DPLL_PORTD_READY_MASK		(0xf)
3450 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3452 #define   PHY_LDO_DELAY_0NS			0x0
3453 #define   PHY_LDO_DELAY_200NS			0x1
3454 #define   PHY_LDO_DELAY_600NS			0x2
3457 #define   PHY_CH_SU_PSR				0x1
3458 #define   PHY_CH_DEEP_PSR			0x7
3461 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3470 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
3476 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
3486 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
3487 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
3495 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3500 #define   SDVO_MULTIPLIER_MASK			0x000000ff
3502 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
3504 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
3505 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
3506 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
3514 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
3517 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
3536 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
3543 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
3544 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
3546 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
3548 #define _FPA0	0x6040
3549 #define _FPA1	0x6044
3550 #define _FPB0	0x6048
3551 #define _FPB1	0x604c
3554 #define   FP_N_DIV_MASK		0x003f0000
3555 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
3557 #define   FP_M1_DIV_MASK	0x00003f00
3559 #define   FP_M2_DIV_MASK	0x0000003f
3560 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
3561 #define   FP_M2_DIV_SHIFT		 0
3562 #define DPLL_TEST	_MMIO(0x606c)
3563 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
3572 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
3573 #define D_STATE		_MMIO(0x6104)
3577 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
3578 #define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)
3615 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
3616 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
3618 #define RENCLK_GATE_D1		_MMIO(0x6204)
3634 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
3651 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
3680 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
3682 #define RENCLK_GATE_D2		_MMIO(0x6208)
3687 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
3690 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
3691 #define DEUC			_MMIO(0x6214)          /* CRL only */
3693 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
3696 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
3698 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
3700 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
3701 #define   CZCLK_FREQ_MASK	0xf
3703 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
3710 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
3715 #define _PALETTE_A		0xa000
3716 #define _PALETTE_B		0xa800
3717 #define _CHV_PALETTE_C		0xc000
3720 #define PALETTE_BLUE_MASK       REG_GENMASK(7, 0)
3732  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3738 #define MCHBAR_MIRROR_BASE	0x10000
3740 #define MCHBAR_MIRROR_BASE_SNB	0x140000
3742 #define CTG_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x34)
3743 #define ELK_STOLEN_RESERVED		_MMIO(MCHBAR_MIRROR_BASE + 0x48)
3744 #define G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
3745 #define G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
3746 #define G4X_STOLEN_RESERVED_ENABLE	(1 << 0)
3749 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3752 #define DCC			_MMIO(MCHBAR_MIRROR_BASE + 0x200)
3753 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
3754 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
3755 #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
3756 #define DCC_ADDRESSING_MODE_MASK			(3 << 0)
3759 #define DCC2			_MMIO(MCHBAR_MIRROR_BASE + 0x204)
3763 #define CSHRDDR3CTL            _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3767 #define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)
3768 #define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)
3771 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3772 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3773 #define MAD_DIMM_C2			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3774 #define   MAD_DIMM_ECC_MASK		(0x3 << 24)
3775 #define   MAD_DIMM_ECC_OFF		(0x0 << 24)
3776 #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF	(0x1 << 24)
3777 #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON	(0x2 << 24)
3778 #define   MAD_DIMM_ECC_ON		(0x3 << 24)
3779 #define   MAD_DIMM_ENH_INTERLEAVE	(0x1 << 22)
3780 #define   MAD_DIMM_RANK_INTERLEAVE	(0x1 << 21)
3781 #define   MAD_DIMM_B_WIDTH_X16		(0x1 << 20) /* X8 chips if unset */
3782 #define   MAD_DIMM_A_WIDTH_X16		(0x1 << 19) /* X8 chips if unset */
3783 #define   MAD_DIMM_B_DUAL_RANK		(0x1 << 18)
3784 #define   MAD_DIMM_A_DUAL_RANK		(0x1 << 17)
3785 #define   MAD_DIMM_A_SELECT		(0x1 << 16)
3788 #define   MAD_DIMM_B_SIZE_MASK		(0xff << MAD_DIMM_B_SIZE_SHIFT)
3789 #define   MAD_DIMM_A_SIZE_SHIFT		0
3790 #define   MAD_DIMM_A_SIZE_MASK		(0xff << MAD_DIMM_A_SIZE_SHIFT)
3793 #define MCH_SSKPD			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3794 #define   MCH_SSKPD_WM0_MASK		0x3f
3795 #define   MCH_SSKPD_WM0_VAL		0xc
3798 #define CLKCFG			_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3799 #define CLKCFG_FSB_400					(0 << 0)	/* hrawclk 100 */
3800 #define CLKCFG_FSB_400_ALT				(5 << 0)	/* hrawclk 100 */
3801 #define CLKCFG_FSB_533					(1 << 0)	/* hrawclk 133 */
3802 #define CLKCFG_FSB_667					(3 << 0)	/* hrawclk 166 */
3803 #define CLKCFG_FSB_800					(2 << 0)	/* hrawclk 200 */
3804 #define CLKCFG_FSB_1067					(6 << 0)	/* hrawclk 266 */
3805 #define CLKCFG_FSB_1067_ALT				(0 << 0)	/* hrawclk 266 */
3806 #define CLKCFG_FSB_1333					(7 << 0)	/* hrawclk 333 */
3807 #define CLKCFG_FSB_1333_ALT				(4 << 0)	/* hrawclk 333 */
3808 #define CLKCFG_FSB_1600_ALT				(6 << 0)	/* hrawclk 400 */
3809 #define CLKCFG_FSB_MASK					(7 << 0)
3815 #define HPLLVCO                 _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3816 #define HPLLVCO_MOBILE          _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3818 #define TSC1			_MMIO(0x11001)
3819 #define   TSE			(1 << 0)
3820 #define TR1			_MMIO(0x11006)
3821 #define TSFS			_MMIO(0x11020)
3822 #define   TSFS_SLOPE_MASK	0x0000ff00
3824 #define   TSFS_INTR_MASK	0x000000ff
3826 #define CRSTANDVID		_MMIO(0x11100)
3827 #define PXVFREQ(fstart)		_MMIO(0x11110 + (fstart) * 4)  /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3828 #define   PXVFREQ_PX_MASK	0x7f000000
3830 #define VIDFREQ_BASE		_MMIO(0x11110)
3831 #define VIDFREQ1		_MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3832 #define VIDFREQ2		_MMIO(0x11114)
3833 #define VIDFREQ3		_MMIO(0x11118)
3834 #define VIDFREQ4		_MMIO(0x1111c)
3835 #define   VIDFREQ_P0_MASK	0x1f000000
3837 #define   VIDFREQ_P0_CSCLK_MASK	0x00f00000
3839 #define   VIDFREQ_P0_CRCLK_MASK	0x000f0000
3841 #define   VIDFREQ_P1_MASK	0x00001f00
3843 #define   VIDFREQ_P1_CSCLK_MASK	0x000000f0
3845 #define   VIDFREQ_P1_CRCLK_MASK	0x0000000f
3846 #define INTTOEXT_BASE_ILK	_MMIO(0x11300)
3847 #define INTTOEXT_BASE		_MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3849 #define   INTTOEXT_MAP3_MASK	(0x1f << INTTOEXT_MAP3_SHIFT)
3851 #define   INTTOEXT_MAP2_MASK	(0x1f << INTTOEXT_MAP2_SHIFT)
3853 #define   INTTOEXT_MAP1_MASK	(0x1f << INTTOEXT_MAP1_SHIFT)
3854 #define   INTTOEXT_MAP0_SHIFT	0
3855 #define   INTTOEXT_MAP0_MASK	(0x1f << INTTOEXT_MAP0_SHIFT)
3856 #define MEMSWCTL		_MMIO(0x11170) /* Ironlake only */
3857 #define   MEMCTL_CMD_MASK	0xe000
3859 #define   MEMCTL_CMD_RCLK_OFF	0
3867 #define   MEMCTL_FREQ_MASK	0x0f00 /* jitter, from 0-15 */
3870 #define   MEMCTL_TGT_VID_MASK	0x007f
3871 #define MEMIHYST		_MMIO(0x1117c)
3872 #define MEMINTREN		_MMIO(0x11180) /* 16 bits */
3881 #define   MEMINT_SW_CMD_EN	(1 << 0)
3882 #define MEMINTRSTR		_MMIO(0x11182) /* 16 bits */
3883 #define   MEM_RSEXIT_MASK	0xc000
3885 #define   MEM_CONT_BUSY_MASK	0x3000
3887 #define   MEM_AVG_BUSY_MASK	0x0c00
3889 #define   MEM_EVAL_CHG_MASK	0x0300
3891 #define   MEM_MON_IDLE_MASK	0x00c0
3893 #define   MEM_UP_EVAL_MASK	0x0030
3895 #define   MEM_DOWN_EVAL_MASK	0x000c
3897 #define   MEM_SW_CMD_MASK	0x0003
3898 #define   MEM_INT_STEER_GFX	0
3902 #define MEMINTRSTS		_MMIO(0x11184)
3910 #define   MEMINT_SW_CMD		(1 << 0)
3911 #define MEMMODECTL		_MMIO(0x11190)
3913 #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3915 #define   MEMMODE_IDLE_MODE_MASK 0x00030000
3917 #define   MEMMODE_IDLE_MODE_EVAL 0
3923 #define   MEMMODE_FSTART_MASK	0x00000f00 /* starting jitter, 0-15 */
3925 #define   MEMMODE_FMAX_MASK	0x000000f0 /* max jitter, 0-15 */
3927 #define   MEMMODE_FMIN_MASK	0x0000000f /* min jitter, 0-15 */
3928 #define RCBMAXAVG		_MMIO(0x1119c)
3929 #define MEMSWCTL2		_MMIO(0x1119e) /* Cantiga only */
3930 #define   SWMEMCMD_RENDER_OFF	(0 << 13)
3938 #define   SWFREQ_MASK		0x0380 /* P0-7 */
3940 #define   TARVID_MASK		0x001f
3941 #define MEMSTAT_CTG		_MMIO(0x111a0)
3942 #define RCBMINAVG		_MMIO(0x111a0)
3943 #define RCUPEI			_MMIO(0x111b0)
3944 #define RCDNEI			_MMIO(0x111b4)
3945 #define RSTDBYCTL		_MMIO(0x111b8)
3956 #define   RSX_STATUS_ON		(0 << 20)
3969 #define   RS1CONTSAV_NO_RS1	(0 << 14) /* rs1 doesn't save/restore context */
3974 #define   SLOW_RS123		(0 << 12)
3978 #define   RCMODE_TIMEOUT	(1 << 11) /* 0 is eval interval method */
3981 #define   STATELOCK		(1 << 7) /* locked to rs_cstate if 0 */
3983 #define   RS_CSTATE_C367_RS1	(0 << 4)
3989 #define VIDCTL			_MMIO(0x111c0)
3990 #define VIDSTS			_MMIO(0x111c8)
3991 #define VIDSTART		_MMIO(0x111cc) /* 8 bits */
3992 #define MEMSTAT_ILK		_MMIO(0x111f8)
3993 #define   MEMSTAT_VID_MASK	0x7f00
3995 #define   MEMSTAT_PSTATE_MASK	0x00f8
3998 #define   MEMSTAT_SRC_CTL_MASK	0x0003
3999 #define   MEMSTAT_SRC_CTL_CORE	0
4003 #define RCPREVBSYTUPAVG		_MMIO(0x113b8)
4004 #define RCPREVBSYTDNAVG		_MMIO(0x113bc)
4005 #define PMMISC			_MMIO(0x11214)
4006 #define   MCPPCE_EN		(1 << 0) /* enable PM_MSG from PCH->MPC */
4007 #define SDEW			_MMIO(0x1124c)
4008 #define CSIEW0			_MMIO(0x11250)
4009 #define CSIEW1			_MMIO(0x11254)
4010 #define CSIEW2			_MMIO(0x11258)
4011 #define PEW(i)			_MMIO(0x1125c + (i) * 4) /* 5 registers */
4012 #define DEW(i)			_MMIO(0x11270 + (i) * 4) /* 3 registers */
4013 #define MCHAFE			_MMIO(0x112c0)
4014 #define CSIEC			_MMIO(0x112e0)
4015 #define DMIEC			_MMIO(0x112e4)
4016 #define DDREC			_MMIO(0x112e8)
4017 #define PEG0EC			_MMIO(0x112ec)
4018 #define PEG1EC			_MMIO(0x112f0)
4019 #define GFXEC			_MMIO(0x112f4)
4020 #define RPPREVBSYTUPAVG		_MMIO(0x113b8)
4021 #define RPPREVBSYTDNAVG		_MMIO(0x113bc)
4022 #define ECR			_MMIO(0x11600)
4025 #define   ECR_CAP_MASK		0x0000001f /* Event range, 0-31 */
4026 #define OGW0			_MMIO(0x11608)
4027 #define OGW1			_MMIO(0x1160c)
4028 #define EG0			_MMIO(0x11610)
4029 #define EG1			_MMIO(0x11614)
4030 #define EG2			_MMIO(0x11618)
4031 #define EG3			_MMIO(0x1161c)
4032 #define EG4			_MMIO(0x11620)
4033 #define EG5			_MMIO(0x11624)
4034 #define EG6			_MMIO(0x11628)
4035 #define EG7			_MMIO(0x1162c)
4036 #define PXW(i)			_MMIO(0x11664 + (i) * 4) /* 4 registers */
4037 #define PXWL(i)			_MMIO(0x11680 + (i) * 8) /* 8 registers */
4038 #define LCFUSE02		_MMIO(0x116c0)
4039 #define   LCFUSE_HIV_MASK	0x000000ff
4040 #define CSIPLL0			_MMIO(0x12c10)
4041 #define DDRMPLL1		_MMIO(0X12c20)
4042 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
4044 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
4045 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
4047 #define GEN6_GT_PERF_STATUS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
4048 #define BXT_GT_PERF_STATUS      _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
4049 #define GEN6_RP_STATE_LIMITS	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
4050 #define GEN6_RP_STATE_CAP	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
4051 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
4052 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
4057 #define CCID(base)			_MMIO((base) + 0x180)
4058 #define   CCID_EN			BIT(0)
4074 #define CXT_SIZE		_MMIO(0x21a0)
4075 #define GEN6_CXT_POWER_SIZE(cxt_reg)	(((cxt_reg) >> 24) & 0x3f)
4076 #define GEN6_CXT_RING_SIZE(cxt_reg)	(((cxt_reg) >> 18) & 0x3f)
4077 #define GEN6_CXT_RENDER_SIZE(cxt_reg)	(((cxt_reg) >> 12) & 0x3f)
4078 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg)	(((cxt_reg) >> 6) & 0x3f)
4079 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg)	(((cxt_reg) >> 0) & 0x3f)
4083 #define GEN7_CXT_SIZE		_MMIO(0x21a8)
4084 #define GEN7_CXT_POWER_SIZE(ctx_reg)	(((ctx_reg) >> 25) & 0x7f)
4085 #define GEN7_CXT_RING_SIZE(ctx_reg)	(((ctx_reg) >> 22) & 0x7)
4086 #define GEN7_CXT_RENDER_SIZE(ctx_reg)	(((ctx_reg) >> 16) & 0x3f)
4087 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg)	(((ctx_reg) >> 9) & 0x7f)
4088 #define GEN7_CXT_GT1_SIZE(ctx_reg)	(((ctx_reg) >> 6) & 0x7)
4089 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)	(((ctx_reg) >> 0) & 0x3f)
4094 	INTEL_ADVANCED_CONTEXT = 0,
4101 	FAULT_AND_HANG = 0,
4107 #define GEN8_CTX_VALID (1 << 0)
4123 #define CHV_CLK_CTL1			_MMIO(0x101100)
4124 #define VLV_CLK_CTL2			_MMIO(0x101104)
4131 #define OVADD			_MMIO(0x30000)
4132 #define DOVSTA			_MMIO(0x30008)
4133 #define OC_BUF			(0x3 << 20)
4134 #define OGAMC5			_MMIO(0x30010)
4135 #define OGAMC4			_MMIO(0x30014)
4136 #define OGAMC3			_MMIO(0x30018)
4137 #define OGAMC2			_MMIO(0x3001c)
4138 #define OGAMC1			_MMIO(0x30020)
4139 #define OGAMC0			_MMIO(0x30024)
4144 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
4149 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
4152 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
4155 #define _CLKGATE_DIS_PSL_A		0x46520
4156 #define _CLKGATE_DIS_PSL_B		0x46524
4157 #define _CLKGATE_DIS_PSL_C		0x46528
4171 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
4178 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
4181 #define SUBSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x9528)
4184 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
4189 #define UNSLICE_UNIT_LEVEL_CLKGATE2	_MMIO(0x94e4)
4193 #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
4201 #define _PIPE_CRC_CTL_A			0x60050
4204 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	(0 << 28)
4213 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	(0 << 29)
4217 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	(0 << 28)
4224 #define   PIPE_CRC_SOURCE_PIPE_VLV	(0 << 27)
4232 #define   PIPE_CRC_SOURCE_PIPE_I9XX	(0 << 28)
4244 #define _PIPE_CRC_RES_1_A_IVB		0x60064
4245 #define _PIPE_CRC_RES_2_A_IVB		0x60068
4246 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
4247 #define _PIPE_CRC_RES_4_A_IVB		0x60070
4248 #define _PIPE_CRC_RES_5_A_IVB		0x60074
4250 #define _PIPE_CRC_RES_RED_A		0x60060
4251 #define _PIPE_CRC_RES_GREEN_A		0x60064
4252 #define _PIPE_CRC_RES_BLUE_A		0x60068
4253 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
4254 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
4257 #define _PIPE_CRC_RES_1_B_IVB		0x61064
4258 #define _PIPE_CRC_RES_2_B_IVB		0x61068
4259 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
4260 #define _PIPE_CRC_RES_4_B_IVB		0x61070
4261 #define _PIPE_CRC_RES_5_B_IVB		0x61074
4277 #define _HTOTAL_A	0x60000
4278 #define _HBLANK_A	0x60004
4279 #define _HSYNC_A	0x60008
4280 #define _VTOTAL_A	0x6000c
4281 #define _VBLANK_A	0x60010
4282 #define _VSYNC_A	0x60014
4283 #define _EXITLINE_A	0x60018
4284 #define _PIPEASRC	0x6001c
4285 #define _BCLRPAT_A	0x60020
4286 #define _VSYNCSHIFT_A	0x60028
4287 #define _PIPE_MULT_A	0x6002c
4290 #define _HTOTAL_B	0x61000
4291 #define _HBLANK_B	0x61004
4292 #define _HSYNC_B	0x61008
4293 #define _VTOTAL_B	0x6100c
4294 #define _VBLANK_B	0x61010
4295 #define _VSYNC_B	0x61014
4296 #define _PIPEBSRC	0x6101c
4297 #define _BCLRPAT_B	0x61020
4298 #define _VSYNCSHIFT_B	0x61028
4299 #define _PIPE_MULT_B	0x6102c
4301 /* DSI 0 timing regs */
4302 #define _HTOTAL_DSI0		0x6b000
4303 #define _HSYNC_DSI0		0x6b008
4304 #define _VTOTAL_DSI0		0x6b00c
4305 #define _VSYNC_DSI0		0x6b014
4306 #define _VSYNCSHIFT_DSI0	0x6b028
4309 #define _HTOTAL_DSI1		0x6b800
4310 #define _HSYNC_DSI1		0x6b808
4311 #define _VTOTAL_DSI1		0x6b80c
4312 #define _VSYNC_DSI1		0x6b814
4313 #define _VSYNCSHIFT_DSI1	0x6b828
4315 #define TRANSCODER_A_OFFSET 0x60000
4316 #define TRANSCODER_B_OFFSET 0x61000
4317 #define TRANSCODER_C_OFFSET 0x62000
4318 #define CHV_TRANSCODER_C_OFFSET 0x63000
4319 #define TRANSCODER_D_OFFSET 0x63000
4320 #define TRANSCODER_EDP_OFFSET 0x6f000
4321 #define TRANSCODER_DSI0_OFFSET	0x6b000
4322 #define TRANSCODER_DSI1_OFFSET	0x6b800
4337 #define   EXITLINE_MASK		REG_GENMASK(12, 0)
4338 #define   EXITLINE_SHIFT	0
4341 #define _TRANS_VRR_CTL_A		0x60420
4342 #define _TRANS_VRR_CTL_B		0x61420
4343 #define _TRANS_VRR_CTL_C		0x62420
4344 #define _TRANS_VRR_CTL_D		0x63420
4350 #define   VRR_CTL_SW_FULLLINE_COUNT	REG_BIT(0)
4352 #define _TRANS_VRR_VMAX_A		0x60424
4353 #define _TRANS_VRR_VMAX_B		0x61424
4354 #define _TRANS_VRR_VMAX_C		0x62424
4355 #define _TRANS_VRR_VMAX_D		0x63424
4357 #define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
4359 #define _TRANS_VRR_VMIN_A		0x60434
4360 #define _TRANS_VRR_VMIN_B		0x61434
4361 #define _TRANS_VRR_VMIN_C		0x62434
4362 #define _TRANS_VRR_VMIN_D		0x63434
4364 #define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
4366 #define _TRANS_VRR_VMAXSHIFT_A		0x60428
4367 #define _TRANS_VRR_VMAXSHIFT_B		0x61428
4368 #define _TRANS_VRR_VMAXSHIFT_C		0x62428
4369 #define _TRANS_VRR_VMAXSHIFT_D		0x63428
4374 #define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
4376 #define _TRANS_VRR_STATUS_A		0x6042C
4377 #define _TRANS_VRR_STATUS_B		0x6142C
4378 #define _TRANS_VRR_STATUS_C		0x6242C
4379 #define _TRANS_VRR_STATUS_D		0x6342C
4388 #define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4396 #define _TRANS_VRR_VTOTAL_PREV_A	0x60480
4397 #define _TRANS_VRR_VTOTAL_PREV_B	0x61480
4398 #define _TRANS_VRR_VTOTAL_PREV_C	0x62480
4399 #define _TRANS_VRR_VTOTAL_PREV_D	0x63480
4405 #define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
4407 #define _TRANS_VRR_FLIPLINE_A		0x60438
4408 #define _TRANS_VRR_FLIPLINE_B		0x61438
4409 #define _TRANS_VRR_FLIPLINE_C		0x62438
4410 #define _TRANS_VRR_FLIPLINE_D		0x63438
4413 #define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
4415 #define _TRANS_VRR_STATUS2_A		0x6043C
4416 #define _TRANS_VRR_STATUS2_B		0x6143C
4417 #define _TRANS_VRR_STATUS2_C		0x6243C
4418 #define _TRANS_VRR_STATUS2_D		0x6343C
4420 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
4422 #define _TRANS_PUSH_A			0x60A70
4423 #define _TRANS_PUSH_B			0x61A70
4424 #define _TRANS_PUSH_C			0x62A70
4425 #define _TRANS_PUSH_D			0x63A70
4433  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
4436 #define _HSW_EDP_PSR_BASE			0x64800
4437 #define _SRD_CTL_A				0x60800
4438 #define _SRD_CTL_EDP				0x6f800
4446 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES	(0 << 25)
4452 #define   EDP_PSR_TP1_TP2_SEL			(0 << 11)
4455 #define   EDP_PSR_TP2_TP3_TIME_500us		(0 << 8)
4460 #define   EDP_PSR_TP1_TIME_500us		(0 << 4)
4464 #define   EDP_PSR_IDLE_FRAME_SHIFT		0
4467  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
4471 #define EDP_PSR_IMR				_MMIO(0x64834)
4472 #define EDP_PSR_IIR				_MMIO(0x64838)
4473 #define _PSR_IMR_A				0x60814
4474 #define _PSR_IIR_A				0x60818
4478 						 0 : ((trans) - TRANSCODER_A + 1) * 8)
4479 #define   EDP_PSR_TRANS_MASK(trans)		(0x7 << _EDP_PSR_TRANS_SHIFT(trans))
4480 #define   EDP_PSR_ERROR(trans)			(0x4 << _EDP_PSR_TRANS_SHIFT(trans))
4481 #define   EDP_PSR_POST_EXIT(trans)		(0x2 << _EDP_PSR_TRANS_SHIFT(trans))
4482 #define   EDP_PSR_PRE_ENTRY(trans)		(0x1 << _EDP_PSR_TRANS_SHIFT(trans))
4484 #define _SRD_AUX_CTL_A				0x60810
4485 #define _SRD_AUX_CTL_EDP			0x6f810
4488 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK	(0x1f << 20)
4489 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK	(0xf << 16)
4491 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK	(0x7ff)
4493 #define _SRD_AUX_DATA_A				0x60814
4494 #define _SRD_AUX_DATA_EDP			0x6f814
4497 #define _SRD_STATUS_A				0x60840
4498 #define _SRD_STATUS_EDP				0x6f840
4502 #define   EDP_PSR_STATUS_STATE_IDLE		(0 << 29)
4510 #define   EDP_PSR_STATUS_LINK_FULL_OFF		(0 << 26)
4514 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK	0x1f
4516 #define   EDP_PSR_STATUS_COUNT_MASK		0xf
4522 #define   EDP_PSR_STATUS_IDLE_MASK		0xf
4524 #define _SRD_PERF_CNT_A			0x60844
4525 #define _SRD_PERF_CNT_EDP		0x6f844
4527 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
4530 #define _SRD_DEBUG_A				0x60860
4531 #define _SRD_DEBUG_EDP				0x6f860
4540 #define _PSR2_CTL_A				0x60900
4541 #define _PSR2_CTL_EDP				0x6f900
4545 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)
4550 #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
4563 #define   EDP_PSR2_TP2_TIME_500us		(0 << 8)
4569 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK		(0xf << 4)
4571 #define   EDP_PSR2_IDLE_FRAME_MASK		0xf
4572 #define   EDP_PSR2_IDLE_FRAME_SHIFT		0
4574 #define _PSR_EVENT_TRANS_A			0x60848
4575 #define _PSR_EVENT_TRANS_B			0x61848
4576 #define _PSR_EVENT_TRANS_C			0x62848
4577 #define _PSR_EVENT_TRANS_D			0x63848
4578 #define _PSR_EVENT_TRANS_EDP			0x6f848
4595 #define  PSR_EVENT_PSR_DISABLE			(1 << 0)
4597 #define _PSR2_STATUS_A			0x60940
4598 #define _PSR2_STATUS_EDP		0x6f940
4600 #define EDP_PSR2_STATUS_STATE_MASK     (0xf << 28)
4603 #define _PSR2_SU_STATUS_A		0x60914
4604 #define _PSR2_SU_STATUS_EDP		0x6f914
4608 #define PSR2_SU_STATUS_MASK(frame)	(0x3ff << PSR2_SU_STATUS_SHIFT(frame))
4611 #define _PSR2_MAN_TRK_CTL_A				0x60910
4612 #define _PSR2_MAN_TRK_CTL_EDP				0x6f910
4624 #define ADPA			_MMIO(0x61100)
4625 #define PCH_ADPA                _MMIO(0xe1100)
4626 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
4629 #define   ADPA_DAC_DISABLE	0
4636 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
4637 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
4642 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
4644 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
4646 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
4648 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
4652 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
4656 #define   ADPA_SETS_HVPOLARITY	0
4658 #define   ADPA_VSYNC_CNTL_ENABLE 0
4660 #define   ADPA_HSYNC_CNTL_ENABLE 0
4662 #define   ADPA_VSYNC_ACTIVE_LOW	0
4664 #define   ADPA_HSYNC_ACTIVE_LOW	0
4666 #define   ADPA_DPMS_ON		(0 << 10)
4673 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
4688 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
4691 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
4693 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
4698 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
4700 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
4703 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
4734 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
4769 #define _GEN3_SDVOB	0x61140
4770 #define _GEN3_SDVOC	0x61160
4775 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
4776 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
4777 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
4778 #define PCH_SDVOB	_MMIO(0xe1140)
4780 #define PCH_HDMIC	_MMIO(0xe1150)
4781 #define PCH_HDMID	_MMIO(0xe1160)
4783 #define PORT_DFT_I9XX				_MMIO(0x61150)
4785 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
4787 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
4790 #define   PIPE_A_SCRAMBLE_RESET			(1 << 0)
4819 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
4821 #define   SDVO_ENCODING_SDVO			(0 << 10)
4824 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
4847 #define _DVOA			0x61120
4849 #define _DVOB			0x61140
4851 #define _DVOC			0x61160
4857 #define   DVO_PIPE_STALL_UNUSED		(0 << 28)
4862 #define   DVO_DATA_ORDER_I740		(0 << 14)
4870 #define   DVO_DATA_ORDER_RGGB		(0 << 6)
4871 #define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
4877 #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
4878 #define   DVO_PRESERVE_MASK		(0x7 << 24)
4879 #define DVOA_SRCDIM		_MMIO(0x61124)
4880 #define DVOB_SRCDIM		_MMIO(0x61144)
4881 #define DVOC_SRCDIM		_MMIO(0x61164)
4883 #define   DVO_SRCDIM_VERTICAL_SHIFT	0
4886 #define LVDS			_MMIO(0x61180)
4912 #define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
4920 #define   LVDS_A3_POWER_DOWN		(0 << 6)
4927 #define   LVDS_CLKB_POWER_DOWN		(0 << 4)
4935 #define   LVDS_B0B3_POWER_DOWN		(0 << 2)
4939 #define VIDEO_DIP_DATA		_MMIO(0x61178)
4947 #define VIDEO_DIP_CTL		_MMIO(0x61170)
4957 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
4962 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
4969 #define   VSC_SELECT_MASK		(0x3 << 25)
4971 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
4981 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
4984 #define PPS_BASE			0x61200
4986 #define PCH_PPS_BASE			0xC7200
4990 					      (pps_idx) * 0x100)
4992 #define _PP_STATUS			0x61200
5004 #define   PP_SEQUENCE_NONE		REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
5008 #define   PP_SEQUENCE_STATE_MASK	REG_GENMASK(3, 0)
5009 #define   PP_SEQUENCE_STATE_OFF_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
5010 #define   PP_SEQUENCE_STATE_OFF_S0_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
5011 #define   PP_SEQUENCE_STATE_OFF_S0_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
5012 #define   PP_SEQUENCE_STATE_OFF_S0_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
5013 #define   PP_SEQUENCE_STATE_ON_IDLE	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
5014 #define   PP_SEQUENCE_STATE_ON_S1_1	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
5015 #define   PP_SEQUENCE_STATE_ON_S1_2	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa)
5016 #define   PP_SEQUENCE_STATE_ON_S1_3	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb)
5017 #define   PP_SEQUENCE_STATE_RESET	REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf)
5019 #define _PP_CONTROL			0x61204
5022 #define  PANEL_UNLOCK_REGS		REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd)
5027 #define  PANEL_POWER_ON			REG_BIT(0)
5029 #define _PP_ON_DELAYS			0x61208
5032 #define  PANEL_PORT_SELECT_LVDS		REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0)
5038 #define  PANEL_LIGHT_ON_DELAY_MASK	REG_GENMASK(12, 0)
5040 #define _PP_OFF_DELAYS			0x6120C
5043 #define  PANEL_LIGHT_OFF_DELAY_MASK	REG_GENMASK(12, 0)
5045 #define _PP_DIVISOR			0x61210
5048 #define  PANEL_POWER_CYCLE_DELAY_MASK	REG_GENMASK(4, 0)
5051 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
5056 #define   VERT_INTERP_DISABLE	(0 << 10)
5060 #define   HORIZ_INTERP_DISABLE	(0 << 6)
5065 #define   PFIT_FILTER_FUZZY	(0 << 24)
5066 #define   PFIT_SCALING_AUTO	(0 << 26)
5070 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
5073 #define		PFIT_VERT_SCALE_MASK		0xfff00000
5075 #define		PFIT_HORIZ_SCALE_MASK		0x0000fff0
5078 #define		PFIT_VERT_SCALE_MASK_965	0x1fff0000
5079 #define		PFIT_HORIZ_SCALE_SHIFT_965	0
5080 #define		PFIT_HORIZ_SCALE_MASK_965	0x00001fff
5082 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
5084 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250)
5085 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350)
5089 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5090 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354)
5094 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5095 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360)
5100 #define BLC_PWM_CTL2	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
5105 #define   BLM_PIPE_A			(0 << 29)
5118 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
5120 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
5121 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
5122 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
5123 #define BLC_PWM_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
5131 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
5140 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
5141 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
5142 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
5143 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
5145 #define BLC_HIST_CTL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
5150 #define BLC_PWM_CPU_CTL2	_MMIO(0x48250)
5151 #define BLC_PWM_CPU_CTL		_MMIO(0x48254)
5153 #define HSW_BLC_PWM2_CTL	_MMIO(0x48350)
5157 #define BLC_PWM_PCH_CTL1	_MMIO(0xc8250)
5161 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
5163 #define UTIL_PIN_CTL			_MMIO(0x48400)
5167 #define   UTIL_PIN_MODE_MASK		(0xf << 24)
5168 #define   UTIL_PIN_MODE_DATA		(0 << 24)
5179 #define _BXT_BLC_PWM_CTL1			0xC8250
5182 #define _BXT_BLC_PWM_FREQ1			0xC8254
5183 #define _BXT_BLC_PWM_DUTY1			0xC8258
5185 #define _BXT_BLC_PWM_CTL2			0xC8350
5186 #define _BXT_BLC_PWM_FREQ2			0xC8354
5187 #define _BXT_BLC_PWM_DUTY2			0xC8358
5196 #define PCH_GTC_CTL		_MMIO(0xe7000)
5200 #define TV_CTL			_MMIO(0x68000)
5208 # define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
5219 # define TV_OVERSAMPLE_4X		(0 << 18)
5242 # define TV_CTL_SAVE			((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
5245 # define TV_FUSE_STATE_ENABLED		(0 << 4)
5251 # define TV_TEST_MODE_NORMAL		(0 << 0)
5253 # define TV_TEST_MODE_PATTERN_1		(1 << 0)
5255 # define TV_TEST_MODE_PATTERN_2		(2 << 0)
5257 # define TV_TEST_MODE_PATTERN_3		(3 << 0)
5259 # define TV_TEST_MODE_PATTERN_4		(4 << 0)
5261 # define TV_TEST_MODE_PATTERN_5		(5 << 0)
5267 # define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
5268 # define TV_TEST_MODE_MASK		(7 << 0)
5270 #define TV_DAC			_MMIO(0x68004)
5271 # define TV_DAC_SAVE		0x00ffff00
5302 # define DAC_A_1_3_V			(0 << 4)
5306 # define DAC_B_1_3_V			(0 << 2)
5310 # define DAC_C_1_3_V			(0 << 0)
5311 # define DAC_C_1_1_V			(1 << 0)
5312 # define DAC_C_0_7_V			(2 << 0)
5313 # define DAC_C_MASK			(3 << 0)
5319  * -1 (0x3) being the only legal negative value.
5321 #define TV_CSC_Y		_MMIO(0x68010)
5322 # define TV_RY_MASK			0x07ff0000
5324 # define TV_GY_MASK			0x00000fff
5325 # define TV_GY_SHIFT			0
5327 #define TV_CSC_Y2		_MMIO(0x68014)
5328 # define TV_BY_MASK			0x07ff0000
5335 # define TV_AY_MASK			0x000003ff
5336 # define TV_AY_SHIFT			0
5338 #define TV_CSC_U		_MMIO(0x68018)
5339 # define TV_RU_MASK			0x07ff0000
5341 # define TV_GU_MASK			0x000007ff
5342 # define TV_GU_SHIFT			0
5344 #define TV_CSC_U2		_MMIO(0x6801c)
5345 # define TV_BU_MASK			0x07ff0000
5352 # define TV_AU_MASK			0x000003ff
5353 # define TV_AU_SHIFT			0
5355 #define TV_CSC_V		_MMIO(0x68020)
5356 # define TV_RV_MASK			0x0fff0000
5358 # define TV_GV_MASK			0x000007ff
5359 # define TV_GV_SHIFT			0
5361 #define TV_CSC_V2		_MMIO(0x68024)
5362 # define TV_BV_MASK			0x07ff0000
5369 # define TV_AV_MASK			0x000007ff
5370 # define TV_AV_SHIFT			0
5372 #define TV_CLR_KNOBS		_MMIO(0x68028)
5374 # define TV_BRIGHTNESS_MASK		0xff000000
5377 # define TV_CONTRAST_MASK		0x00ff0000
5380 # define TV_SATURATION_MASK		0x0000ff00
5383 # define TV_HUE_MASK			0x000000ff
5384 # define TV_HUE_SHIFT			0
5386 #define TV_CLR_LEVEL		_MMIO(0x6802c)
5388 # define TV_BLACK_LEVEL_MASK		0x01ff0000
5391 # define TV_BLANK_LEVEL_MASK		0x000001ff
5392 # define TV_BLANK_LEVEL_SHIFT		0
5394 #define TV_H_CTL_1		_MMIO(0x68030)
5396 # define TV_HSYNC_END_MASK		0x1fff0000
5399 # define TV_HTOTAL_MASK			0x00001fff
5400 # define TV_HTOTAL_SHIFT		0
5402 #define TV_H_CTL_2		_MMIO(0x68034)
5407 # define TV_HBURST_START_MASK		0x1fff0000
5409 # define TV_HBURST_LEN_SHIFT		0
5410 # define TV_HBURST_LEN_MASK		0x0001fff
5412 #define TV_H_CTL_3		_MMIO(0x68038)
5415 # define TV_HBLANK_END_MASK		0x1fff0000
5417 # define TV_HBLANK_START_SHIFT		0
5418 # define TV_HBLANK_START_MASK		0x0001fff
5420 #define TV_V_CTL_1		_MMIO(0x6803c)
5423 # define TV_NBR_END_MASK		0x07ff0000
5426 # define TV_VI_END_F1_MASK		0x00003f00
5428 # define TV_VI_END_F2_SHIFT		0
5429 # define TV_VI_END_F2_MASK		0x0000003f
5431 #define TV_V_CTL_2		_MMIO(0x68040)
5433 # define TV_VSYNC_LEN_MASK		0x07ff0000
5438 # define TV_VSYNC_START_F1_MASK		0x00007f00
5444 # define TV_VSYNC_START_F2_MASK		0x0000007f
5445 # define TV_VSYNC_START_F2_SHIFT	0
5447 #define TV_V_CTL_3		_MMIO(0x68044)
5451 # define TV_VEQ_LEN_MASK		0x007f0000
5456 # define TV_VEQ_START_F1_MASK		0x0007f00
5462 # define TV_VEQ_START_F2_MASK		0x000007f
5463 # define TV_VEQ_START_F2_SHIFT		0
5465 #define TV_V_CTL_4		_MMIO(0x68048)
5470 # define TV_VBURST_START_F1_MASK	0x003f0000
5476 # define TV_VBURST_END_F1_MASK		0x000000ff
5477 # define TV_VBURST_END_F1_SHIFT		0
5479 #define TV_V_CTL_5		_MMIO(0x6804c)
5484 # define TV_VBURST_START_F2_MASK	0x003f0000
5490 # define TV_VBURST_END_F2_MASK		0x000000ff
5491 # define TV_VBURST_END_F2_SHIFT		0
5493 #define TV_V_CTL_6		_MMIO(0x68050)
5498 # define TV_VBURST_START_F3_MASK	0x003f0000
5504 # define TV_VBURST_END_F3_MASK		0x000000ff
5505 # define TV_VBURST_END_F3_SHIFT		0
5507 #define TV_V_CTL_7		_MMIO(0x68054)
5512 # define TV_VBURST_START_F4_MASK	0x003f0000
5518 # define TV_VBURST_END_F4_MASK		0x000000ff
5519 # define TV_VBURST_END_F4_SHIFT		0
5521 #define TV_SC_CTL_1		_MMIO(0x68060)
5529 # define TV_SC_RESET_EVERY_2		(0 << 24)
5537 # define TV_BURST_LEVEL_MASK		0x00ff0000
5540 # define TV_SCDDA1_INC_MASK		0x00000fff
5541 # define TV_SCDDA1_INC_SHIFT		0
5543 #define TV_SC_CTL_2		_MMIO(0x68064)
5545 # define TV_SCDDA2_SIZE_MASK		0x7fff0000
5548 # define TV_SCDDA2_INC_MASK		0x00007fff
5549 # define TV_SCDDA2_INC_SHIFT		0
5551 #define TV_SC_CTL_3		_MMIO(0x68068)
5553 # define TV_SCDDA3_SIZE_MASK		0x7fff0000
5556 # define TV_SCDDA3_INC_MASK		0x00007fff
5557 # define TV_SCDDA3_INC_SHIFT		0
5559 #define TV_WIN_POS		_MMIO(0x68070)
5561 # define TV_XPOS_MASK			0x1fff0000
5564 # define TV_YPOS_MASK			0x00000fff
5565 # define TV_YPOS_SHIFT			0
5567 #define TV_WIN_SIZE		_MMIO(0x68074)
5569 # define TV_XSIZE_MASK			0x1fff0000
5576 # define TV_YSIZE_MASK			0x00000fff
5577 # define TV_YSIZE_SHIFT			0
5579 #define TV_FILTER_CTL_1		_MMIO(0x68080)
5596 # define TV_VADAPT_MODE_LEAST		(0 << 26)
5609 # define TV_HSCALE_FRAC_MASK		0x00003fff
5610 # define TV_HSCALE_FRAC_SHIFT		0
5612 #define TV_FILTER_CTL_2		_MMIO(0x68084)
5618 # define TV_VSCALE_INT_MASK		0x00038000
5625 # define TV_VSCALE_FRAC_MASK		0x00007fff
5626 # define TV_VSCALE_FRAC_SHIFT		0
5628 #define TV_FILTER_CTL_3		_MMIO(0x68088)
5636 # define TV_VSCALE_IP_INT_MASK		0x00038000
5645 # define TV_VSCALE_IP_FRAC_MASK		0x00007fff
5646 # define TV_VSCALE_IP_FRAC_SHIFT		0
5648 #define TV_CC_CONTROL		_MMIO(0x68090)
5653  * CC data is usually sent in field 0.
5658 # define TV_CC_HOFF_MASK		0x03ff0000
5661 # define TV_CC_LINE_MASK		0x0000003f
5662 # define TV_CC_LINE_SHIFT		0
5664 #define TV_CC_DATA		_MMIO(0x68094)
5667 # define TV_CC_DATA_2_MASK		0x007f0000
5670 # define TV_CC_DATA_1_MASK		0x0000007f
5671 # define TV_CC_DATA_1_SHIFT		0
5673 #define TV_H_LUMA(i)		_MMIO(0x68100 + (i) * 4) /* 60 registers */
5674 #define TV_H_CHROMA(i)		_MMIO(0x68200 + (i) * 4) /* 60 registers */
5675 #define TV_V_LUMA(i)		_MMIO(0x68300 + (i) * 4) /* 43 registers */
5676 #define TV_V_CHROMA(i)		_MMIO(0x68400 + (i) * 4) /* 43 registers */
5679 #define DP_A			_MMIO(0x64000) /* eDP */
5680 #define DP_B			_MMIO(0x64100)
5681 #define DP_C			_MMIO(0x64200)
5682 #define DP_D			_MMIO(0x64300)
5684 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
5685 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
5686 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
5700 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
5708 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
5716 #define   DP_VOLTAGE_0_4		(0 << 25)
5726 #define   DP_PRE_EMPHASIS_0		(0 << 22)
5742 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
5776 #define _DPA_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
5777 #define _DPA_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
5779 #define _DPB_AUX_CH_CTL		(DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
5780 #define _DPB_AUX_CH_DATA1	(DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
5789 #define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
5795 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
5797 #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
5804 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
5805 #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
5810 #define   DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5827 #define _PIPEA_DATA_M_G4X	0x70050
5828 #define _PIPEB_DATA_M_G4X	0x71050
5830 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5833 #define  TU_SIZE_MASK           (0x3f << 25)
5835 #define  DATA_LINK_M_N_MASK	(0xffffff)
5836 #define  DATA_LINK_N_MAX	(0x800000)
5838 #define _PIPEA_DATA_N_G4X	0x70054
5839 #define _PIPEB_DATA_N_G4X	0x71054
5840 #define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
5853 #define _PIPEA_LINK_M_G4X	0x70060
5854 #define _PIPEB_LINK_M_G4X	0x71060
5855 #define   PIPEA_DP_LINK_M_MASK			(0xffffff)
5857 #define _PIPEA_LINK_N_G4X	0x70064
5858 #define _PIPEB_LINK_N_G4X	0x71064
5859 #define   PIPEA_DP_LINK_N_MASK			(0xffffff)
5869 #define _PIPEADSL		0x70000
5870 #define   DSL_LINEMASK_GEN2	0x00000fff
5871 #define   DSL_LINEMASK_GEN3	0x00001fff
5872 #define _PIPEACONF		0x70008
5874 #define   PIPECONF_DISABLE	0
5879 #define   PIPECONF_FRAME_START_DELAY(x)		((x) << 27) /* pre-hsw: 0-3 */
5880 #define   PIPECONF_SINGLE_WIDE	0
5881 #define   PIPECONF_PIPE_UNLOCKED 0
5886 #define   PIPECONF_GAMMA_MODE_8BIT	(0 << 24) /* gmch,ilk-ivb */
5896 #define   PIPECONF_PROGRESSIVE			(0 << 21)
5914 #define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
5918 #define   PIPECONF_BPC_MASK	(0x7 << 5)
5919 #define   PIPECONF_8BPC		(0 << 5)
5924 #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5925 #define   PIPECONF_DITHER_TYPE_SP (0 << 2)
5929 #define _PIPEASTAT		0x70024
5974 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
5975 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
5977 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
5978 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
5980 #define PIPE_A_OFFSET		0x70000
5981 #define PIPE_B_OFFSET		0x71000
5982 #define PIPE_C_OFFSET		0x72000
5983 #define PIPE_D_OFFSET		0x73000
5984 #define CHV_PIPE_C_OFFSET	0x74000
5991 #define PIPE_EDP_OFFSET	0x7f000
5993 /* ICL DSI 0 and 1 */
5994 #define PIPE_DSI0_OFFSET	0x7b000
5995 #define PIPE_DSI1_OFFSET	0x7b800
6003 #define  _PIPEAGCMAX           0x70010
6004 #define  _PIPEBGCMAX           0x71010
6007 #define _PIPE_MISC_A			0x70030
6008 #define _PIPE_MISC_B			0x71030
6015 #define   PIPEMISC_DITHER_8_BPC		(0 << 5)
6021 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
6025 #define _SKL_BOTTOM_COLOR_A		0x70034
6030 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
6051 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
6064 #define   DPINVGTT_EN_MASK			0xff0000
6065 #define   DPINVGTT_EN_MASK_CHV			0xfff0000
6077 #define   PLANEA_INVALID_GTT_STATUS		(1 << 0)
6078 #define   DPINVGTT_STATUS_MASK			0xff
6079 #define   DPINVGTT_STATUS_MASK_CHV		0xfff
6081 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
6082 #define   DSPARB_CSTART_MASK	(0x7f << 7)
6084 #define   DSPARB_BSTART_MASK	(0x7f)
6085 #define   DSPARB_BSTART_SHIFT	0
6087 #define   DSPARB_AEND_SHIFT	0
6088 #define   DSPARB_SPRITEA_SHIFT_VLV	0
6089 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
6091 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
6093 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
6095 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
6096 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
6097 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
6098 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
6100 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
6102 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
6104 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
6106 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
6108 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
6109 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
6110 #define   DSPARB_SPRITEE_SHIFT_VLV	0
6111 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
6113 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
6116 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
6118 #define   DSPFW_SR_MASK			(0x1ff << 23)
6120 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
6122 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
6123 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
6124 #define   DSPFW_PLANEA_SHIFT		0
6125 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
6126 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
6127 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
6130 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
6132 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
6134 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
6135 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
6137 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
6138 #define   DSPFW_PLANEC_OLD_SHIFT	0
6139 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
6140 #define   DSPFW_SPRITEA_SHIFT		0
6141 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
6142 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
6143 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
6147 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
6149 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
6150 #define   DSPFW_HPLL_SR_SHIFT		0
6151 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
6154 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
6156 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
6158 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
6159 #define   DSPFW_SPRITEA_WM1_SHIFT	0
6160 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
6161 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
6163 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
6165 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
6167 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
6168 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
6169 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
6170 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
6171 #define   DSPFW_SR_WM1_SHIFT		0
6172 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
6173 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
6174 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
6176 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
6178 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
6180 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
6181 #define   DSPFW_SPRITEC_SHIFT		0
6182 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
6183 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
6185 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
6187 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
6189 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
6190 #define   DSPFW_SPRITEE_SHIFT		0
6191 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
6192 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
6194 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
6196 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
6198 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
6199 #define   DSPFW_CURSORC_SHIFT		0
6200 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
6203 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
6222 #define   DSPFW_PLANEA_HI_SHIFT		0
6223 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
6224 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
6243 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
6244 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
6247 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
6250 #define DDL_PLANE_SHIFT			0
6252 #define DDL_PRECISION_LOW		(0 << 7)
6253 #define DRAIN_LATENCY_MASK		0x7f
6255 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
6259 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
6275 #define VALLEYVIEW_MAX_WM	0xff
6276 #define G4X_MAX_WM		0x3f
6277 #define I915_MAX_WM		0x3f
6281 #define PINEVIEW_MAX_WM		0x1ff
6282 #define PINEVIEW_DFT_WM		0x3f
6283 #define PINEVIEW_DFT_HPLLOFF_WM	0
6286 #define PINEVIEW_CURSOR_MAX_WM	0x3f
6287 #define PINEVIEW_CURSOR_DFT_WM	0
6296 #define _CUR_WM_A_0		0x70140
6297 #define _CUR_WM_B_0		0x71140
6298 #define _PLANE_WM_1_A_0		0x70240
6299 #define _PLANE_WM_1_B_0		0x71240
6300 #define _PLANE_WM_2_A_0		0x70340
6301 #define _PLANE_WM_2_B_0		0x71340
6302 #define _PLANE_WM_TRANS_1_A_0	0x70268
6303 #define _PLANE_WM_TRANS_1_B_0	0x71268
6304 #define _PLANE_WM_TRANS_2_A_0	0x70368
6305 #define _PLANE_WM_TRANS_2_B_0	0x71368
6306 #define _CUR_WM_TRANS_A_0	0x70168
6307 #define _CUR_WM_TRANS_B_0	0x71168
6311 #define   PLANE_WM_LINES_MASK	0x1f
6312 #define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */
6332 #define WM0_PIPEA_ILK		_MMIO(0x45100)
6333 #define  WM0_PIPE_PLANE_MASK	(0xffff << 16)
6335 #define  WM0_PIPE_SPRITE_MASK	(0xff << 8)
6337 #define  WM0_PIPE_CURSOR_MASK	(0xff)
6339 #define WM0_PIPEB_ILK		_MMIO(0x45104)
6340 #define WM0_PIPEC_IVB		_MMIO(0x45200)
6341 #define WM1_LP_ILK		_MMIO(0x45108)
6344 #define  WM1_LP_LATENCY_MASK	(0x7f << 24)
6345 #define  WM1_LP_FBC_MASK	(0xf << 20)
6348 #define  WM1_LP_SR_MASK		(0x7ff << 8)
6350 #define  WM1_LP_CURSOR_MASK	(0xff)
6351 #define WM2_LP_ILK		_MMIO(0x4510c)
6353 #define WM3_LP_ILK		_MMIO(0x45110)
6355 #define WM1S_LP_ILK		_MMIO(0x45120)
6356 #define WM2S_LP_IVB		_MMIO(0x45124)
6357 #define WM3S_LP_IVB		_MMIO(0x45128)
6365 #define MLTR_ILK		_MMIO(0x11222)
6366 #define  MLTR_WM1_SHIFT		0
6369 #define  ILK_SRLT_MASK		0x3f
6373 #define SSKPD			_MMIO(0x5d10)
6374 #define SSKPD_WM_MASK		0x3f
6375 #define SSKPD_WM0_SHIFT		0
6395 #define _PIPEAFRAMEHIGH          0x70040
6396 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
6397 #define   PIPE_FRAME_HIGH_SHIFT   0
6398 #define _PIPEAFRAMEPIXEL         0x70044
6399 #define   PIPE_FRAME_LOW_MASK     0xff000000
6401 #define   PIPE_PIXEL_MASK         0x00ffffff
6402 #define   PIPE_PIXEL_SHIFT        0
6404 #define _PIPEA_FRMCOUNT_G4X	0x70040
6405 #define _PIPEA_FLIPCOUNT_G4X	0x70044
6410 #define _CURACNTR		0x70080
6412 #define   CURSOR_ENABLE		0x80000000
6413 #define   CURSOR_GAMMA_ENABLE	0x40000000
6417 #define   CURSOR_FORMAT_MASK	(0x07 << CURSOR_FORMAT_SHIFT)
6418 #define   CURSOR_FORMAT_2C	(0x00 << CURSOR_FORMAT_SHIFT)
6419 #define   CURSOR_FORMAT_3C	(0x01 << CURSOR_FORMAT_SHIFT)
6420 #define   CURSOR_FORMAT_4C	(0x02 << CURSOR_FORMAT_SHIFT)
6421 #define   CURSOR_FORMAT_ARGB	(0x04 << CURSOR_FORMAT_SHIFT)
6422 #define   CURSOR_FORMAT_XRGB	(0x05 << CURSOR_FORMAT_SHIFT)
6424 #define   MCURSOR_MODE		0x27
6425 #define   MCURSOR_MODE_DISABLE   0x00
6426 #define   MCURSOR_MODE_128_32B_AX 0x02
6427 #define   MCURSOR_MODE_256_32B_AX 0x03
6428 #define   MCURSOR_MODE_64_32B_AX 0x07
6432 #define   MCURSOR_PIPE_SELECT_MASK	(0x3 << 28)
6439 #define _CURABASE		0x70084
6440 #define _CURAPOS		0x70088
6441 #define   CURSOR_POS_MASK       0x007FF
6442 #define   CURSOR_POS_SIGN       0x8000
6443 #define   CURSOR_X_SHIFT        0
6445 #define CURSIZE			_MMIO(0x700a0) /* 845/865 */
6446 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
6448 #define _CURASURFLIVE		0x700ac /* g4x+ */
6449 #define _CURBCNTR		0x700c0
6450 #define _CURBBASE		0x700c4
6451 #define _CURBPOS		0x700c8
6453 #define _CURBCNTR_IVB		0x71080
6454 #define _CURBBASE_IVB		0x71084
6455 #define _CURBPOS_IVB		0x71088
6463 #define CURSOR_A_OFFSET 0x70080
6464 #define CURSOR_B_OFFSET 0x700c0
6465 #define CHV_CURSOR_C_OFFSET 0x700e0
6466 #define IVB_CURSOR_B_OFFSET 0x71080
6467 #define IVB_CURSOR_C_OFFSET 0x72080
6468 #define TGL_CURSOR_D_OFFSET 0x73080
6471 #define _DSPACNTR				0x70180
6473 #define   DISPLAY_PLANE_DISABLE			0
6475 #define   DISPPLANE_GAMMA_DISABLE		0
6476 #define   DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
6477 #define   DISPPLANE_YUV422			(0x0 << 26)
6478 #define   DISPPLANE_8BPP			(0x2 << 26)
6479 #define   DISPPLANE_BGRA555			(0x3 << 26)
6480 #define   DISPPLANE_BGRX555			(0x4 << 26)
6481 #define   DISPPLANE_BGRX565			(0x5 << 26)
6482 #define   DISPPLANE_BGRX888			(0x6 << 26)
6483 #define   DISPPLANE_BGRA888			(0x7 << 26)
6484 #define   DISPPLANE_RGBX101010			(0x8 << 26)
6485 #define   DISPPLANE_RGBA101010			(0x9 << 26)
6486 #define   DISPPLANE_BGRX101010			(0xa << 26)
6487 #define   DISPPLANE_BGRA101010			(0xb << 26)
6488 #define   DISPPLANE_RGBX161616			(0xc << 26)
6489 #define   DISPPLANE_RGBX888			(0xe << 26)
6490 #define   DISPPLANE_RGBA888			(0xf << 26)
6492 #define   DISPPLANE_STEREO_DISABLE		0
6498 #define   DISPPLANE_SRC_KEY_DISABLE		0
6500 #define   DISPPLANE_NO_LINE_DOUBLE		0
6501 #define   DISPPLANE_STEREO_POLARITY_FIRST	0
6508 #define _DSPAADDR				0x70184
6509 #define _DSPASTRIDE				0x70188
6510 #define _DSPAPOS				0x7018C /* reserved */
6511 #define _DSPASIZE				0x70190
6512 #define _DSPASURF				0x7019C /* 965+ only */
6513 #define _DSPATILEOFF				0x701A4 /* 965+ only */
6514 #define _DSPAOFFSET				0x701A4 /* HSW */
6515 #define _DSPASURFLIVE				0x701AC
6516 #define _DSPAGAMC				0x701E0
6531 #define _CHV_BLEND_A		0x60a00
6532 #define   CHV_BLEND_LEGACY		(0 << 30)
6536 #define _CHV_CANVAS_A		0x60a04
6537 #define _PRIMPOS_A		0x60a08
6538 #define _PRIMSIZE_A		0x60a0c
6539 #define _PRIMCNSTALPHA_A	0x60a10
6549 #define DISP_BASEADDR_MASK	(0xfffff000)
6560  * [00:0f] all
6564 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
6565 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
6566 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
6567 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
6570 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
6571 #define _PIPEBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
6572 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
6573 #define _PIPEBFRAMEHIGH		0x71040
6574 #define _PIPEBFRAMEPIXEL	0x71044
6575 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
6576 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
6580 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
6582 #define   DISPPLANE_ALPHA_TRANS_DISABLE		0
6583 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
6585 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
6586 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
6587 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
6588 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
6589 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
6590 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6591 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
6592 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
6594 /* ICL DSI 0 and 1 */
6595 #define _PIPEDSI0CONF		0x7b008
6596 #define _PIPEDSI1CONF		0x7b808
6599 #define _DVSACNTR		0x72180
6604 #define   DVS_FORMAT_YUV422	(0 << 25)
6613 #define   DVS_YUV_ORDER_YUYV	(0 << 16)
6621 #define _DVSALINOFF		0x72184
6622 #define _DVSASTRIDE		0x72188
6623 #define _DVSAPOS		0x7218c
6624 #define _DVSASIZE		0x72190
6625 #define _DVSAKEYVAL		0x72194
6626 #define _DVSAKEYMSK		0x72198
6627 #define _DVSASURF		0x7219c
6628 #define _DVSAKEYMAXVAL		0x721a0
6629 #define _DVSATILEOFF		0x721a4
6630 #define _DVSASURFLIVE		0x721ac
6631 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
6632 #define _DVSASCALE		0x72204
6635 #define   DVS_FILTER_MEDIUM	(0 << 29)
6640 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
6641 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
6643 #define _DVSBCNTR		0x73180
6644 #define _DVSBLINOFF		0x73184
6645 #define _DVSBSTRIDE		0x73188
6646 #define _DVSBPOS		0x7318c
6647 #define _DVSBSIZE		0x73190
6648 #define _DVSBKEYVAL		0x73194
6649 #define _DVSBKEYMSK		0x73198
6650 #define _DVSBSURF		0x7319c
6651 #define _DVSBKEYMAXVAL		0x731a0
6652 #define _DVSBTILEOFF		0x731a4
6653 #define _DVSBSURFLIVE		0x731ac
6654 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
6655 #define _DVSBSCALE		0x73204
6656 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
6657 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
6675 #define _SPRA_CTL		0x70280
6680 #define   SPRITE_FORMAT_YUV422		(0 << 25)
6690 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	(1 << 18) /* 0 is BT601 */
6692 #define   SPRITE_YUV_ORDER_YUYV		(0 << 16)
6701 #define _SPRA_LINOFF		0x70284
6702 #define _SPRA_STRIDE		0x70288
6703 #define _SPRA_POS		0x7028c
6704 #define _SPRA_SIZE		0x70290
6705 #define _SPRA_KEYVAL		0x70294
6706 #define _SPRA_KEYMSK		0x70298
6707 #define _SPRA_SURF		0x7029c
6708 #define _SPRA_KEYMAX		0x702a0
6709 #define _SPRA_TILEOFF		0x702a4
6710 #define _SPRA_OFFSET		0x702a4
6711 #define _SPRA_SURFLIVE		0x702ac
6712 #define _SPRA_SCALE		0x70304
6715 #define   SPRITE_FILTER_MEDIUM	(0 << 29)
6720 #define _SPRA_GAMC		0x70400
6721 #define _SPRA_GAMC16		0x70440
6722 #define _SPRA_GAMC17		0x7044c
6724 #define _SPRB_CTL		0x71280
6725 #define _SPRB_LINOFF		0x71284
6726 #define _SPRB_STRIDE		0x71288
6727 #define _SPRB_POS		0x7128c
6728 #define _SPRB_SIZE		0x71290
6729 #define _SPRB_KEYVAL		0x71294
6730 #define _SPRB_KEYMSK		0x71298
6731 #define _SPRB_SURF		0x7129c
6732 #define _SPRB_KEYMAX		0x712a0
6733 #define _SPRB_TILEOFF		0x712a4
6734 #define _SPRB_OFFSET		0x712a4
6735 #define _SPRB_SURFLIVE		0x712ac
6736 #define _SPRB_SCALE		0x71304
6737 #define _SPRB_GAMC		0x71400
6738 #define _SPRB_GAMC16		0x71440
6739 #define _SPRB_GAMC17		0x7144c
6758 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
6761 #define   SP_PIXFORMAT_MASK		(0xf << 26)
6762 #define   SP_FORMAT_YUV422		(0x0 << 26)
6763 #define   SP_FORMAT_8BPP		(0x2 << 26)
6764 #define   SP_FORMAT_BGR565		(0x5 << 26)
6765 #define   SP_FORMAT_BGRX8888		(0x6 << 26)
6766 #define   SP_FORMAT_BGRA8888		(0x7 << 26)
6767 #define   SP_FORMAT_RGBX1010102		(0x8 << 26)
6768 #define   SP_FORMAT_RGBA1010102		(0x9 << 26)
6769 #define   SP_FORMAT_BGRX1010102		(0xa << 26) /* CHV pipe B */
6770 #define   SP_FORMAT_BGRA1010102		(0xb << 26) /* CHV pipe B */
6771 #define   SP_FORMAT_RGBX8888		(0xe << 26)
6772 #define   SP_FORMAT_RGBA8888		(0xf << 26)
6777 #define   SP_YUV_ORDER_YUYV		(0 << 16)
6784 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
6785 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
6786 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
6787 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
6788 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
6789 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
6790 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
6791 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
6792 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
6793 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
6795 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
6797 #define   SP_BRIGHTNESS(x)		((x) & 0xff) /* s8 */
6798 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
6799 #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
6801 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
6803 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
6804 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
6805 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
6806 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
6807 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
6808 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
6809 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
6810 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
6811 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
6812 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
6813 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
6814 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
6815 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
6816 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
6846 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6848 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
6849 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
6850 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
6851 #define  SPCSC_OOFF(x)		(((x) & 0x7ff) << 16) /* s11 */
6852 #define  SPCSC_IOFF(x)		(((x) & 0x7ff) << 0) /* s11 */
6854 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6855 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
6856 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
6857 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
6858 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6859 #define  SPCSC_C1(x)		(((x) & 0x7fff) << 16) /* s3.12 */
6860 #define  SPCSC_C0(x)		(((x) & 0x7fff) << 0) /* s3.12 */
6862 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
6863 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
6864 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
6865 #define  SPCSC_IMAX(x)		(((x) & 0x7ff) << 16) /* s11 */
6866 #define  SPCSC_IMIN(x)		(((x) & 0x7ff) << 0) /* s11 */
6868 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6869 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
6870 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
6872 #define  SPCSC_OMIN(x)		((x) << 0) /* u10 */
6876 #define _PLANE_CTL_1_A				0x70180
6877 #define _PLANE_CTL_2_A				0x70280
6878 #define _PLANE_CTL_3_A				0x70380
6885  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6887 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
6888 #define   PLANE_CTL_FORMAT_YUV422		(0 << 24)
6899 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
6906 #define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
6907 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
6910 #define   PLANE_CTL_ORDER_BGRX			(0 << 20)
6914 #define   PLANE_CTL_YUV422_ORDER_MASK		(0x3 << 16)
6915 #define   PLANE_CTL_YUV422_YUYV			(0 << 16)
6923 #define   PLANE_CTL_TILED_MASK			(0x7 << 10)
6924 #define   PLANE_CTL_TILED_LINEAR		(0 << 10)
6930 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
6931 #define   PLANE_CTL_ALPHA_DISABLE		(0 << 4)
6934 #define   PLANE_CTL_ROTATE_MASK			0x3
6935 #define   PLANE_CTL_ROTATE_0			0x0
6936 #define   PLANE_CTL_ROTATE_90			0x1
6937 #define   PLANE_CTL_ROTATE_180			0x2
6938 #define   PLANE_CTL_ROTATE_270			0x3
6939 #define _PLANE_STRIDE_1_A			0x70188
6940 #define _PLANE_STRIDE_2_A			0x70288
6941 #define _PLANE_STRIDE_3_A			0x70388
6942 #define _PLANE_POS_1_A				0x7018c
6943 #define _PLANE_POS_2_A				0x7028c
6944 #define _PLANE_POS_3_A				0x7038c
6945 #define _PLANE_SIZE_1_A				0x70190
6946 #define _PLANE_SIZE_2_A				0x70290
6947 #define _PLANE_SIZE_3_A				0x70390
6948 #define _PLANE_SURF_1_A				0x7019c
6949 #define _PLANE_SURF_2_A				0x7029c
6950 #define _PLANE_SURF_3_A				0x7039c
6951 #define _PLANE_OFFSET_1_A			0x701a4
6952 #define _PLANE_OFFSET_2_A			0x702a4
6953 #define _PLANE_OFFSET_3_A			0x703a4
6954 #define _PLANE_KEYVAL_1_A			0x70194
6955 #define _PLANE_KEYVAL_2_A			0x70294
6956 #define _PLANE_KEYMSK_1_A			0x70198
6957 #define _PLANE_KEYMSK_2_A			0x70298
6959 #define _PLANE_KEYMAX_1_A			0x701a0
6960 #define _PLANE_KEYMAX_2_A			0x702a0
6962 #define _PLANE_AUX_DIST_1_A			0x701c0
6963 #define _PLANE_AUX_DIST_2_A			0x702c0
6964 #define _PLANE_AUX_OFFSET_1_A			0x701c4
6965 #define _PLANE_AUX_OFFSET_2_A			0x702c4
6966 #define _PLANE_CUS_CTL_1_A			0x701c8
6967 #define _PLANE_CUS_CTL_2_A			0x702c8
6969 #define  PLANE_CUS_PLANE_4_RKL			(0 << 30)
6971 #define  PLANE_CUS_PLANE_6			(0 << 30)
6974 #define  PLANE_CUS_HPHASE_0			(0 << 16)
6978 #define  PLANE_CUS_VPHASE_0			(0 << 12)
6981 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
6982 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
6983 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
6988 #define   PLANE_COLOR_CSC_MODE_BYPASS			(0 << 17)
6994 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
6995 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
6998 #define _PLANE_BUF_CFG_1_A			0x7027c
6999 #define _PLANE_BUF_CFG_2_A			0x7037c
7000 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
7001 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
7004 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
7005 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
7007 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
7008 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
7021 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
7022 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
7024 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
7025 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
7037 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
7038 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
7040 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
7041 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
7053 #define _PLANE_CTL_1_B				0x71180
7054 #define _PLANE_CTL_2_B				0x71280
7055 #define _PLANE_CTL_3_B				0x71380
7062 #define _PLANE_STRIDE_1_B			0x71188
7063 #define _PLANE_STRIDE_2_B			0x71288
7064 #define _PLANE_STRIDE_3_B			0x71388
7074 #define _PLANE_POS_1_B				0x7118c
7075 #define _PLANE_POS_2_B				0x7128c
7076 #define _PLANE_POS_3_B				0x7138c
7083 #define _PLANE_SIZE_1_B				0x71190
7084 #define _PLANE_SIZE_2_B				0x71290
7085 #define _PLANE_SIZE_3_B				0x71390
7092 #define _PLANE_SURF_1_B				0x7119c
7093 #define _PLANE_SURF_2_B				0x7129c
7094 #define _PLANE_SURF_3_B				0x7139c
7101 #define _PLANE_OFFSET_1_B			0x711a4
7102 #define _PLANE_OFFSET_2_B			0x712a4
7108 #define _PLANE_KEYVAL_1_B			0x71194
7109 #define _PLANE_KEYVAL_2_B			0x71294
7115 #define _PLANE_KEYMSK_1_B			0x71198
7116 #define _PLANE_KEYMSK_2_B			0x71298
7122 #define _PLANE_KEYMAX_1_B			0x711a0
7123 #define _PLANE_KEYMAX_2_B			0x712a0
7129 #define _PLANE_BUF_CFG_1_B			0x7127c
7130 #define _PLANE_BUF_CFG_2_B			0x7137c
7131 #define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */
7140 #define _PLANE_NV12_BUF_CFG_1_B		0x71278
7141 #define _PLANE_NV12_BUF_CFG_2_B		0x71378
7149 #define _PLANE_AUX_DIST_1_B		0x711c0
7150 #define _PLANE_AUX_DIST_2_B		0x712c0
7158 #define _PLANE_AUX_OFFSET_1_B		0x711c4
7159 #define _PLANE_AUX_OFFSET_2_B		0x712c4
7167 #define _PLANE_CUS_CTL_1_B		0x711c8
7168 #define _PLANE_CUS_CTL_2_B		0x712c8
7176 #define _PLANE_COLOR_CTL_1_B			0x711CC
7177 #define _PLANE_COLOR_CTL_2_B			0x712CC
7178 #define _PLANE_COLOR_CTL_3_B			0x713CC
7186 #define _SEL_FETCH_PLANE_BASE_1_A		0x70890
7187 #define _SEL_FETCH_PLANE_BASE_2_A		0x708B0
7188 #define _SEL_FETCH_PLANE_BASE_3_A		0x708D0
7189 #define _SEL_FETCH_PLANE_BASE_4_A		0x708F0
7190 #define _SEL_FETCH_PLANE_BASE_5_A		0x70920
7191 #define _SEL_FETCH_PLANE_BASE_6_A		0x70940
7192 #define _SEL_FETCH_PLANE_BASE_7_A		0x70960
7193 #define _SEL_FETCH_PLANE_BASE_CUR_A		0x70880
7194 #define _SEL_FETCH_PLANE_BASE_1_B		0x70990
7210 #define _SEL_FETCH_PLANE_CTL_1_A		0x70890
7216 #define _SEL_FETCH_PLANE_POS_1_A		0x70894
7221 #define _SEL_FETCH_PLANE_SIZE_1_A		0x70898
7226 #define _SEL_FETCH_PLANE_OFFSET_1_A		0x7089C
7232 #define _CUR_BUF_CFG_A				0x7017c
7233 #define _CUR_BUF_CFG_B				0x7117c
7237 #define VGACNTRL		_MMIO(0x71400)
7242 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
7246 #define CPU_VGACNTRL	_MMIO(0x41000)
7248 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
7250 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
7255 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
7256 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
7257 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
7258 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
7261 #define RR_HW_CTL       _MMIO(0x45300)
7262 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
7263 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
7265 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
7266 #define  FDI_PLL_FB_CLOCK_MASK  0xff
7267 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
7268 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
7269 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
7270 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
7271 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
7273 #define PCH_3DCGDIS0		_MMIO(0x46020)
7277 #define PCH_3DCGDIS1		_MMIO(0x46024)
7280 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
7282 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
7283 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
7286 #define _PIPEA_DATA_M1		0x60030
7287 #define  PIPE_DATA_M1_OFFSET    0
7288 #define _PIPEA_DATA_N1		0x60034
7289 #define  PIPE_DATA_N1_OFFSET    0
7291 #define _PIPEA_DATA_M2		0x60038
7292 #define  PIPE_DATA_M2_OFFSET    0
7293 #define _PIPEA_DATA_N2		0x6003c
7294 #define  PIPE_DATA_N2_OFFSET    0
7296 #define _PIPEA_LINK_M1		0x60040
7297 #define  PIPE_LINK_M1_OFFSET    0
7298 #define _PIPEA_LINK_N1		0x60044
7299 #define  PIPE_LINK_N1_OFFSET    0
7301 #define _PIPEA_LINK_M2		0x60048
7302 #define  PIPE_LINK_M2_OFFSET    0
7303 #define _PIPEA_LINK_N2		0x6004c
7304 #define  PIPE_LINK_N2_OFFSET    0
7306 /* PIPEB timing regs are same start from 0x61000 */
7308 #define _PIPEB_DATA_M1		0x61030
7309 #define _PIPEB_DATA_N1		0x61034
7310 #define _PIPEB_DATA_M2		0x61038
7311 #define _PIPEB_DATA_N2		0x6103c
7312 #define _PIPEB_LINK_M1		0x61040
7313 #define _PIPEB_LINK_N1		0x61044
7314 #define _PIPEB_LINK_M2		0x61048
7315 #define _PIPEB_LINK_N2		0x6104c
7327 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
7328 #define _PFA_CTL_1               0x68080
7329 #define _PFB_CTL_1               0x68880
7334 #define  PF_FILTER_PROGRAMMED	(0 << 23)
7338 #define _PFA_WIN_SZ		0x68074
7339 #define _PFB_WIN_SZ		0x68874
7340 #define _PFA_WIN_POS		0x68070
7341 #define _PFB_WIN_POS		0x68870
7342 #define _PFA_VSCALE		0x68084
7343 #define _PFB_VSCALE		0x68884
7344 #define _PFA_HSCALE		0x68090
7345 #define _PFB_HSCALE		0x68890
7353 #define _PSA_CTL		0x68180
7354 #define _PSB_CTL		0x68980
7356 #define _PSA_WIN_SZ		0x68174
7357 #define _PSB_WIN_SZ		0x68974
7358 #define _PSA_WIN_POS		0x68170
7359 #define _PSB_WIN_POS		0x68970
7368 #define _PS_1A_CTRL      0x68180
7369 #define _PS_2A_CTRL      0x68280
7370 #define _PS_1B_CTRL      0x68980
7371 #define _PS_2B_CTRL      0x68A80
7372 #define _PS_1C_CTRL      0x69180
7375 #define SKL_PS_SCALER_MODE_DYN  (0 << 28)
7379 #define PS_SCALER_MODE_NORMAL (0 << 29)
7383 #define PS_FILTER_MEDIUM       (0 << 23)
7387 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
7393 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
7399 #define _PS_PWR_GATE_1A     0x68160
7400 #define _PS_PWR_GATE_2A     0x68260
7401 #define _PS_PWR_GATE_1B     0x68960
7402 #define _PS_PWR_GATE_2B     0x68A60
7403 #define _PS_PWR_GATE_1C     0x69160
7405 #define PS_PWR_GATE_SETTLING_TIME_32   (0 << 3)
7409 #define PS_PWR_GATE_SLPEN_8             0
7414 #define _PS_WIN_POS_1A      0x68170
7415 #define _PS_WIN_POS_2A      0x68270
7416 #define _PS_WIN_POS_1B      0x68970
7417 #define _PS_WIN_POS_2B      0x68A70
7418 #define _PS_WIN_POS_1C      0x69170
7420 #define _PS_WIN_SZ_1A       0x68174
7421 #define _PS_WIN_SZ_2A       0x68274
7422 #define _PS_WIN_SZ_1B       0x68974
7423 #define _PS_WIN_SZ_2B       0x68A74
7424 #define _PS_WIN_SZ_1C       0x69174
7426 #define _PS_VSCALE_1A       0x68184
7427 #define _PS_VSCALE_2A       0x68284
7428 #define _PS_VSCALE_1B       0x68984
7429 #define _PS_VSCALE_2B       0x68A84
7430 #define _PS_VSCALE_1C       0x69184
7432 #define _PS_HSCALE_1A       0x68190
7433 #define _PS_HSCALE_2A       0x68290
7434 #define _PS_HSCALE_1B       0x68990
7435 #define _PS_HSCALE_2B       0x68A90
7436 #define _PS_HSCALE_1C       0x69190
7438 #define _PS_VPHASE_1A       0x68188
7439 #define _PS_VPHASE_2A       0x68288
7440 #define _PS_VPHASE_1B       0x68988
7441 #define _PS_VPHASE_2B       0x68A88
7442 #define _PS_VPHASE_1C       0x69188
7444 #define  PS_UV_RGB_PHASE(x)	((x) << 0)
7445 #define   PS_PHASE_MASK	(0x7fff << 1) /* u2.13 */
7446 #define   PS_PHASE_TRIP	(1 << 0)
7448 #define _PS_HPHASE_1A       0x68194
7449 #define _PS_HPHASE_2A       0x68294
7450 #define _PS_HPHASE_1B       0x68994
7451 #define _PS_HPHASE_2B       0x68A94
7452 #define _PS_HPHASE_1C       0x69194
7454 #define _PS_ECC_STAT_1A     0x681D0
7455 #define _PS_ECC_STAT_2A     0x682D0
7456 #define _PS_ECC_STAT_1B     0x689D0
7457 #define _PS_ECC_STAT_2B     0x68AD0
7458 #define _PS_ECC_STAT_1C     0x691D0
7490 #define _LGC_PALETTE_A           0x4a000
7491 #define _LGC_PALETTE_B           0x4a800
7494 #define LGC_PALETTE_BLUE_MASK    REG_GENMASK(7, 0)
7498 #define _PREC_PALETTE_A           0x4b000
7499 #define _PREC_PALETTE_B           0x4c000
7502 #define   PREC_PALETTE_BLUE_MASK  REG_GENMASK(9, 0)
7505 #define  _PREC_PIPEAGCMAX              0x4d000
7506 #define  _PREC_PIPEBGCMAX              0x4d010
7509 #define _GAMMA_MODE_A		0x4a480
7510 #define _GAMMA_MODE_B		0x4ac80
7514 #define  GAMMA_MODE_MODE_MASK	(3 << 0)
7515 #define  GAMMA_MODE_MODE_8BIT	(0 << 0)
7516 #define  GAMMA_MODE_MODE_10BIT	(1 << 0)
7517 #define  GAMMA_MODE_MODE_12BIT	(2 << 0)
7518 #define  GAMMA_MODE_MODE_SPLIT	(3 << 0) /* ivb-bdw */
7519 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
7522 #define CSR_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
7523 #define CSR_SSP_BASE_ADDR_GEN9	0x00002FC0
7524 #define CSR_HTP_ADDR_SKL	0x00500034
7525 #define CSR_SSP_BASE		_MMIO(0x8F074)
7526 #define CSR_HTP_SKL		_MMIO(0x8F004)
7527 #define CSR_LAST_WRITE		_MMIO(0x8F034)
7528 #define CSR_LAST_WRITE_VALUE	0xc003b400
7529 /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
7530 #define CSR_MMIO_START_RANGE	0x80000
7531 #define CSR_MMIO_END_RANGE	0x8FFFF
7532 #define SKL_CSR_DC3_DC5_COUNT	_MMIO(0x80030)
7533 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
7534 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
7535 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
7536 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
7538 #define DMC_DEBUG3		_MMIO(0x101090)
7541 #define RM_TIMEOUT		_MMIO(0x42060)
7542 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
7574 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
7593 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
7596 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
7599 #define DEISR   _MMIO(0x44000)
7600 #define DEIMR   _MMIO(0x44004)
7601 #define DEIIR   _MMIO(0x44008)
7602 #define DEIER   _MMIO(0x4400c)
7604 #define GTISR   _MMIO(0x44010)
7605 #define GTIMR   _MMIO(0x44014)
7606 #define GTIIR   _MMIO(0x44018)
7607 #define GTIER   _MMIO(0x4401c)
7609 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
7625 #define  GEN8_GT_RCS_IRQ		(1 << 0)
7627 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
7628 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
7629 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
7630 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7632 #define GEN8_RCS_IRQ_SHIFT 0
7634 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
7636 #define GEN8_VECS_IRQ_SHIFT 0
7639 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7640 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7641 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7642 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7653 #define  GEN8_PIPE_VBLANK		(1 << 0)
7686 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
7687 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
7688 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
7689 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
7707 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
7716 #define  TGL_DE_PORT_AUX_DDIA		(1 << 0)
7718 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
7719 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
7720 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
7721 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
7725 #define GEN8_PCU_ISR _MMIO(0x444e0)
7726 #define GEN8_PCU_IMR _MMIO(0x444e4)
7727 #define GEN8_PCU_IIR _MMIO(0x444e8)
7728 #define GEN8_PCU_IER _MMIO(0x444ec)
7730 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
7731 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
7732 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
7733 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
7736 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
7743 #define  GEN11_GT_DW0_IRQ		(1 << 0)
7745 #define DG1_MSTR_UNIT_INTR		_MMIO(0x190008)
7749 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
7760 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
7761 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
7762 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
7763 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
7779 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
7780 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
7784 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
7786 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
7794 #define  GEN11_RCS0			(0)
7796 #define GEN11_GT_INTR_DW1		_MMIO(0x19001c)
7800 #define GEN11_GT_INTR_DW(x)		_MMIO(0x190018 + ((x) * 4))
7802 #define GEN11_INTR_IDENTITY_REG0	_MMIO(0x190060)
7803 #define GEN11_INTR_IDENTITY_REG1	_MMIO(0x190064)
7807 #define  GEN11_INTR_ENGINE_INTR(x)	((x) & 0xffff)
7809 #define OTHER_GUC_INSTANCE	0
7812 #define GEN11_INTR_IDENTITY_REG(x)	_MMIO(0x190060 + ((x) * 4))
7814 #define GEN11_IIR_REG0_SELECTOR		_MMIO(0x190070)
7815 #define GEN11_IIR_REG1_SELECTOR		_MMIO(0x190074)
7817 #define GEN11_IIR_REG_SELECTOR(x)	_MMIO(0x190070 + ((x) * 4))
7819 #define GEN11_RENDER_COPY_INTR_ENABLE	_MMIO(0x190030)
7820 #define GEN11_VCS_VECS_INTR_ENABLE	_MMIO(0x190034)
7821 #define GEN11_GUC_SG_INTR_ENABLE	_MMIO(0x190038)
7822 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE	_MMIO(0x19003c)
7823 #define GEN11_CRYPTO_RSVD_INTR_ENABLE	_MMIO(0x190040)
7824 #define GEN11_GUNIT_CSME_INTR_ENABLE	_MMIO(0x190044)
7826 #define GEN11_RCS0_RSVD_INTR_MASK	_MMIO(0x190090)
7827 #define GEN11_BCS_RSVD_INTR_MASK	_MMIO(0x1900a0)
7828 #define GEN11_VCS0_VCS1_INTR_MASK	_MMIO(0x1900a8)
7829 #define GEN11_VCS2_VCS3_INTR_MASK	_MMIO(0x1900ac)
7830 #define GEN11_VECS0_VECS1_INTR_MASK	_MMIO(0x1900d0)
7831 #define GEN11_GUC_SG_INTR_MASK		_MMIO(0x1900e8)
7832 #define GEN11_GPM_WGBOXPERF_INTR_MASK	_MMIO(0x1900ec)
7833 #define GEN11_CRYPTO_RSVD_INTR_MASK	_MMIO(0x1900f0)
7834 #define GEN11_GUNIT_CSME_INTR_MASK	_MMIO(0x1900f4)
7837 #define   ENGINE0_MASK			REG_GENMASK(15, 0)
7839 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
7844 #define FUSE_STRAP			_MMIO(0x42014)
7855 #define FUSE_STRAP3			_MMIO(0x42020)
7858 #define ILK_DSPCLK_GATE_D			_MMIO(0x42020)
7865 #define IVB_CHICKEN3	_MMIO(0x4200c)
7869 #define CHICKEN_PAR1_1			_MMIO(0x42080)
7877 #define CHICKEN_PAR2_1		_MMIO(0x42090)
7880 #define CHICKEN_MISC_2		_MMIO(0x42084)
7886 #define CHICKEN_MISC_4		_MMIO(0x4208c)
7888 #define   FBC_STRIDE_MASK	0x1FFF
7890 #define _CHICKEN_PIPESL_1_A	0x420b0
7891 #define _CHICKEN_PIPESL_1_B	0x420b4
7893 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
7896 #define _CHICKEN_TRANS_A	0x420c0
7897 #define _CHICKEN_TRANS_B	0x420c4
7898 #define _CHICKEN_TRANS_C	0x420c8
7899 #define _CHICKEN_TRANS_EDP	0x420cc
7900 #define _CHICKEN_TRANS_D	0x420d8
7908 #define  HSW_FRAME_START_DELAY(x)	((x) << 27) /* 0-3 */
7917 #define DISP_ARB_CTL	_MMIO(0x45000)
7921 #define DISP_ARB_CTL2	_MMIO(0x45004)
7924 #define _DBUF_CTL_S1			0x45008
7925 #define _DBUF_CTL_S2			0x44FE8
7929 #define GEN7_MSG_CTL	_MMIO(0x45010)
7931 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
7933 #define _BW_BUDDY0_CTL			0x45130
7934 #define _BW_BUDDY1_CTL			0x45140
7942 #define _BW_BUDDY0_PAGE_MASK		0x45134
7943 #define _BW_BUDDY1_PAGE_MASK		0x45144
7948 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
7951 #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
7957 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
7963 #define SKL_DFSM			_MMIO(0x51000)
7967 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
7978 #define SKL_DSSM				_MMIO(0x51004)
7981 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
7985 #define GEN7_FF_SLICE_CS_CHICKEN1	_MMIO(0x20e0)
7988 #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
7992 #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
7994 #define GEN9_CTX_PREEMPT_REG		_MMIO(0x2248)
7997 #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
7998 #define GEN9_PREEMPT_3D_OBJECT_LEVEL		(1 << 0)
8000 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
8001 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
8002 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL	GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
8006 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
8010 #define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
8014   #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
8016 #define GEN8_L3CNTLREG	_MMIO(0x7034)
8019 #define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
8023 #define HIZ_CHICKEN					_MMIO(0x7018)
8027 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
8030 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
8033 #define GEN7_SARCHKMD				_MMIO(0xB000)
8037 #define GEN7_L3SQCREG1				_MMIO(0xB010)
8038 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
8040 #define GEN8_L3SQCREG1				_MMIO(0xB100)
8049 #define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))
8051 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
8052 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
8054 #define GEN7_L3CNTLREG2				_MMIO(0xB020)
8055 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
8057 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
8058 #define   GEN7_WA_L3_CHICKEN_MODE		0x20000000
8059 #define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
8062 #define GEN7_L3SQCREG4				_MMIO(0xb034)
8065 #define GEN11_SCRATCH2					_MMIO(0xb140)
8068 #define GEN8_L3SQCREG4				_MMIO(0xb118)
8074 #define HDC_CHICKEN0				_MMIO(0x7300)
8075 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
8076 #define ICL_HDC_MODE				_MMIO(0xE5F4)
8084 #define GEN8_HDC_CHICKEN1			_MMIO(0x7304)
8087 #define SLICE_ECO_CHICKEN0			_MMIO(0x7308)
8090 #define GEN9_WM_CHICKEN3			_MMIO(0x5588)
8094 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		_MMIO(0x9030)
8097 #define HSW_SCRATCH1				_MMIO(0xb038)
8100 #define BDW_SCRATCH1					_MMIO(0xb11c)
8104 #define _PIPEA_CHICKEN				0x70038
8105 #define _PIPEB_CHICKEN				0x71038
8106 #define _PIPEC_CHICKEN				0x72038
8112 #define FF_MODE2			_MMIO(0x6604)
8120 #define PCH_DISPLAY_BASE	0xc0000u
8160 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
8161 #define SDE_TRANS_MASK		(0x3f)
8200 #define SDE_FDI_RXA_CPT		(1 << 0)
8231 #define SDEISR  _MMIO(0xc4000)
8232 #define SDEIMR  _MMIO(0xc4004)
8233 #define SDEIIR  _MMIO(0xc4008)
8234 #define SDEIER  _MMIO(0xc400c)
8236 #define SERR_INT			_MMIO(0xc4040)
8241 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
8245 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
8249 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
8255 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
8260 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
8266 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
8271 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
8276 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
8277 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
8278 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
8279 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
8284 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
8286 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
8287 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
8288 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
8289 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
8296 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
8297 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)		(0x8 << (4 * (port)))
8298 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)	(0x3 << (4 * (port)))
8299 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)		(0x0 << (4 * (port)))
8300 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)	(0x1 << (4 * (port)))
8301 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)	(0x2 << (4 * (port)))
8302 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)	(0x3 << (4 * (port)))
8304 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
8307 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
8308 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
8311 #define DSCA_RC_RANGE_PARAMETERS_0		_MMIO(0x6B240)
8312 #define DSCA_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6B240 + 4)
8313 #define DSCC_RC_RANGE_PARAMETERS_0		_MMIO(0x6BA40)
8314 #define DSCC_RC_RANGE_PARAMETERS_0_UDW		_MMIO(0x6BA40 + 4)
8315 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB	(0x78208)
8316 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78208 + 4)
8317 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB	(0x78308)
8318 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB	(0x78308 + 4)
8319 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC	(0x78408)
8320 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78408 + 4)
8321 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC	(0x78508)
8322 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC	(0x78508 + 4)
8337 #define RC_MIN_QP_SHIFT				0
8339 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
8340 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
8341 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
8342 #define DSCC_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6BA48 + 4)
8343 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB	(0x78210)
8344 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78210 + 4)
8345 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB	(0x78310)
8346 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB	(0x78310 + 4)
8347 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC	(0x78410)
8348 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78410 + 4)
8349 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC	(0x78510)
8350 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC	(0x78510 + 4)
8364 #define DSCA_RC_RANGE_PARAMETERS_2		_MMIO(0x6B250)
8365 #define DSCA_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6B250 + 4)
8366 #define DSCC_RC_RANGE_PARAMETERS_2		_MMIO(0x6BA50)
8367 #define DSCC_RC_RANGE_PARAMETERS_2_UDW		_MMIO(0x6BA50 + 4)
8368 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB	(0x78218)
8369 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78218 + 4)
8370 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB	(0x78318)
8371 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB	(0x78318 + 4)
8372 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC	(0x78418)
8373 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78418 + 4)
8374 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC	(0x78518)
8375 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC	(0x78518 + 4)
8389 #define DSCA_RC_RANGE_PARAMETERS_3		_MMIO(0x6B258)
8390 #define DSCA_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6B258 + 4)
8391 #define DSCC_RC_RANGE_PARAMETERS_3		_MMIO(0x6BA58)
8392 #define DSCC_RC_RANGE_PARAMETERS_3_UDW		_MMIO(0x6BA58 + 4)
8393 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB	(0x78220)
8394 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78220 + 4)
8395 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB	(0x78320)
8396 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB	(0x78320 + 4)
8397 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC	(0x78420)
8398 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78420 + 4)
8399 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC	(0x78520)
8400 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC	(0x78520 + 4)
8430 #define _PCH_DPLL_A              0xc6014
8431 #define _PCH_DPLL_B              0xc6018
8432 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
8434 #define _PCH_FPA0                0xc6040
8435 #define  FP_CB_TUNE		(0x3 << 22)
8436 #define _PCH_FPA1                0xc6044
8437 #define _PCH_FPB0                0xc6048
8438 #define _PCH_FPB1                0xc604c
8439 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
8440 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
8442 #define PCH_DPLL_TEST           _MMIO(0xc606c)
8444 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
8445 #define  DREF_CONTROL_MASK      0x7fc3
8446 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
8450 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
8453 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
8457 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
8460 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
8462 #define  DREF_SSC1_DISABLE                      (0 << 1)
8464 #define  DREF_SSC4_DISABLE                      (0)
8467 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
8472 #define  RAWCLK_FREQ_MASK       0x3ff
8473 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
8475 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
8479 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
8481 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
8482 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
8484 #define PCH_DPLL_SEL		_MMIO(0xc7000)
8486 #define	 TRANS_DPLLA_SEL(pipe)		0
8491 #define _PCH_TRANS_HTOTAL_A		0xe0000
8493 #define  TRANS_HACTIVE_SHIFT		0
8494 #define _PCH_TRANS_HBLANK_A		0xe0004
8496 #define  TRANS_HBLANK_START_SHIFT	0
8497 #define _PCH_TRANS_HSYNC_A		0xe0008
8499 #define  TRANS_HSYNC_START_SHIFT	0
8500 #define _PCH_TRANS_VTOTAL_A		0xe000c
8502 #define  TRANS_VACTIVE_SHIFT		0
8503 #define _PCH_TRANS_VBLANK_A		0xe0010
8505 #define  TRANS_VBLANK_START_SHIFT	0
8506 #define _PCH_TRANS_VSYNC_A		0xe0014
8508 #define  TRANS_VSYNC_START_SHIFT	0
8509 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
8511 #define _PCH_TRANSA_DATA_M1	0xe0030
8512 #define _PCH_TRANSA_DATA_N1	0xe0034
8513 #define _PCH_TRANSA_DATA_M2	0xe0038
8514 #define _PCH_TRANSA_DATA_N2	0xe003c
8515 #define _PCH_TRANSA_LINK_M1	0xe0040
8516 #define _PCH_TRANSA_LINK_N1	0xe0044
8517 #define _PCH_TRANSA_LINK_M2	0xe0048
8518 #define _PCH_TRANSA_LINK_N2	0xe004c
8521 #define _VIDEO_DIP_CTL_A         0xe0200
8522 #define _VIDEO_DIP_DATA_A        0xe0208
8523 #define _VIDEO_DIP_GCP_A         0xe0210
8526 #define  GCP_AV_MUTE			(1 << 0)
8528 #define _VIDEO_DIP_CTL_B         0xe1200
8529 #define _VIDEO_DIP_DATA_B        0xe1208
8530 #define _VIDEO_DIP_GCP_B         0xe1210
8537 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
8538 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
8539 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
8541 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
8542 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
8543 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
8545 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
8546 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
8547 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
8561 #define _HSW_VIDEO_DIP_CTL_A		0x60200
8562 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
8563 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
8564 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
8565 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
8566 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
8567 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
8568 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
8569 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
8570 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
8571 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
8572 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
8573 #define _HSW_VIDEO_DIP_GCP_A		0x60210
8575 #define _HSW_VIDEO_DIP_CTL_B		0x61200
8576 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
8577 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
8578 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
8579 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
8580 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
8581 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
8582 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
8583 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
8584 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
8585 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
8586 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
8587 #define _HSW_VIDEO_DIP_GCP_B		0x61210
8595 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
8596 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
8597 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
8598 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
8611 #define _HSW_STEREO_3D_CTL_A		0x70020
8613 #define _HSW_STEREO_3D_CTL_B		0x71020
8617 #define _PCH_TRANS_HTOTAL_B          0xe1000
8618 #define _PCH_TRANS_HBLANK_B          0xe1004
8619 #define _PCH_TRANS_HSYNC_B           0xe1008
8620 #define _PCH_TRANS_VTOTAL_B          0xe100c
8621 #define _PCH_TRANS_VBLANK_B          0xe1010
8622 #define _PCH_TRANS_VSYNC_B           0xe1014
8623 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
8633 #define _PCH_TRANSB_DATA_M1	0xe1030
8634 #define _PCH_TRANSB_DATA_N1	0xe1034
8635 #define _PCH_TRANSB_DATA_M2	0xe1038
8636 #define _PCH_TRANSB_DATA_N2	0xe103c
8637 #define _PCH_TRANSB_LINK_M1	0xe1040
8638 #define _PCH_TRANSB_LINK_N1	0xe1044
8639 #define _PCH_TRANSB_LINK_M2	0xe1048
8640 #define _PCH_TRANSB_LINK_N2	0xe104c
8651 #define _PCH_TRANSACONF              0xf0008
8652 #define _PCH_TRANSBCONF              0xf1008
8655 #define  TRANS_DISABLE          (0 << 31)
8658 #define  TRANS_STATE_DISABLE    (0 << 30)
8661 #define  TRANS_FRAME_START_DELAY(x)	((x) << 27) /* ibx: 0-3 */
8663 #define  TRANS_PROGRESSIVE      (0 << 21)
8666 #define  TRANS_8BPC             (0 << 5)
8671 #define _TRANSA_CHICKEN1	 0xf0060
8672 #define _TRANSB_CHICKEN1	 0xf1060
8676 #define _TRANSA_CHICKEN2	 0xf0064
8677 #define _TRANSB_CHICKEN2	 0xf1064
8682 #define  TRANS_CHICKEN2_FRAME_START_DELAY(x)		((x) << 27) /* 0-3 */
8686 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
8692 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
8695 #define  SPT_PWM_GRANULARITY		(1 << 0)
8696 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
8700 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
8702 #define _FDI_RXA_CHICKEN        0xc200c
8703 #define _FDI_RXB_CHICKEN        0xc2010
8705 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
8708 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
8718 #define _FDI_TXA_CTL            0x60100
8719 #define _FDI_TXB_CTL            0x61100
8721 #define  FDI_TX_DISABLE         (0 << 31)
8723 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
8727 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
8731 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
8735 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
8738 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8739 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8740 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8741 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8743 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
8744 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
8745 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
8746 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
8747 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
8756 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
8764 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
8768 #define _FDI_RXA_CTL             0xf000c
8769 #define _FDI_RXB_CTL             0xf100c
8776 #define  FDI_8BPC                       (0 << 16)
8791 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
8797 #define _FDI_RXA_MISC			0xf0010
8798 #define _FDI_RXB_MISC			0xf1010
8805 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
8808 #define _FDI_RXA_TUSIZE1        0xf0030
8809 #define _FDI_RXA_TUSIZE2        0xf0038
8810 #define _FDI_RXB_TUSIZE1        0xf1030
8811 #define _FDI_RXB_TUSIZE2        0xf1038
8826 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
8828 #define _FDI_RXA_IIR            0xf0014
8829 #define _FDI_RXA_IMR            0xf0018
8830 #define _FDI_RXB_IIR            0xf1014
8831 #define _FDI_RXB_IMR            0xf1018
8835 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
8836 #define FDI_PLL_CTL_2           _MMIO(0xfe004)
8838 #define PCH_LVDS	_MMIO(0xe1180)
8841 #define _PCH_DP_B		0xe4100
8843 #define _PCH_DPB_AUX_CH_CTL	0xe4110
8844 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
8845 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
8846 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
8847 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
8848 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
8850 #define _PCH_DP_C		0xe4200
8852 #define _PCH_DPC_AUX_CH_CTL	0xe4210
8853 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
8854 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
8855 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
8856 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
8857 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
8859 #define _PCH_DP_D		0xe4300
8861 #define _PCH_DPD_AUX_CH_CTL	0xe4310
8862 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
8863 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
8864 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
8865 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
8866 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
8872 #define _TRANS_DP_CTL_A		0xe0300
8873 #define _TRANS_DP_CTL_B		0xe1300
8874 #define _TRANS_DP_CTL_C		0xe2300
8882 #define  TRANS_DP_8BPC		(0 << 9)
8888 #define  TRANS_DP_VSYNC_ACTIVE_LOW	0
8890 #define  TRANS_DP_HSYNC_ACTIVE_LOW	0
8895 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
8896 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
8897 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
8898 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
8900 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
8901 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
8902 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
8903 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
8904 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
8905 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
8908 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
8909 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
8910 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
8911 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
8912 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
8913 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
8914 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
8917 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
8918 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
8919 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
8920 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
8921 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
8923 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
8925 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
8927 #define  RC6_LOCATION				_MMIO(0xD40)
8928 #define	   RC6_CTX_IN_DRAM			(1 << 0)
8929 #define  RC6_CTX_BASE				_MMIO(0xD48)
8930 #define    RC6_CTX_BASE_MASK			0xFFFFFFF0
8931 #define  PWRCTX_MAXCNT_RCSUNIT			_MMIO(0x2054)
8932 #define  PWRCTX_MAXCNT_VCSUNIT0			_MMIO(0x12054)
8933 #define  PWRCTX_MAXCNT_BCSUNIT			_MMIO(0x22054)
8934 #define  PWRCTX_MAXCNT_VECSUNIT			_MMIO(0x1A054)
8935 #define  PWRCTX_MAXCNT_VCSUNIT1			_MMIO(0x1C054)
8936 #define    IDLE_TIME_MASK			0xFFFFF
8937 #define  FORCEWAKE				_MMIO(0xA18C)
8938 #define  FORCEWAKE_VLV				_MMIO(0x1300b0)
8939 #define  FORCEWAKE_ACK_VLV			_MMIO(0x1300b4)
8940 #define  FORCEWAKE_MEDIA_VLV			_MMIO(0x1300b8)
8941 #define  FORCEWAKE_ACK_MEDIA_VLV		_MMIO(0x1300bc)
8942 #define  FORCEWAKE_ACK_HSW			_MMIO(0x130044)
8943 #define  FORCEWAKE_ACK				_MMIO(0x130090)
8944 #define  VLV_GTLC_WAKE_CTRL			_MMIO(0x130090)
8947 #define   VLV_GTLC_ALLOWWAKEREQ			(1 << 0)
8949 #define  VLV_GTLC_PW_STATUS			_MMIO(0x130094)
8950 #define   VLV_GTLC_ALLOWWAKEACK			(1 << 0)
8954 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
8955 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
8956 #define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
8957 #define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
8958 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
8959 #define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
8960 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
8961 #define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
8962 #define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
8963 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
8964 #define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
8965 #define   FORCEWAKE_KERNEL			BIT(0)
8968 #define  FORCEWAKE_MT_ACK			_MMIO(0x130040)
8969 #define  ECOBUS					_MMIO(0xa180)
8971 #define  VLV_SPAREG2H				_MMIO(0xA194)
8972 #define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
8973 #define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
8976 #define  GTFIFODBG				_MMIO(0x120000)
8977 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)
8978 #define    GT_FIFO_FREE_ENTRIES_CHV		(0x7f << 13)
8985 #define    GT_FIFO_IARDERR			(1 << 0)
8987 #define  GTFIFOCTL				_MMIO(0x120008)
8988 #define    GT_FIFO_FREE_ENTRIES_MASK		0x7f
8993 #define  HSW_IDICR				_MMIO(0x9008)
8994 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
8995 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
8996 #define    EDRAM_ENABLED			0x1
8997 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
8998 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
8999 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
9001 #define GEN6_UCGCTL1				_MMIO(0x9400)
9007 #define GEN6_UCGCTL2				_MMIO(0x9404)
9015 #define GEN6_UCGCTL3				_MMIO(0x9408)
9018 #define GEN7_UCGCTL4				_MMIO(0x940c)
9022 #define GEN6_RCGCTL1				_MMIO(0x9410)
9023 #define GEN6_RCGCTL2				_MMIO(0x9414)
9024 #define GEN6_RSTCTL				_MMIO(0x9420)
9026 #define GEN8_UCGCTL6				_MMIO(0x9430)
9031 #define GEN6_GFXPAUSE				_MMIO(0xA000)
9032 #define GEN6_RPNSWREQ				_MMIO(0xA008)
9038 #define   GEN6_AGGRESSIVE_TURBO			(0 << 15)
9039 #define GEN6_RC_VIDEO_FREQ			_MMIO(0xA00C)
9040 #define GEN6_RC_CONTROL				_MMIO(0xA090)
9050 #define GEN6_RP_DOWN_TIMEOUT			_MMIO(0xA010)
9051 #define GEN6_RP_INTERRUPT_LIMITS		_MMIO(0xA014)
9052 #define GEN6_RPSTAT1				_MMIO(0xA01C)
9056 #define   GEN6_CAGF_MASK			(0x7f << GEN6_CAGF_SHIFT)
9057 #define   HSW_CAGF_MASK				(0x7f << HSW_CAGF_SHIFT)
9058 #define   GEN9_CAGF_MASK			(0x1ff << GEN9_CAGF_SHIFT)
9059 #define GEN6_RP_CONTROL				_MMIO(0xA024)
9065 #define   GEN6_RP_MEDIA_SW_MODE			(0 << 9)
9068 #define   GEN6_RP_UP_IDLE_MIN			(0x1 << 3)
9069 #define   GEN6_RP_UP_BUSY_AVG			(0x2 << 3)
9070 #define   GEN6_RP_UP_BUSY_CONT			(0x4 << 3)
9071 #define   GEN6_RP_DOWN_IDLE_AVG			(0x2 << 0)
9072 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1 << 0)
9073 #define GEN6_RP_UP_THRESHOLD			_MMIO(0xA02C)
9074 #define GEN6_RP_DOWN_THRESHOLD			_MMIO(0xA030)
9075 #define GEN6_RP_CUR_UP_EI			_MMIO(0xA050)
9076 #define   GEN6_RP_EI_MASK			0xffffff
9078 #define GEN6_RP_CUR_UP				_MMIO(0xA054)
9080 #define GEN6_RP_PREV_UP				_MMIO(0xA058)
9081 #define GEN6_RP_CUR_DOWN_EI			_MMIO(0xA05C)
9083 #define GEN6_RP_CUR_DOWN			_MMIO(0xA060)
9084 #define GEN6_RP_PREV_DOWN			_MMIO(0xA064)
9085 #define GEN6_RP_UP_EI				_MMIO(0xA068)
9086 #define GEN6_RP_DOWN_EI				_MMIO(0xA06C)
9087 #define GEN6_RP_IDLE_HYSTERSIS			_MMIO(0xA070)
9088 #define GEN6_RPDEUHWTC				_MMIO(0xA080)
9089 #define GEN6_RPDEUC				_MMIO(0xA084)
9090 #define GEN6_RPDEUCSW				_MMIO(0xA088)
9091 #define GEN6_RC_STATE				_MMIO(0xA094)
9094 #define GEN6_RC1_WAKE_RATE_LIMIT		_MMIO(0xA098)
9095 #define GEN6_RC6_WAKE_RATE_LIMIT		_MMIO(0xA09C)
9096 #define GEN6_RC6pp_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9097 #define GEN10_MEDIA_WAKE_RATE_LIMIT		_MMIO(0xA0A0)
9098 #define GEN6_RC_EVALUATION_INTERVAL		_MMIO(0xA0A8)
9099 #define GEN6_RC_IDLE_HYSTERSIS			_MMIO(0xA0AC)
9100 #define GEN6_RC_SLEEP				_MMIO(0xA0B0)
9101 #define GEN6_RCUBMABDTMR			_MMIO(0xA0B0)
9102 #define GEN6_RC1e_THRESHOLD			_MMIO(0xA0B4)
9103 #define GEN6_RC6_THRESHOLD			_MMIO(0xA0B8)
9104 #define GEN6_RC6p_THRESHOLD			_MMIO(0xA0BC)
9105 #define VLV_RCEDATA				_MMIO(0xA0BC)
9106 #define GEN6_RC6pp_THRESHOLD			_MMIO(0xA0C0)
9107 #define GEN6_PMINTRMSK				_MMIO(0xA168)
9110 #define GEN8_MISC_CTRL0				_MMIO(0xA180)
9111 #define VLV_PWRDWNUPCTL				_MMIO(0xA294)
9112 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS		_MMIO(0xA0C4)
9113 #define GEN9_RENDER_PG_IDLE_HYSTERESIS		_MMIO(0xA0C8)
9114 #define GEN9_PG_ENABLE				_MMIO(0xA210)
9115 #define   GEN9_RENDER_PG_ENABLE			REG_BIT(0)
9120 #define GEN8_PUSHBUS_CONTROL			_MMIO(0xA248)
9121 #define GEN8_PUSHBUS_ENABLE			_MMIO(0xA250)
9122 #define GEN8_PUSHBUS_SHIFT			_MMIO(0xA25C)
9124 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
9128 #define GEN6_PMISR				_MMIO(0x44020)
9129 #define GEN6_PMIMR				_MMIO(0x44024) /* rps_lock */
9130 #define GEN6_PMIIR				_MMIO(0x44028)
9131 #define GEN6_PMIER				_MMIO(0x4402C)
9150 #define GEN7_GT_SCRATCH(i)			_MMIO(0x4F100 + (i) * 4)
9153 #define VLV_GTLC_SURVIVABILITY_REG              _MMIO(0x130098)
9157 #define GEN6_GT_GFX_RC6_LOCKED			_MMIO(0x138104)
9158 #define VLV_COUNTER_CONTROL			_MMIO(0x138104)
9163 #define   VLV_RENDER_RC6_COUNT_EN		(1 << 0)
9164 #define GEN6_GT_GFX_RC6				_MMIO(0x138108)
9165 #define VLV_GT_RENDER_RC6			_MMIO(0x138108)
9166 #define VLV_GT_MEDIA_RC6			_MMIO(0x13810C)
9168 #define GEN6_GT_GFX_RC6p			_MMIO(0x13810C)
9169 #define GEN6_GT_GFX_RC6pp			_MMIO(0x138110)
9170 #define VLV_RENDER_C0_COUNT			_MMIO(0x138118)
9171 #define VLV_MEDIA_C0_COUNT			_MMIO(0x13811C)
9173 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
9175 #define   GEN6_PCODE_ERROR_MASK			0xFF
9176 #define     GEN6_PCODE_SUCCESS			0x0
9177 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
9178 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
9179 #define     GEN6_PCODE_TIMEOUT			0x3
9180 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
9181 #define     GEN7_PCODE_TIMEOUT			0x2
9182 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
9183 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
9184 #define     GEN11_PCODE_LOCKED			0x6
9185 #define     GEN11_PCODE_REJECTED		0x11
9186 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
9187 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
9188 #define   GEN6_PCODE_READ_RC6VIDS		0x5
9191 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
9192 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
9193 #define     GEN9_MEM_LATENCY_LEVEL_MASK		0xFF
9197 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
9198 #define   SKL_PCODE_CDCLK_CONTROL		0x7
9199 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
9200 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
9201 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
9202 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
9203 #define   GEN6_READ_OC_PARAMS			0xc
9204 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
9205 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
9206 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
9207 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
9208 #define     ICL_PCODE_POINTS_RESTRICTED		0x0
9209 #define     ICL_PCODE_POINTS_RESTRICTED_MASK	0x1
9210 #define   GEN6_PCODE_READ_D_COMP		0x10
9211 #define   GEN6_PCODE_WRITE_D_COMP		0x11
9212 #define   ICL_PCODE_EXIT_TCCOLD			0x12
9213 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
9214 #define   DISPLAY_IPS_CONTROL			0x19
9215 #define   TGL_PCODE_TCCOLD			0x26
9216 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
9217 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
9218 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
9221 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
9222 #define   GEN9_PCODE_SAGV_CONTROL		0x21
9223 #define     GEN9_SAGV_DISABLE			0x0
9224 #define     GEN9_SAGV_IS_DISABLED		0x1
9225 #define     GEN9_SAGV_ENABLE			0x3
9226 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
9227 #define GEN6_PCODE_DATA				_MMIO(0x138128)
9230 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
9232 #define GEN6_GT_CORE_STATUS		_MMIO(0x138060)
9235 #define   GEN6_RC0			0
9240 #define GEN8_GT_SLICE_INFO		_MMIO(0x138064)
9241 #define   GEN8_LSLICESTAT_MASK		0x7
9243 #define CHV_POWER_SS0_SIG1		_MMIO(0xa720)
9244 #define CHV_POWER_SS1_SIG1		_MMIO(0xa728)
9250 #define CHV_POWER_SS0_SIG2		_MMIO(0xa724)
9251 #define CHV_POWER_SS1_SIG2		_MMIO(0xa72c)
9254 #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
9255 #define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
9256 					      ((slice) % 3) * 0x4)
9257 #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
9259 #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
9261 #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
9262 #define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
9263 					      ((slice) % 3) * 0x8)
9264 #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
9265 #define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
9266 					      ((slice) % 3) * 0x8)
9267 #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
9276 #define GEN7_MISCCPCTL				_MMIO(0x9424)
9277 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)
9282 #define GEN8_GARBCNTL				_MMIO(0xB004)
9284 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
9285 #define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
9286 #define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
9288 #define GEN11_GLBLINVL				_MMIO(0xB404)
9289 #define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
9292 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
9295 #define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
9296 #define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
9297 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
9300 #define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
9304 #define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
9309 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
9310 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
9322 #define GEN7_L3LOG(slice, i)		_MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
9323 #define GEN7_L3LOG_SIZE			0x80
9325 #define GEN7_HALF_SLICE_CHICKEN1	_MMIO(0xe100) /* IVB GT1 + VLV */
9326 #define GEN7_HALF_SLICE_CHICKEN1_GT2	_MMIO(0xf100)
9332 #define GEN9_HALF_SLICE_CHICKEN5	_MMIO(0xe188)
9336 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
9343 #define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)
9347 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
9348 #define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
9352 #define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)
9356 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
9359 #define HALF_SLICE_CHICKEN2		_MMIO(0xe180)
9362 #define HALF_SLICE_CHICKEN3		_MMIO(0xe184)
9369 #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
9375 #define G4X_AUD_VID_DID			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
9376 #define   INTEL_AUDIO_DEVCL		0x808629FB
9377 #define   INTEL_AUDIO_DEVBLC		0x80862801
9378 #define   INTEL_AUDIO_DEVCTG		0x80862802
9380 #define G4X_AUD_CNTL_ST			_MMIO(0x620B4)
9383 #define   G4X_ELD_ADDR_MASK		(0xf << 5)
9385 #define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)
9387 #define _IBX_HDMIW_HDMIEDID_A		0xE2050
9388 #define _IBX_HDMIW_HDMIEDID_B		0xE2150
9391 #define _IBX_AUD_CNTL_ST_A		0xE20B4
9392 #define _IBX_AUD_CNTL_ST_B		0xE21B4
9395 #define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)
9396 #define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)
9398 #define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)
9400 #define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))
9402 #define _CPT_HDMIW_HDMIEDID_A		0xE5050
9403 #define _CPT_HDMIW_HDMIEDID_B		0xE5150
9405 #define _CPT_AUD_CNTL_ST_A		0xE50B4
9406 #define _CPT_AUD_CNTL_ST_B		0xE51B4
9408 #define CPT_AUD_CNTRL_ST2		_MMIO(0xE50C0)
9410 #define _VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
9411 #define _VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
9413 #define _VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
9414 #define _VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
9416 #define VLV_AUD_CNTL_ST2		_MMIO(VLV_DISPLAY_BASE + 0x620C0)
9422 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
9424 #define _IBX_AUD_CONFIG_A		0xe2000
9425 #define _IBX_AUD_CONFIG_B		0xe2100
9427 #define _CPT_AUD_CONFIG_A		0xe5000
9428 #define _CPT_AUD_CONFIG_B		0xe5100
9430 #define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)
9431 #define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)
9437 #define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)
9439 #define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)
9442 	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\
9443 	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
9445 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)
9446 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)
9463 #define _HSW_AUD_CONFIG_A		0x65000
9464 #define _HSW_AUD_CONFIG_B		0x65100
9467 #define _HSW_AUD_MISC_CTRL_A		0x65010
9468 #define _HSW_AUD_MISC_CTRL_B		0x65110
9471 #define _HSW_AUD_M_CTS_ENABLE_A		0x65028
9472 #define _HSW_AUD_M_CTS_ENABLE_B		0x65128
9476 #define   AUD_CONFIG_M_MASK		0xfffff
9478 #define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4
9479 #define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
9483 #define _HSW_AUD_DIG_CNVT_1		0x65080
9484 #define _HSW_AUD_DIG_CNVT_2		0x65180
9486 #define DIP_PORT_SEL_MASK		0x3
9488 #define _HSW_AUD_EDID_DATA_A		0x65050
9489 #define _HSW_AUD_EDID_DATA_B		0x65150
9492 #define HSW_AUD_PIPE_CONV_CFG		_MMIO(0x6507c)
9493 #define HSW_AUD_PIN_ELD_CP_VLD		_MMIO(0x650c0)
9497 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
9499 #define HSW_AUD_CHICKENBIT			_MMIO(0x65f10)
9502 #define AUD_FREQ_CNTRL			_MMIO(0x65900)
9503 #define AUD_PIN_BUF_CTL		_MMIO(0x48414)
9507 #define AUD_CONFIG_BE			_MMIO(0x65ef0)
9508 #define HBLANK_EARLY_ENABLE_ICL(pipe)		(0x1 << (20 - (pipe)))
9509 #define HBLANK_EARLY_ENABLE_TGL(pipe)		(0x1 << (24 + (pipe)))
9510 #define HBLANK_START_COUNT_MASK(pipe)		(0x7 << (3 + ((pipe) * 6)))
9511 #define HBLANK_START_COUNT(pipe, val)		(((val) & 0x7) << (3 + ((pipe)) * 6))
9512 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe)	(0x3 << ((pipe) * 6))
9513 #define NUMBER_SAMPLES_PER_LINE(pipe, val)	(((val) & 0x3) << ((pipe) * 6))
9515 #define HBLANK_START_COUNT_8	0
9537 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
9538 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
9539 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
9540 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
9541 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
9542 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
9561 #define   SKL_PW_CTL_IDX_MISC_IO		0
9568 #define   ICL_PW_CTL_IDX_PW_1			0
9570 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
9571 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
9572 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
9594 #define   ICL_PW_CTL_IDX_AUX_A			0
9596 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
9597 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
9598 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
9610 #define   ICL_PW_CTL_IDX_DDI_A			0
9613 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
9617 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
9628 #define SKL_FUSE_STATUS				_MMIO(0x42000)
9645 #define _CNL_AUX_ANAOVRD1_B		0x162250
9646 #define _CNL_AUX_ANAOVRD1_C		0x162210
9647 #define _CNL_AUX_ANAOVRD1_D		0x1622D0
9648 #define _CNL_AUX_ANAOVRD1_F		0x162A90
9658 #define _ICL_AUX_ANAOVRD1_A		0x162398
9659 #define _ICL_AUX_ANAOVRD1_B		0x6C398
9664 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
9667 #define HDCP_KEY_CONF			_MMIO(0x66c00)
9671 #define HDCP_KEY_STATUS			_MMIO(0x66c04)
9676 #define  HDCP_KEY_LOAD_DONE		BIT(0)
9677 #define HDCP_AKSV_LO			_MMIO(0x66c10)
9678 #define HDCP_AKSV_HI			_MMIO(0x66c14)
9681 #define HDCP_REP_CTL			_MMIO(0x66d00)
9712 #define HDCP_SHA_V_PRIME_H0		_MMIO(0x66d04)
9713 #define HDCP_SHA_V_PRIME_H1		_MMIO(0x66d08)
9714 #define HDCP_SHA_V_PRIME_H2		_MMIO(0x66d0C)
9715 #define HDCP_SHA_V_PRIME_H3		_MMIO(0x66d10)
9716 #define HDCP_SHA_V_PRIME_H4		_MMIO(0x66d14)
9717 #define HDCP_SHA_V_PRIME(h)		_MMIO((0x66d04 + (h) * 4))
9718 #define HDCP_SHA_TEXT			_MMIO(0x66d18)
9721 #define _PORTA_HDCP_AUTHENC		0x66800
9722 #define _PORTB_HDCP_AUTHENC		0x66500
9723 #define _PORTC_HDCP_AUTHENC		0x66600
9724 #define _PORTD_HDCP_AUTHENC		0x66700
9725 #define _PORTE_HDCP_AUTHENC		0x66A00
9726 #define _PORTF_HDCP_AUTHENC		0x66900
9734 #define PORT_HDCP_CONF(port)		_PORT_HDCP_AUTHENC(port, 0x0)
9735 #define _TRANSA_HDCP_CONF		0x66400
9736 #define _TRANSB_HDCP_CONF		0x66500
9744 #define  HDCP_CONF_CAPTURE_AN		BIT(0)
9745 #define  HDCP_CONF_AUTH_AND_ENC		(BIT(1) | BIT(0))
9746 #define PORT_HDCP_ANINIT(port)		_PORT_HDCP_AUTHENC(port, 0x4)
9747 #define _TRANSA_HDCP_ANINIT		0x66404
9748 #define _TRANSB_HDCP_ANINIT		0x66504
9757 #define PORT_HDCP_ANLO(port)		_PORT_HDCP_AUTHENC(port, 0x8)
9758 #define _TRANSA_HDCP_ANLO		0x66408
9759 #define _TRANSB_HDCP_ANLO		0x66508
9767 #define PORT_HDCP_ANHI(port)		_PORT_HDCP_AUTHENC(port, 0xC)
9768 #define _TRANSA_HDCP_ANHI		0x6640C
9769 #define _TRANSB_HDCP_ANHI		0x6650C
9777 #define PORT_HDCP_BKSVLO(port)		_PORT_HDCP_AUTHENC(port, 0x10)
9778 #define _TRANSA_HDCP_BKSVLO		0x66410
9779 #define _TRANSB_HDCP_BKSVLO		0x66510
9788 #define PORT_HDCP_BKSVHI(port)		_PORT_HDCP_AUTHENC(port, 0x14)
9789 #define _TRANSA_HDCP_BKSVHI		0x66414
9790 #define _TRANSB_HDCP_BKSVHI		0x66514
9799 #define PORT_HDCP_RPRIME(port)		_PORT_HDCP_AUTHENC(port, 0x18)
9800 #define _TRANSA_HDCP_RPRIME		0x66418
9801 #define _TRANSB_HDCP_RPRIME		0x66518
9810 #define PORT_HDCP_STATUS(port)		_PORT_HDCP_AUTHENC(port, 0x1C)
9811 #define _TRANSA_HDCP_STATUS		0x6641C
9812 #define _TRANSB_HDCP_STATUS		0x6651C
9831 #define  HDCP_STATUS_FRAME_CNT(x)	(((x) >> 8) & 0xff)
9834 #define _PORTA_HDCP2_BASE		0x66800
9835 #define _PORTB_HDCP2_BASE		0x66500
9836 #define _PORTC_HDCP2_BASE		0x66600
9837 #define _PORTD_HDCP2_BASE		0x66700
9838 #define _PORTE_HDCP2_BASE		0x66A00
9839 #define _PORTF_HDCP2_BASE		0x66900
9847 #define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)
9848 #define _TRANSA_HDCP2_AUTH		0x66498
9849 #define _TRANSB_HDCP2_AUTH		0x66598
9861 #define PORT_HDCP2_CTL(port)		_PORT_HDCP2_BASE(port, 0xB0)
9862 #define _TRANSA_HDCP2_CTL		0x664B0
9863 #define _TRANSB_HDCP2_CTL		0x665B0
9872 #define PORT_HDCP2_STATUS(port)		_PORT_HDCP2_BASE(port, 0xB4)
9873 #define _TRANSA_HDCP2_STATUS		0x664B4
9874 #define _TRANSB_HDCP2_STATUS		0x665B4
9887 #define _TRANS_DDI_FUNC_CTL_A		0x60400
9888 #define _TRANS_DDI_FUNC_CTL_B		0x61400
9889 #define _TRANS_DDI_FUNC_CTL_C		0x62400
9890 #define _TRANS_DDI_FUNC_CTL_D		0x63400
9891 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
9892 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
9893 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
9901 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
9907 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
9913 #define  TRANS_DDI_BPC_8		(0 << 20)
9923 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
9937 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
9942 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
9943 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
9944 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
9945 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
9946 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
9947 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
9950 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
9954 #define _DP_TP_CTL_A			0x64040
9955 #define _DP_TP_CTL_B			0x64140
9956 #define _TGL_DP_TP_CTL_A		0x60540
9961 #define  DP_TP_CTL_MODE_SST			(0 << 27)
9967 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
9976 #define _DP_TP_STATUS_A			0x64044
9977 #define _DP_TP_STATUS_B			0x64144
9978 #define _TGL_DP_TP_STATUS_A		0x60544
9988 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
9991 #define _DDI_BUF_CTL_A				0x64000
9992 #define _DDI_BUF_CTL_B				0x64100
9996 #define  DDI_BUF_EMP_MASK			(0xf << 24)
10003 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
10006 #define _DDI_BUF_TRANS_A		0x64E00
10007 #define _DDI_BUF_TRANS_B		0x64E60
10013 #define _DDI_DP_COMP_CTL_A			0x605F0
10014 #define _DDI_DP_COMP_CTL_B			0x615F0
10017 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
10023 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
10026 #define _DDI_DP_COMP_PAT_A			0x605F4
10027 #define _DDI_DP_COMP_PAT_B			0x615F4
10033 #define SBI_ADDR			_MMIO(0xC6000)
10034 #define SBI_DATA			_MMIO(0xC6004)
10035 #define SBI_CTL_STAT			_MMIO(0xC6008)
10036 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
10037 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
10038 #define  SBI_CTL_OP_IORD		(0x2 << 8)
10039 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
10040 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
10041 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
10042 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
10043 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
10044 #define  SBI_BUSY			(0x1 << 0)
10045 #define  SBI_READY			(0x0 << 0)
10048 #define  SBI_SSCDIVINTPHASE			0x0200
10049 #define  SBI_SSCDIVINTPHASE6			0x0600
10051 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
10054 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
10057 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
10058 #define  SBI_SSCDITHPHASE			0x0204
10059 #define  SBI_SSCCTL				0x020c
10060 #define  SBI_SSCCTL6				0x060C
10062 #define   SBI_SSCCTL_DISABLE			(1 << 0)
10063 #define  SBI_SSCAUXDIV6				0x0610
10067 #define  SBI_DBUFF0				0x2a00
10068 #define  SBI_GEN0				0x1f00
10069 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
10072 #define PIXCLK_GATE			_MMIO(0xC6020)
10073 #define  PIXCLK_GATE_UNGATE		(1 << 0)
10074 #define  PIXCLK_GATE_GATE		(0 << 0)
10077 #define SPLL_CTL			_MMIO(0x46020)
10079 #define  SPLL_REF_BCLK			(0 << 28)
10085 #define  SPLL_FREQ_810MHz		(0 << 26)
10091 #define _WRPLL_CTL1			0x46040
10092 #define _WRPLL_CTL2			0x46060
10095 #define  WRPLL_REF_BCLK			(0 << 28)
10102 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
10103 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
10105 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
10109 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
10112 #define _PORT_CLK_SEL_A			0x46100
10113 #define _PORT_CLK_SEL_B			0x46104
10115 #define  PORT_CLK_SEL_LCPLL_2700	(0 << 29)
10127 #define  DDI_CLK_SEL_NONE		(0x0 << 28)
10128 #define  DDI_CLK_SEL_MG			(0x8 << 28)
10129 #define  DDI_CLK_SEL_TBT_162		(0xC << 28)
10130 #define  DDI_CLK_SEL_TBT_270		(0xD << 28)
10131 #define  DDI_CLK_SEL_TBT_540		(0xE << 28)
10132 #define  DDI_CLK_SEL_TBT_810		(0xF << 28)
10133 #define  DDI_CLK_SEL_MASK		(0xF << 28)
10136 #define _TRANS_CLK_SEL_A		0x46140
10137 #define _TRANS_CLK_SEL_B		0x46144
10140 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
10142 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
10146 #define CDCLK_FREQ			_MMIO(0x46200)
10148 #define _TRANSA_MSA_MISC		0x60410
10149 #define _TRANSB_MSA_MISC		0x61410
10150 #define _TRANSC_MSA_MISC		0x62410
10151 #define _TRANS_EDP_MSA_MISC		0x6f410
10156 #define LCPLL_CTL			_MMIO(0x130040)
10159 #define  LCPLL_REF_NON_SSC		(0 << 28)
10164 #define  LCPLL_CLK_FREQ_450		(0 << 26)
10180 #define CDCLK_CTL			_MMIO(0x46000)
10182 #define  CDCLK_FREQ_450_432		(0 << 26)
10187 #define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)
10194 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
10199 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
10202 #define LCPLL1_CTL		_MMIO(0x46010)
10203 #define LCPLL2_CTL		_MMIO(0x46014)
10207 #define DPLL_CTRL1		_MMIO(0x6C058)
10214 #define  DPLL_CTRL1_LINK_RATE_2700		0
10222 #define DPLL_CTRL2				_MMIO(0x6C05C)
10230 #define DPLL_STATUS	_MMIO(0x6C060)
10234 #define _DPLL1_CFGCR1	0x6C040
10235 #define _DPLL2_CFGCR1	0x6C048
10236 #define _DPLL3_CFGCR1	0x6C050
10238 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
10240 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
10242 #define _DPLL1_CFGCR2	0x6C044
10243 #define _DPLL2_CFGCR2	0x6C04C
10244 #define _DPLL3_CFGCR2	0x6C054
10245 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
10250 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
10256 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
10268 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
10276 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
10285 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
10292 #define DPLL0_ENABLE		0x46010
10293 #define DPLL1_ENABLE		0x46014
10300 #define TBT_PLL_ENABLE		_MMIO(0x46020)
10302 #define _MG_PLL1_ENABLE		0x46030
10303 #define _MG_PLL2_ENABLE		0x46034
10304 #define _MG_PLL3_ENABLE		0x46038
10305 #define _MG_PLL4_ENABLE		0x4603C
10310 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
10311 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
10312 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
10313 #define _MG_REFCLKIN_CTL_PORT4				0x16B92C
10315 #define   MG_REFCLKIN_CTL_OD_2_MUX_MASK			(0x7 << 8)
10320 #define _MG_CLKTOP2_CORECLKCTL1_PORT1			0x1688D8
10321 #define _MG_CLKTOP2_CORECLKCTL1_PORT2			0x1698D8
10322 #define _MG_CLKTOP2_CORECLKCTL1_PORT3			0x16A8D8
10323 #define _MG_CLKTOP2_CORECLKCTL1_PORT4			0x16B8D8
10325 #define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK	(0xff << 16)
10327 #define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK	(0xff << 8)
10332 #define _MG_CLKTOP2_HSCLKCTL_PORT1			0x1688D4
10333 #define _MG_CLKTOP2_HSCLKCTL_PORT2			0x1698D4
10334 #define _MG_CLKTOP2_HSCLKCTL_PORT3			0x16A8D4
10335 #define _MG_CLKTOP2_HSCLKCTL_PORT4			0x16B8D4
10337 #define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)
10339 #define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)
10340 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)
10341 #define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)
10347 #define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)
10352 #define _MG_PLL_DIV0_PORT1				0x168A00
10353 #define _MG_PLL_DIV0_PORT2				0x169A00
10354 #define _MG_PLL_DIV0_PORT3				0x16AA00
10355 #define _MG_PLL_DIV0_PORT4				0x16BA00
10357 #define   MG_PLL_DIV0_FBDIV_FRAC_MASK			(0x3fffff << 8)
10360 #define   MG_PLL_DIV0_FBDIV_INT_MASK			(0xff << 0)
10361 #define   MG_PLL_DIV0_FBDIV_INT(x)			((x) << 0)
10365 #define _MG_PLL_DIV1_PORT1				0x168A04
10366 #define _MG_PLL_DIV1_PORT2				0x169A04
10367 #define _MG_PLL_DIV1_PORT3				0x16AA04
10368 #define _MG_PLL_DIV1_PORT4				0x16BA04
10370 #define   MG_PLL_DIV1_DITHER_DIV_1			(0 << 12)
10375 #define   MG_PLL_DIV1_FBPREDIV_MASK			(0xf << 0)
10376 #define   MG_PLL_DIV1_FBPREDIV(x)			((x) << 0)
10380 #define _MG_PLL_LF_PORT1				0x168A08
10381 #define _MG_PLL_LF_PORT2				0x169A08
10382 #define _MG_PLL_LF_PORT3				0x16AA08
10383 #define _MG_PLL_LF_PORT4				0x16BA08
10385 #define   MG_PLL_LF_AFCCNTSEL_256			(0 << 20)
10389 #define   MG_PLL_LF_PROP_COEFF(x)			((x) << 0)
10393 #define _MG_PLL_FRAC_LOCK_PORT1				0x168A0C
10394 #define _MG_PLL_FRAC_LOCK_PORT2				0x169A0C
10395 #define _MG_PLL_FRAC_LOCK_PORT3				0x16AA0C
10396 #define _MG_PLL_FRAC_LOCK_PORT4				0x16BA0C
10402 #define   MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x)		((x) << 0)
10407 #define _MG_PLL_SSC_PORT1				0x168A10
10408 #define _MG_PLL_SSC_PORT2				0x169A10
10409 #define _MG_PLL_SSC_PORT3				0x16AA10
10410 #define _MG_PLL_SSC_PORT4				0x16BA10
10416 #define   MG_PLL_SSC_STEPSIZE(x)			((x) << 0)
10420 #define _MG_PLL_BIAS_PORT1				0x168A14
10421 #define _MG_PLL_BIAS_PORT2				0x169A14
10422 #define _MG_PLL_BIAS_PORT3				0x16AA14
10423 #define _MG_PLL_BIAS_PORT4				0x16BA14
10425 #define   MG_PLL_BIAS_BIAS_GB_SEL_MASK			(0x3 << 30)
10427 #define   MG_PLL_BIAS_INIT_DCOAMP_MASK			(0x3f << 24)
10429 #define   MG_PLL_BIAS_BIAS_BONUS_MASK			(0xff << 16)
10432 #define   MG_PLL_BIAS_CTRIM_MASK			(0x1f << 8)
10434 #define   MG_PLL_BIAS_VREF_RDAC_MASK			(0x7 << 5)
10435 #define   MG_PLL_BIAS_IREFTRIM(x)			((x) << 0)
10436 #define   MG_PLL_BIAS_IREFTRIM_MASK			(0x1f << 0)
10440 #define _MG_PLL_TDC_COLDST_BIAS_PORT1			0x168A18
10441 #define _MG_PLL_TDC_COLDST_BIAS_PORT2			0x169A18
10442 #define _MG_PLL_TDC_COLDST_BIAS_PORT3			0x16AA18
10443 #define _MG_PLL_TDC_COLDST_BIAS_PORT4			0x16BA18
10448 #define   MG_PLL_TDC_TDCSEL(x)				((x) << 0)
10453 #define _CNL_DPLL0_CFGCR0		0x6C000
10454 #define _CNL_DPLL1_CFGCR0		0x6C080
10458 #define  DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
10459 #define  DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
10467 #define  DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
10470 #define  DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
10473 #define _CNL_DPLL0_CFGCR1		0x6C004
10474 #define _CNL_DPLL1_CFGCR1		0x6C084
10475 #define  DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
10486 #define  DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
10493 #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
10494 #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
10495 #define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
10498 #define _ICL_DPLL0_CFGCR0		0x164000
10499 #define _ICL_DPLL1_CFGCR0		0x164080
10503 #define _ICL_DPLL0_CFGCR1		0x164004
10504 #define _ICL_DPLL1_CFGCR1		0x164084
10508 #define _TGL_DPLL0_CFGCR0		0x164284
10509 #define _TGL_DPLL1_CFGCR0		0x16428C
10510 #define _TGL_TBTPLL_CFGCR0		0x16429C
10517 #define _TGL_DPLL0_CFGCR1		0x164288
10518 #define _TGL_DPLL1_CFGCR1		0x164290
10519 #define _TGL_TBTPLL_CFGCR1		0x1642A0
10526 #define _DKL_PHY1_BASE			0x168000
10527 #define _DKL_PHY2_BASE			0x169000
10528 #define _DKL_PHY3_BASE			0x16A000
10529 #define _DKL_PHY4_BASE			0x16B000
10530 #define _DKL_PHY5_BASE			0x16C000
10531 #define _DKL_PHY6_BASE			0x16D000
10534 #define _DKL_PLL_DIV0			0x200
10536 #define   DKL_PLL_DIV0_INTEG_COEFF_MASK	(0x1F << 16)
10538 #define   DKL_PLL_DIV0_PROP_COEFF_MASK	(0xF << 12)
10541 #define   DKL_PLL_DIV0_FBPREDIV_MASK	(0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT)
10542 #define   DKL_PLL_DIV0_FBDIV_INT(x)	((x) << 0)
10543 #define   DKL_PLL_DIV0_FBDIV_INT_MASK	(0xFF << 0)
10548 #define _DKL_PLL_DIV1				0x204
10550 #define   DKL_PLL_DIV1_IREF_TRIM_MASK		(0x1F << 16)
10551 #define   DKL_PLL_DIV1_TDC_TARGET_CNT(x)	((x) << 0)
10552 #define   DKL_PLL_DIV1_TDC_TARGET_CNT_MASK	(0xFF << 0)
10557 #define _DKL_PLL_SSC				0x210
10559 #define   DKL_PLL_SSC_IREF_NDIV_RATIO_MASK	(0x7 << 29)
10561 #define   DKL_PLL_SSC_STEP_LEN_MASK		(0xFF << 16)
10563 #define   DKL_PLL_SSC_STEP_NUM_MASK		(0x7 << 11)
10569 #define _DKL_PLL_BIAS			0x214
10573 #define   DKL_PLL_BIAS_FBDIV_FRAC_MASK	(0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT)
10578 #define _DKL_PLL_TDC_COLDST_BIAS		0x218
10580 #define   DKL_PLL_TDC_SSC_STEP_SIZE_MASK	(0xFF << 8)
10581 #define   DKL_PLL_TDC_FEED_FWD_GAIN(x)		((x) << 0)
10582 #define   DKL_PLL_TDC_FEED_FWD_GAIN_MASK	(0xFF << 0)
10588 #define _DKL_REFCLKIN_CTL		0x12C
10595 #define _DKL_CLKTOP2_HSCLKCTL		0xD4
10602 #define _DKL_CLKTOP2_CORECLKCTL1		0xD8
10609 #define _DKL_TX_DPCNTL0				0x2C0
10611 #define  DKL_TX_PRESHOOT_COEFF_MASK			(0x1f << 13)
10613 #define  DKL_TX_DE_EMPAHSIS_COEFF_MASK		(0x1f << 8)
10614 #define  DKL_TX_VSWING_CONTROL(x)			((x) << 0)
10615 #define  DKL_TX_VSWING_CONTROL_MASK			(0x7 << 0)
10621 #define _DKL_TX_DPCNTL1				0x2C4
10628 #define _DKL_TX_DPCNTL2				0x2C8
10635 #define _DKL_TX_FW_CALIB				0x2F8
10642 #define _DKL_TX_PMD_LANE_SUS				0xD00
10648 #define _DKL_TX_DW17					0xDC4
10654 #define _DKL_TX_DW18					0xDC8
10660 #define _DKL_DP_MODE					0xA0
10666 #define _DKL_CMN_UC_DW27			0x36C
10667 #define  DKL_CMN_UC_DW27_UC_HEALTH		(0x1 << 15)
10679 #define _HIP_INDEX_REG0			0x1010A0
10680 #define _HIP_INDEX_REG1			0x1010A4
10687 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
10689 #define   BXT_DE_PLL_RATIO_MASK		0xff
10691 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
10695 #define   CNL_CDCLK_PLL_RATIO_MASK	0xff
10698 #define DC_STATE_EN			_MMIO(0x45504)
10699 #define  DC_STATE_DISABLE		0
10702 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
10704 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
10705 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
10707 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
10708 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
10711 #define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
10712 #define  BXT_REQ_DATA_MASK			0x3F
10714 #define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
10717 #define BXT_D_CR_DRP0_DUNIT8			0x1000
10718 #define BXT_D_CR_DRP0_DUNIT9			0x1200
10724 #define  BXT_DRAM_RANK_MASK			0x3
10725 #define  BXT_DRAM_RANK_SINGLE			0x1
10726 #define  BXT_DRAM_RANK_DUAL			0x3
10727 #define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
10729 #define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
10730 #define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
10731 #define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
10732 #define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
10733 #define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
10735 #define  BXT_DRAM_SIZE_4GBIT			(0x0 << 6)
10736 #define  BXT_DRAM_SIZE_6GBIT			(0x1 << 6)
10737 #define  BXT_DRAM_SIZE_8GBIT			(0x2 << 6)
10738 #define  BXT_DRAM_SIZE_12GBIT			(0x3 << 6)
10739 #define  BXT_DRAM_SIZE_16GBIT			(0x4 << 6)
10740 #define  BXT_DRAM_TYPE_MASK			(0x7 << 22)
10742 #define  BXT_DRAM_TYPE_DDR3			(0x0 << 22)
10743 #define  BXT_DRAM_TYPE_LPDDR3			(0x1 << 22)
10744 #define  BXT_DRAM_TYPE_LPDDR4			(0x2 << 22)
10745 #define  BXT_DRAM_TYPE_DDR4			(0x4 << 22)
10748 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
10749 #define  SKL_REQ_DATA_MASK			(0xF << 0)
10751 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
10752 #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
10753 #define  SKL_DRAM_DDR_TYPE_DDR4			(0 << 0)
10754 #define  SKL_DRAM_DDR_TYPE_DDR3			(1 << 0)
10755 #define  SKL_DRAM_DDR_TYPE_LPDDR3		(2 << 0)
10756 #define  SKL_DRAM_DDR_TYPE_LPDDR4		(3 << 0)
10758 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
10759 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
10761 #define  SKL_DRAM_SIZE_MASK			0x3F
10762 #define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
10764 #define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
10765 #define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
10766 #define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
10767 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
10769 #define  SKL_DRAM_RANK_1			(0x0 << 10)
10770 #define  SKL_DRAM_RANK_2			(0x1 << 10)
10771 #define  SKL_DRAM_RANK_MASK			(0x1 << 10)
10772 #define  CNL_DRAM_SIZE_MASK			0x7F
10773 #define  CNL_DRAM_WIDTH_MASK			(0x3 << 7)
10775 #define  CNL_DRAM_WIDTH_X8			(0x0 << 7)
10776 #define  CNL_DRAM_WIDTH_X16			(0x1 << 7)
10777 #define  CNL_DRAM_WIDTH_X32			(0x2 << 7)
10778 #define  CNL_DRAM_RANK_MASK			(0x3 << 9)
10780 #define  CNL_DRAM_RANK_1			(0x0 << 9)
10781 #define  CNL_DRAM_RANK_2			(0x1 << 9)
10782 #define  CNL_DRAM_RANK_3			(0x2 << 9)
10783 #define  CNL_DRAM_RANK_4			(0x3 << 9)
10787 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
10788 #define D_COMP_BDW			_MMIO(0x138144)
10791 #define  D_COMP_COMP_DISABLE		(1 << 0)
10794 #define _WM_LINETIME_A		0x45270
10795 #define _WM_LINETIME_B		0x45274
10797 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
10803 #define SFUSE_STRAP			_MMIO(0xc2014)
10811 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
10813 #define WM_MISC				_MMIO(0x45260)
10814 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
10816 #define WM_DBG				_MMIO(0x45280)
10817 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
10822 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
10823 #define _PIPE_A_CSC_COEFF_BY	0x49014
10824 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
10825 #define _PIPE_A_CSC_COEFF_BU	0x4901c
10826 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
10827 #define _PIPE_A_CSC_COEFF_BV	0x49024
10829 #define _PIPE_A_CSC_MODE	0x49028
10834 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
10836 #define _PIPE_A_CSC_PREOFF_HI	0x49030
10837 #define _PIPE_A_CSC_PREOFF_ME	0x49034
10838 #define _PIPE_A_CSC_PREOFF_LO	0x49038
10839 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
10840 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
10841 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
10843 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
10844 #define _PIPE_B_CSC_COEFF_BY	0x49114
10845 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
10846 #define _PIPE_B_CSC_COEFF_BU	0x4911c
10847 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
10848 #define _PIPE_B_CSC_COEFF_BV	0x49124
10849 #define _PIPE_B_CSC_MODE	0x49128
10850 #define _PIPE_B_CSC_PREOFF_HI	0x49130
10851 #define _PIPE_B_CSC_PREOFF_ME	0x49134
10852 #define _PIPE_B_CSC_PREOFF_LO	0x49138
10853 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
10854 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
10855 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
10872 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
10873 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
10874 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
10875 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
10876 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
10877 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
10878 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
10879 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
10880 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
10881 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
10882 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
10883 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
10885 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
10886 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
10887 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
10888 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
10889 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
10890 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
10891 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
10892 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
10893 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
10894 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
10895 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
10896 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
10936 #define _PAL_PREC_INDEX_A	0x4A400
10937 #define _PAL_PREC_INDEX_B	0x4AC00
10938 #define _PAL_PREC_INDEX_C	0x4B400
10939 #define   PAL_PREC_10_12_BIT		(0 << 31)
10942 #define   PAL_PREC_INDEX_VALUE_MASK	(0x3ff << 0)
10943 #define   PAL_PREC_INDEX_VALUE(x)	((x) << 0)
10944 #define _PAL_PREC_DATA_A	0x4A404
10945 #define _PAL_PREC_DATA_B	0x4AC04
10946 #define _PAL_PREC_DATA_C	0x4B404
10947 #define _PAL_PREC_GC_MAX_A	0x4A410
10948 #define _PAL_PREC_GC_MAX_B	0x4AC10
10949 #define _PAL_PREC_GC_MAX_C	0x4B410
10952 #define   PREC_PAL_DATA_BLUE_MASK	REG_GENMASK(9, 0)
10953 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
10954 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
10955 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
10956 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
10957 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
10958 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
10966 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
10967 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
10968 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
10970 #define _PRE_CSC_GAMC_DATA_A	0x4A488
10971 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
10972 #define _PRE_CSC_GAMC_DATA_C	0x4B488
10978 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
10979 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
10981 #define  PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
10983 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
10984 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
10990 #define  PAL_PREC_MULTI_SEG_BLUE_UDW_MASK  REG_GENMASK(9, 0)
11000 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
11001 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
11002 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
11003 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
11004 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
11005 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
11006 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
11007 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
11010 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
11011 #define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
11013 #define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
11015 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
11016 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
11017 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
11018 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
11019 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
11020 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
11021 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
11022 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
11042 #define MIPIO_TXESC_CLK_DIV1			_MMIO(0x160004)
11043 #define  GLK_TX_ESC_CLK_DIV1_MASK			0x3FF
11044 #define MIPIO_TXESC_CLK_DIV2			_MMIO(0x160008)
11045 #define  GLK_TX_ESC_CLK_DIV2_MASK			0x3FF
11047 #define _ICL_DSI_ESC_CLK_DIV0		0x6b090
11048 #define _ICL_DSI_ESC_CLK_DIV1		0x6b890
11052 #define _ICL_DPHY_ESC_CLK_DIV0		0x162190
11053 #define _ICL_DPHY_ESC_CLK_DIV1		0x6C190
11057 #define  ICL_BYTE_CLK_PER_ESC_CLK_MASK		(0x1f << 16)
11059 #define  ICL_ESC_CLK_DIV_MASK			0x1ff
11060 #define  ICL_ESC_CLK_DIV_SHIFT			0
11063 #define _DSI_CMD_FRMCTL_0		0x6b034
11064 #define _DSI_CMD_FRMCTL_1		0x6b834
11071 #define   DSI_FRAME_IN_PROGRESS			(1 << 0)
11073 #define _DSI_INTR_MASK_REG_0		0x6b070
11074 #define _DSI_INTR_MASK_REG_1		0x6b870
11079 #define _DSI_INTR_IDENT_REG_0		0x6b074
11080 #define _DSI_INTR_IDENT_REG_1		0x6b874
11112 #define   DSI_SOT_ERROR				(1 << 0)
11115 #define GEN4_TIMESTAMP		_MMIO(0x2358)
11116 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
11117 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
11119 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
11120 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
11121 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
11123 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
11125 #define _PIPE_FRMTMSTMP_A		0x70048
11132 #define BXT_MIPI_CLOCK_CTL			_MMIO(0x46090)
11145 #define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(0x3F << 26)
11146 #define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(0x3F << 10)
11151 		(((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
11180 #define  BXT_MIPI2_RX_ESCLK_LOWER_SHIFT		0
11185 #define  BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK		(3 << 0)
11192 #define RX_DIVIDER_BIT_1_2                     0x3
11193 #define RX_DIVIDER_BIT_3_4                     0xC
11196 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
11197 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
11201 #define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
11202 #define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
11206 #define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
11207 #define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
11211 #define BXT_DSI_PLL_CTL			_MMIO(0x161000)
11215 #define  BXT_DSIC_16X_BY1		(0 << 10)
11220 #define  BXT_DSIA_16X_BY1		(0 << 8)
11226 #define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
11228 #define BXT_DSI_PLL_RATIO_MAX		0x7D
11229 #define BXT_DSI_PLL_RATIO_MIN		0x22
11230 #define GLK_DSI_PLL_RATIO_MAX		0x6F
11231 #define GLK_DSI_PLL_RATIO_MIN		0x22
11232 #define BXT_DSI_PLL_RATIO_MASK		0xFF
11235 #define BXT_DSI_PLL_ENABLE		_MMIO(0x46080)
11239 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
11240 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
11244 #define _BXT_MIPIA_PORT_CTRL				0x6B0C0
11245 #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
11249 #define _ICL_DSI_IO_MODECTL_0				0x6B094
11250 #define _ICL_DSI_IO_MODECTL_1				0x6B894
11254 #define  COMBO_PHY_MODE_DSI				(1 << 0)
11257 #define DSS_CTL1				_MMIO(0x67400)
11261 #define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
11262 #define  OVERLAP_PIXELS_MASK			(0xf << 16)
11264 #define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11265 #define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11266 #define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0
11268 #define DSS_CTL2				_MMIO(0x67404)
11271 #define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
11272 #define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
11274 #define _ICL_PIPE_DSS_CTL1_PB			0x78200
11275 #define _ICL_PIPE_DSS_CTL1_PC			0x78400
11283 #define _ICL_PIPE_DSS_CTL2_PB			0x78204
11284 #define _ICL_PIPE_DSS_CTL2_PC			0x78404
11289 #define BXT_P_DSI_REGULATOR_CFG			_MMIO(0x160020)
11290 #define  STAP_SELECT					(1 << 0)
11292 #define BXT_P_DSI_REGULATOR_TX_CTRL		_MMIO(0x160054)
11293 #define  HS_IO_CTRL_SELECT				(1 << 0)
11297 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
11300 #define  DUAL_LINK_MODE_FRONT_BACK			(0 << 26)
11306 #define  MIPIA_FLISDSI_DELAY_COUNT_MASK			(0xf << 18)
11312 #define  MIPIC_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 11)
11315 #define  CSB_20MHZ					(0 << 9)
11319 #define  BANDGAP_PNW_CIRCUIT				(0 << 8)
11326 #define  TEARING_EFFECT_OFF				(0 << 2)
11329 #define  LANE_CONFIGURATION_SHIFT			0
11330 #define  LANE_CONFIGURATION_MASK			(3 << 0)
11331 #define  LANE_CONFIGURATION_4LANE			(0 << 0)
11332 #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 << 0)
11333 #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 << 0)
11335 #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61194)
11336 #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE + 0x61704)
11338 #define  TEARING_EFFECT_DELAY_SHIFT			0
11339 #define  TEARING_EFFECT_DELAY_MASK			(0xffff << 0)
11342 #define _MIPIA_AUTOPWG			(VLV_DISPLAY_BASE + 0x611a0)
11346 #define _MIPIA_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb000)
11347 #define _MIPIC_DEVICE_READY		(dev_priv->mipi_mmio_base + 0xb800)
11353 #define  ULPS_STATE_NORMAL_OPERATION			(0 << 1)
11354 #define  DEVICE_READY					(1 << 0)
11356 #define _MIPIA_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb004)
11357 #define _MIPIC_INTR_STAT		(dev_priv->mipi_mmio_base + 0xb804)
11359 #define _MIPIA_INTR_EN			(dev_priv->mipi_mmio_base + 0xb008)
11360 #define _MIPIC_INTR_EN			(dev_priv->mipi_mmio_base + 0xb808)
11393 #define  RXSOT_ERROR					(1 << 0)
11395 #define _MIPIA_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb00c)
11396 #define _MIPIC_DSI_FUNC_PRG		(dev_priv->mipi_mmio_base + 0xb80c)
11399 #define  CMD_MODE_NOT_SUPPORTED				(0 << 13)
11405 #define  VID_MODE_FORMAT_MASK				(0xf << 7)
11406 #define  VID_MODE_NOT_SUPPORTED				(0 << 7)
11415 #define  DATA_LANES_PRG_REG_SHIFT			0
11416 #define  DATA_LANES_PRG_REG_MASK			(7 << 0)
11418 #define _MIPIA_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb010)
11419 #define _MIPIC_HS_TX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb810)
11421 #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK		0xffffff
11423 #define _MIPIA_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb014)
11424 #define _MIPIC_LP_RX_TIMEOUT		(dev_priv->mipi_mmio_base + 0xb814)
11426 #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK		0xffffff
11428 #define _MIPIA_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb018)
11429 #define _MIPIC_TURN_AROUND_TIMEOUT	(dev_priv->mipi_mmio_base + 0xb818)
11431 #define  TURN_AROUND_TIMEOUT_MASK			0x3f
11433 #define _MIPIA_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb01c)
11434 #define _MIPIC_DEVICE_RESET_TIMER	(dev_priv->mipi_mmio_base + 0xb81c)
11436 #define  DEVICE_RESET_TIMER_MASK			0xffff
11438 #define _MIPIA_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb020)
11439 #define _MIPIC_DPI_RESOLUTION		(dev_priv->mipi_mmio_base + 0xb820)
11442 #define  VERTICAL_ADDRESS_MASK				(0xffff << 16)
11443 #define  HORIZONTAL_ADDRESS_SHIFT			0
11444 #define  HORIZONTAL_ADDRESS_MASK			0xffff
11446 #define _MIPIA_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb024)
11447 #define _MIPIC_DBI_FIFO_THROTTLE	(dev_priv->mipi_mmio_base + 0xb824)
11449 #define  DBI_FIFO_EMPTY_HALF				(0 << 0)
11450 #define  DBI_FIFO_EMPTY_QUARTER				(1 << 0)
11451 #define  DBI_FIFO_EMPTY_7_LOCATIONS			(2 << 0)
11453 /* regs below are bits 15:0 */
11454 #define _MIPIA_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb028)
11455 #define _MIPIC_HSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb828)
11458 #define _MIPIA_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb02c)
11459 #define _MIPIC_HBP_COUNT		(dev_priv->mipi_mmio_base + 0xb82c)
11462 #define _MIPIA_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb030)
11463 #define _MIPIC_HFP_COUNT		(dev_priv->mipi_mmio_base + 0xb830)
11466 #define _MIPIA_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb034)
11467 #define _MIPIC_HACTIVE_AREA_COUNT	(dev_priv->mipi_mmio_base + 0xb834)
11470 #define _MIPIA_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb038)
11471 #define _MIPIC_VSYNC_PADDING_COUNT	(dev_priv->mipi_mmio_base + 0xb838)
11474 #define _MIPIA_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb03c)
11475 #define _MIPIC_VBP_COUNT		(dev_priv->mipi_mmio_base + 0xb83c)
11478 #define _MIPIA_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb040)
11479 #define _MIPIC_VFP_COUNT		(dev_priv->mipi_mmio_base + 0xb840)
11482 #define _MIPIA_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb044)
11483 #define _MIPIC_HIGH_LOW_SWITCH_COUNT	(dev_priv->mipi_mmio_base + 0xb844)
11486 /* regs above are bits 15:0 */
11488 #define _MIPIA_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb048)
11489 #define _MIPIC_DPI_CONTROL		(dev_priv->mipi_mmio_base + 0xb848)
11497 #define  SHUTDOWN					(1 << 0)
11499 #define _MIPIA_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb04c)
11500 #define _MIPIC_DPI_DATA			(dev_priv->mipi_mmio_base + 0xb84c)
11502 #define  COMMAND_BYTE_SHIFT				0
11503 #define  COMMAND_BYTE_MASK				(0x3f << 0)
11505 #define _MIPIA_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb050)
11506 #define _MIPIC_INIT_COUNT		(dev_priv->mipi_mmio_base + 0xb850)
11508 #define  MASTER_INIT_TIMER_SHIFT			0
11509 #define  MASTER_INIT_TIMER_MASK				(0xffff << 0)
11511 #define _MIPIA_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb054)
11512 #define _MIPIC_MAX_RETURN_PKT_SIZE	(dev_priv->mipi_mmio_base + 0xb854)
11515 #define  MAX_RETURN_PKT_SIZE_SHIFT			0
11516 #define  MAX_RETURN_PKT_SIZE_MASK			(0x3ff << 0)
11518 #define _MIPIA_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb058)
11519 #define _MIPIC_VIDEO_MODE_FORMAT	(dev_priv->mipi_mmio_base + 0xb858)
11524 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE		(1 << 0)
11525 #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS		(2 << 0)
11526 #define  VIDEO_MODE_BURST				(3 << 0)
11528 #define _MIPIA_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb05c)
11529 #define _MIPIC_EOT_DISABLE		(dev_priv->mipi_mmio_base + 0xb85c)
11540 #define  EOT_DISABLE					(1 << 0)
11542 #define _MIPIA_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb060)
11543 #define _MIPIC_LP_BYTECLK		(dev_priv->mipi_mmio_base + 0xb860)
11545 #define  LP_BYTECLK_SHIFT				0
11546 #define  LP_BYTECLK_MASK				(0xffff << 0)
11548 #define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
11549 #define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
11552 #define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
11553 #define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
11556 /* bits 31:0 */
11557 #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
11558 #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
11561 /* bits 31:0 */
11562 #define _MIPIA_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb068)
11563 #define _MIPIC_HS_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb868)
11566 #define _MIPIA_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb06c)
11567 #define _MIPIC_LP_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb86c)
11569 #define _MIPIA_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb070)
11570 #define _MIPIC_HS_GEN_CTRL		(dev_priv->mipi_mmio_base + 0xb870)
11573 #define  LONG_PACKET_WORD_COUNT_MASK			(0xffff << 8)
11575 #define  SHORT_PACKET_PARAM_MASK			(0xffff << 8)
11578 #define  DATA_TYPE_SHIFT				0
11579 #define  DATA_TYPE_MASK					(0x3f << 0)
11582 #define _MIPIA_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb074)
11583 #define _MIPIC_GEN_FIFO_STAT		(dev_priv->mipi_mmio_base + 0xb874)
11598 #define  HS_DATA_FIFO_FULL				(1 << 0)
11600 #define _MIPIA_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb078)
11601 #define _MIPIC_HS_LS_DBI_ENABLE		(dev_priv->mipi_mmio_base + 0xb878)
11603 #define  DBI_HS_LP_MODE_MASK				(1 << 0)
11604 #define  DBI_LP_MODE					(1 << 0)
11605 #define  DBI_HS_MODE					(0 << 0)
11607 #define _MIPIA_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb080)
11608 #define _MIPIC_DPHY_PARAM		(dev_priv->mipi_mmio_base + 0xb880)
11611 #define  EXIT_ZERO_COUNT_MASK				(0x3f << 24)
11613 #define  TRAIL_COUNT_MASK				(0x1f << 16)
11615 #define  CLK_ZERO_COUNT_MASK				(0xff << 8)
11616 #define  PREPARE_COUNT_SHIFT				0
11617 #define  PREPARE_COUNT_MASK				(0x3f << 0)
11619 #define _ICL_DSI_T_INIT_MASTER_0	0x6b088
11620 #define _ICL_DSI_T_INIT_MASTER_1	0x6b888
11625 #define _DPHY_CLK_TIMING_PARAM_0	0x162180
11626 #define _DPHY_CLK_TIMING_PARAM_1	0x6c180
11630 #define _DSI_CLK_TIMING_PARAM_0		0x6b080
11631 #define _DSI_CLK_TIMING_PARAM_1		0x6b880
11637 #define  CLK_PREPARE_MASK		(0x7 << 28)
11641 #define  CLK_ZERO_MASK			(0xf << 20)
11645 #define  CLK_PRE_MASK			(0x3 << 16)
11649 #define  CLK_POST_MASK			(0x7 << 8)
11652 #define  CLK_TRAIL(x)			((x) << 0)
11653 #define  CLK_TRAIL_MASK		(0xf << 0)
11654 #define  CLK_TRAIL_SHIFT		0
11656 #define _DPHY_DATA_TIMING_PARAM_0	0x162184
11657 #define _DPHY_DATA_TIMING_PARAM_1	0x6c184
11661 #define _DSI_DATA_TIMING_PARAM_0	0x6B084
11662 #define _DSI_DATA_TIMING_PARAM_1	0x6B884
11668 #define  HS_PREPARE_MASK		(0x7 << 24)
11672 #define  HS_ZERO_MASK			(0xf << 16)
11676 #define  HS_TRAIL_MASK			(0x7 << 8)
11679 #define  HS_EXIT(x)			((x) << 0)
11680 #define  HS_EXIT_MASK			(0x7 << 0)
11681 #define  HS_EXIT_SHIFT			0
11683 #define _DPHY_TA_TIMING_PARAM_0		0x162188
11684 #define _DPHY_TA_TIMING_PARAM_1		0x6c188
11688 #define _DSI_TA_TIMING_PARAM_0		0x6b098
11689 #define _DSI_TA_TIMING_PARAM_1		0x6b898
11695 #define  TA_SURE_MASK			(0x1f << 16)
11699 #define  TA_GO_MASK			(0xf << 8)
11702 #define  TA_GET(x)			((x) << 0)
11703 #define  TA_GET_MASK			(0xf << 0)
11704 #define  TA_GET_SHIFT			0
11707 #define _DSI_TRANS_FUNC_CONF_0		0x6b030
11708 #define _DSI_TRANS_FUNC_CONF_1		0x6b830
11712 #define  OP_MODE_MASK			(0x3 << 28)
11714 #define  CMD_MODE_NO_GATE		(0x0 << 28)
11715 #define  CMD_MODE_TE_GATE		(0x1 << 28)
11716 #define  VIDEO_MODE_SYNC_EVENT		(0x2 << 28)
11717 #define  VIDEO_MODE_SYNC_PULSE		(0x3 << 28)
11720 #define  PIX_FMT_MASK			(0x3 << 16)
11722 #define  PIX_FMT_RGB565			(0x0 << 16)
11723 #define  PIX_FMT_RGB666_PACKED		(0x1 << 16)
11724 #define  PIX_FMT_RGB666_LOOSE		(0x2 << 16)
11725 #define  PIX_FMT_RGB888			(0x3 << 16)
11726 #define  PIX_FMT_RGB101010		(0x4 << 16)
11727 #define  PIX_FMT_RGB121212		(0x5 << 16)
11728 #define  PIX_FMT_COMPRESSED		(0x6 << 16)
11731 #define  PIX_VIRT_CHAN_MASK		(0x3 << 12)
11733 #define  PIX_BUF_THRESHOLD_MASK		(0x3 << 10)
11735 #define  PIX_BUF_THRESHOLD_1_4		(0x0 << 10)
11736 #define  PIX_BUF_THRESHOLD_1_2		(0x1 << 10)
11737 #define  PIX_BUF_THRESHOLD_3_4		(0x2 << 10)
11738 #define  PIX_BUF_THRESHOLD_FULL		(0x3 << 10)
11739 #define  CONTINUOUS_CLK_MASK		(0x3 << 8)
11741 #define  CLK_ENTER_LP_AFTER_DATA	(0x0 << 8)
11742 #define  CLK_HS_OR_LP			(0x2 << 8)
11743 #define  CLK_HS_CONTINUOUS		(0x3 << 8)
11744 #define  LINK_CALIBRATION_MASK		(0x3 << 4)
11746 #define  CALIBRATION_DISABLED		(0x0 << 4)
11747 #define  CALIBRATION_ENABLED_INITIAL_ONLY	(0x2 << 4)
11748 #define  CALIBRATION_ENABLED_INITIAL_PERIODIC	(0x3 << 4)
11751 #define  EOTP_DISABLED			(1 << 0)
11753 #define _DSI_CMD_RXCTL_0		0x6b0d4
11754 #define _DSI_CMD_RXCTL_1		0x6b8d4
11765 #define  NUMBER_RX_PLOAD_DW_MASK	(0xff << 0)
11766 #define  NUMBER_RX_PLOAD_DW_SHIFT	0
11768 #define _DSI_CMD_TXCTL_0		0x6b0d0
11769 #define _DSI_CMD_TXCTL_1		0x6b8d0
11774 #define  FREE_HEADER_CREDIT_MASK	(0x1f << 8)
11775 #define  FREE_HEADER_CREDIT_SHIFT	0x8
11776 #define  FREE_PLOAD_CREDIT_MASK		(0xff << 0)
11777 #define  FREE_PLOAD_CREDIT_SHIFT	0
11778 #define  MAX_HEADER_CREDIT		0x10
11779 #define  MAX_PLOAD_CREDIT		0x40
11781 #define _DSI_CMD_TXHDR_0		0x6b100
11782 #define _DSI_CMD_TXHDR_1		0x6b900
11789 #define  PARAM_WC_MASK			(0xffff << 8)
11792 #define  VC_MASK			(0x3 << 6)
11794 #define  DT_MASK			(0x3f << 0)
11795 #define  DT_SHIFT			0
11797 #define _DSI_CMD_TXPYLD_0		0x6b104
11798 #define _DSI_CMD_TXPYLD_1		0x6b904
11803 #define _DSI_LP_MSG_0			0x6b0d8
11804 #define _DSI_LP_MSG_1			0x6b8d8
11811 #define  LINK_ENTER_ULPS		(1 << 0)
11814 #define _DSI_HSTX_TO_0			0x6b044
11815 #define _DSI_HSTX_TO_1			0x6b844
11819 #define  HSTX_TIMEOUT_VALUE_MASK	(0xffff << 16)
11822 #define  HSTX_TIMED_OUT			(1 << 0)
11824 #define _DSI_LPRX_HOST_TO_0		0x6b048
11825 #define _DSI_LPRX_HOST_TO_1		0x6b848
11830 #define  LPRX_TIMEOUT_VALUE_MASK	(0xffff << 0)
11831 #define  LPRX_TIMEOUT_VALUE_SHIFT	0
11832 #define  LPRX_TIMEOUT_VALUE(x)		((x) << 0)
11834 #define _DSI_PWAIT_TO_0			0x6b040
11835 #define _DSI_PWAIT_TO_1			0x6b840
11839 #define  PRESET_TIMEOUT_VALUE_MASK	(0xffff << 16)
11842 #define  PRESPONSE_TIMEOUT_VALUE_MASK	(0xffff << 0)
11843 #define  PRESPONSE_TIMEOUT_VALUE_SHIFT	0
11844 #define  PRESPONSE_TIMEOUT_VALUE(x)	((x) << 0)
11846 #define _DSI_TA_TO_0			0x6b04c
11847 #define _DSI_TA_TO_1			0x6b84c
11852 #define  TA_TIMEOUT_VALUE_MASK		(0xffff << 0)
11853 #define  TA_TIMEOUT_VALUE_SHIFT		0
11854 #define  TA_TIMEOUT_VALUE(x)		((x) << 0)
11856 /* bits 31:0 */
11857 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
11858 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
11861 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb088)
11862 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT		(dev_priv->mipi_mmio_base + 0xb888)
11865 #define  LP_HS_SSW_CNT_MASK				(0xffff << 16)
11866 #define  HS_LP_PWR_SW_CNT_SHIFT				0
11867 #define  HS_LP_PWR_SW_CNT_MASK				(0xffff << 0)
11869 #define _MIPIA_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb08c)
11870 #define _MIPIC_STOP_STATE_STALL		(dev_priv->mipi_mmio_base + 0xb88c)
11872 #define  STOP_STATE_STALL_COUNTER_SHIFT			0
11873 #define  STOP_STATE_STALL_COUNTER_MASK			(0xff << 0)
11875 #define _MIPIA_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb090)
11876 #define _MIPIC_INTR_STAT_REG_1		(dev_priv->mipi_mmio_base + 0xb890)
11878 #define _MIPIA_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb094)
11879 #define _MIPIC_INTR_EN_REG_1		(dev_priv->mipi_mmio_base + 0xb894)
11881 #define  RX_CONTENTION_DETECTED				(1 << 0)
11884 #define MIPIA_DBI_TYPEC_CTRL		(dev_priv->mipi_mmio_base + 0xb100)
11890 #define  DBI_TYPEC_FREQ_MASK				(0xf << 24)
11892 #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT		0
11893 #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK		(0xff << 0)
11898 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
11899 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
11903 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
11908 #define  READ_REQUEST_PRIORITY_LOW			(0 << 3)
11924 #define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
11929 #define  GLK_MIPIIO_ENABLE				(1 << 0)
11931 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
11932 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
11935 #define  DATA_MEM_ADDRESS_MASK				(0x7ffffff << 5)
11936 #define  DATA_VALID					(1 << 0)
11938 #define _MIPIA_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb10c)
11939 #define _MIPIC_DATA_LENGTH		(dev_priv->mipi_mmio_base + 0xb90c)
11941 #define  DATA_LENGTH_SHIFT				0
11942 #define  DATA_LENGTH_MASK				(0xfffff << 0)
11944 #define _MIPIA_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb110)
11945 #define _MIPIC_COMMAND_ADDRESS		(dev_priv->mipi_mmio_base + 0xb910)
11948 #define  COMMAND_MEM_ADDRESS_MASK			(0x7ffffff << 5)
11951 #define  COMMAND_VALID					(1 << 0)
11953 #define _MIPIA_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb114)
11954 #define _MIPIC_COMMAND_LENGTH		(dev_priv->mipi_mmio_base + 0xb914)
11956 #define  COMMAND_LENGTH_SHIFT(n)			(8 * (n)) /* n: 0...3 */
11957 #define  COMMAND_LENGTH_MASK(n)				(0xff << (8 * (n)))
11959 #define _MIPIA_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb118)
11960 #define _MIPIC_READ_DATA_RETURN0	(dev_priv->mipi_mmio_base + 0xb918)
11961 … n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
11963 #define _MIPIA_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb138)
11964 #define _MIPIC_READ_DATA_VALID		(dev_priv->mipi_mmio_base + 0xb938)
11969 #define GEN9_LNCFCMOCS(i)	_MMIO(0xb020 + (i) * 4)	/* L3 Cache Control */
11971 #define __GEN9_RCS0_MOCS0	0xc800
11973 #define __GEN9_VCS0_MOCS0	0xc900
11975 #define __GEN9_VCS1_MOCS0	0xca00
11977 #define __GEN9_VECS0_MOCS0	0xcb00
11979 #define __GEN9_BCS0_MOCS0	0xcc00
11981 #define __GEN11_VCS2_MOCS0	0x10000
11984 #define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
11989 #define GEN12_GLOBAL_MOCS(i)	_MMIO(0x4000 + (i) * 4) /* Global MOCS regs */
11992 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
11993 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
11994 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
11995 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL  0x67F1427F /*    "        " */
11996 #define   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT  0x5FF101FF /*    "        " */
11998 #define MMCD_MISC_CTRL		_MMIO(0x4ddc) /* skl+ */
12002 #define _ICL_PHY_MISC_A		0x64C00
12003 #define _ICL_PHY_MISC_B		0x64C04
12010 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
12011 #define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
12012 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB	0x78270
12013 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB	0x78370
12014 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC	0x78470
12015 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC	0x78570
12029 #define  DSC_VER_MAJ			(0x1 << 0)
12031 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
12032 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
12033 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB	0x78274
12034 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB	0x78374
12035 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC	0x78474
12036 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC	0x78574
12043 #define  DSC_BPP(bpp)				((bpp) << 0)
12045 #define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
12046 #define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
12047 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB	0x78278
12048 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB	0x78378
12049 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC	0x78478
12050 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC	0x78578
12058 #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
12060 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
12061 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
12062 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB	0x7827C
12063 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB	0x7837C
12064 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC	0x7847C
12065 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC	0x7857C
12073 #define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
12075 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
12076 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
12077 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB	0x78280
12078 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB	0x78380
12079 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC	0x78480
12080 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC	0x78580
12088 #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
12090 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
12091 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
12092 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB	0x78284
12093 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB	0x78384
12094 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC	0x78484
12095 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC	0x78584
12103 #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
12105 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
12106 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
12107 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB	0x78288
12108 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB	0x78388
12109 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC	0x78488
12110 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC	0x78588
12120 #define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
12122 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
12123 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
12124 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB	0x7828C
12125 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB	0x7838C
12126 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC	0x7848C
12127 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC	0x7858C
12135 #define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
12137 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
12138 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
12139 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB	0x78290
12140 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB	0x78390
12141 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC	0x78490
12142 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC	0x78590
12150 #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
12152 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
12153 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
12154 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB	0x78294
12155 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB	0x78394
12156 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC	0x78494
12157 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC	0x78594
12165 #define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
12167 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
12168 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
12169 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB	0x78298
12170 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB	0x78398
12171 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC	0x78498
12172 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC	0x78598
12182 #define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
12184 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
12185 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
12186 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB	0x7829C
12187 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB	0x7839C
12188 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC	0x7849C
12189 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC	0x7859C
12197 #define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
12198 #define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
12199 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB	0x782A0
12200 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB	0x783A0
12201 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC	0x784A0
12202 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC	0x785A0
12210 #define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
12211 #define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
12212 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB	0x782A4
12213 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB	0x783A4
12214 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC	0x784A4
12215 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC	0x785A4
12223 #define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
12224 #define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
12225 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB	0x782A8
12226 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB	0x783A8
12227 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC	0x784A8
12228 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC	0x785A8
12236 #define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
12237 #define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
12238 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB	0x782AC
12239 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB	0x783AC
12240 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC	0x784AC
12241 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC	0x785AC
12249 #define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
12250 #define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
12251 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB	0x782B0
12252 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB	0x783B0
12253 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC	0x784B0
12254 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC	0x785B0
12263 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
12266 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
12267 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
12268 #define DSCC_RC_BUF_THRESH_0			_MMIO(0x6BA30)
12269 #define DSCC_RC_BUF_THRESH_0_UDW		_MMIO(0x6BA30 + 4)
12270 #define _ICL_DSC0_RC_BUF_THRESH_0_PB		(0x78254)
12271 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB	(0x78254 + 4)
12272 #define _ICL_DSC1_RC_BUF_THRESH_0_PB		(0x78354)
12273 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB	(0x78354 + 4)
12274 #define _ICL_DSC0_RC_BUF_THRESH_0_PC		(0x78454)
12275 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC	(0x78454 + 4)
12276 #define _ICL_DSC1_RC_BUF_THRESH_0_PC		(0x78554)
12277 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC	(0x78554 + 4)
12291 #define DSCA_RC_BUF_THRESH_1			_MMIO(0x6B238)
12292 #define DSCA_RC_BUF_THRESH_1_UDW		_MMIO(0x6B238 + 4)
12293 #define DSCC_RC_BUF_THRESH_1			_MMIO(0x6BA38)
12294 #define DSCC_RC_BUF_THRESH_1_UDW		_MMIO(0x6BA38 + 4)
12295 #define _ICL_DSC0_RC_BUF_THRESH_1_PB		(0x7825C)
12296 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB	(0x7825C + 4)
12297 #define _ICL_DSC1_RC_BUF_THRESH_1_PB		(0x7835C)
12298 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB	(0x7835C + 4)
12299 #define _ICL_DSC0_RC_BUF_THRESH_1_PC		(0x7845C)
12300 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC	(0x7845C + 4)
12301 #define _ICL_DSC1_RC_BUF_THRESH_1_PC		(0x7855C)
12302 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC	(0x7855C + 4)
12316 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
12321 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
12324 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
12327 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
12330 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
12332 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
12336 #define _DSBSL_INSTANCE_BASE		0x70B00
12338 					 (pipe) * 0x1000 + (id) * 0x100)
12339 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
12340 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
12341 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
12343 #define   DSB_STATUS			(1 << 0)
12345 #define TGL_ROOT_DEVICE_ID		0x9A00
12346 #define TGL_ROOT_DEVICE_MASK		0xFF00
12347 #define TGL_ROOT_DEVICE_SKU_MASK	0xF
12348 #define TGL_ROOT_DEVICE_SKU_ULX		0x2
12349 #define TGL_ROOT_DEVICE_SKU_ULT		0x4