2091 #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \  argument
2102 #define MG_TX1_LINK_PARAMS(ln, tc_port) \  argument
2115 #define MG_TX2_LINK_PARAMS(ln, tc_port) \  argument
2129 #define MG_TX1_PISO_READLOAD(ln, tc_port) \  argument
2142 #define MG_TX2_PISO_READLOAD(ln, tc_port) \  argument
2156 #define MG_TX1_SWINGCTRL(ln, tc_port) \  argument
2169 #define MG_TX2_SWINGCTRL(ln, tc_port) \  argument
2184 #define MG_TX1_DRVCTRL(ln, tc_port) \  argument
2197 #define MG_TX2_DRVCTRL(ln, tc_port) \  argument
2217 #define MG_CLKHUB(ln, tc_port) \  argument
2231 #define MG_TX1_DCC(ln, tc_port) \  argument
2243 #define MG_TX2_DCC(ln, tc_port) \  argument
2259 #define MG_DP_MODE(ln, tc_port)	\  argument
7764 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))  argument
7771 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))  argument
7781 #define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)  argument
7782 #define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)  argument
7783 #define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)  argument
7784 #define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)  argument
8213 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))  argument
8305 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)  argument
8414 #define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)  argument
8415 #define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)  argument
10279 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \  argument
10307 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \  argument
10316 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \  argument
10328 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \  argument
10348 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \  argument
10362 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \  argument
10377 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \  argument
10390 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \  argument
10403 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \  argument
10417 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \  argument
10437 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \  argument
10449 #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \  argument
10544 #define DKL_PLL_DIV0(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10553 #define DKL_PLL_DIV1(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10565 #define DKL_PLL_SSC(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10574 #define DKL_PLL_BIAS(tc_port)		_MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \  argument
10583 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \  argument
10590 #define DKL_REFCLKIN_CTL(tc_port)	_MMIO(_PORT(tc_port, \  argument
10597 #define DKL_CLKTOP2_HSCLKCTL(tc_port)	_MMIO(_PORT(tc_port, \  argument
10604 #define DKL_CLKTOP2_CORECLKCTL1(tc_port)	_MMIO(_PORT(tc_port, \  argument
10616 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \  argument
10623 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \  argument
10630 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \  argument
10637 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \  argument
10643 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \  argument
10649 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \  argument
10655 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \  argument
10661 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \  argument
10668 #define DKL_CMN_UC_DW_27(tc_port)		_MMIO(_PORT(tc_port, \  argument
10681 #define HIP_INDEX_REG(tc_port)		_MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \  argument
10683 #define _HIP_INDEX_SHIFT(tc_port)	(8 * ((tc_port) % 4))  argument
10684 #define HIP_INDEX_VAL(tc_port, val)	((val) << _HIP_INDEX_SHIFT(tc_port))  argument