203 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,  in gen3_irq_reset()  argument
206 	intel_uncore_write(uncore, imr, 0xffffffff);  in gen3_irq_reset()
207 	intel_uncore_posting_read(uncore, imr);  in gen3_irq_reset()
209 	intel_uncore_write(uncore, ier, 0);  in gen3_irq_reset()
212 	intel_uncore_write(uncore, iir, 0xffffffff);  in gen3_irq_reset()
213 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
214 	intel_uncore_write(uncore, iir, 0xffffffff);  in gen3_irq_reset()
215 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
218 void gen2_irq_reset(struct intel_uncore *uncore)  in gen2_irq_reset()  argument
220 	intel_uncore_write16(uncore, GEN2_IMR, 0xffff);  in gen2_irq_reset()
221 	intel_uncore_posting_read16(uncore, GEN2_IMR);  in gen2_irq_reset()
223 	intel_uncore_write16(uncore, GEN2_IER, 0);  in gen2_irq_reset()
226 	intel_uncore_write16(uncore, GEN2_IIR, 0xffff);  in gen2_irq_reset()
227 	intel_uncore_posting_read16(uncore, GEN2_IIR);  in gen2_irq_reset()
228 	intel_uncore_write16(uncore, GEN2_IIR, 0xffff);  in gen2_irq_reset()
229 	intel_uncore_posting_read16(uncore, GEN2_IIR);  in gen2_irq_reset()
235 static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)  in gen3_assert_iir_is_zero()  argument
237 	u32 val = intel_uncore_read(uncore, reg);  in gen3_assert_iir_is_zero()
242 	drm_WARN(&uncore->i915->drm, 1,  in gen3_assert_iir_is_zero()
245 	intel_uncore_write(uncore, reg, 0xffffffff);  in gen3_assert_iir_is_zero()
246 	intel_uncore_posting_read(uncore, reg);  in gen3_assert_iir_is_zero()
247 	intel_uncore_write(uncore, reg, 0xffffffff);  in gen3_assert_iir_is_zero()
248 	intel_uncore_posting_read(uncore, reg);  in gen3_assert_iir_is_zero()
251 static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)  in gen2_assert_iir_is_zero()  argument
253 	u16 val = intel_uncore_read16(uncore, GEN2_IIR);  in gen2_assert_iir_is_zero()
258 	drm_WARN(&uncore->i915->drm, 1,  in gen2_assert_iir_is_zero()
261 	intel_uncore_write16(uncore, GEN2_IIR, 0xffff);  in gen2_assert_iir_is_zero()
262 	intel_uncore_posting_read16(uncore, GEN2_IIR);  in gen2_assert_iir_is_zero()
263 	intel_uncore_write16(uncore, GEN2_IIR, 0xffff);  in gen2_assert_iir_is_zero()
264 	intel_uncore_posting_read16(uncore, GEN2_IIR);  in gen2_assert_iir_is_zero()
267 void gen3_irq_init(struct intel_uncore *uncore,  in gen3_irq_init()  argument
272 	gen3_assert_iir_is_zero(uncore, iir);  in gen3_irq_init()
274 	intel_uncore_write(uncore, ier, ier_val);  in gen3_irq_init()
275 	intel_uncore_write(uncore, imr, imr_val);  in gen3_irq_init()
276 	intel_uncore_posting_read(uncore, imr);  in gen3_irq_init()
279 void gen2_irq_init(struct intel_uncore *uncore,  in gen2_irq_init()  argument
282 	gen2_assert_iir_is_zero(uncore);  in gen2_irq_init()
284 	intel_uncore_write16(uncore, GEN2_IER, ier_val);  in gen2_irq_init()
285 	intel_uncore_write16(uncore, GEN2_IMR, imr_val);  in gen2_irq_init()
286 	intel_uncore_posting_read16(uncore, GEN2_IMR);  in gen2_irq_init()
655 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
668 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_vblank_counter()
847 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
902 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in i915_get_crtc_scanoutpos()
940 	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
942 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);  in intel_get_crtc_scanline()
2047 	void __iomem * const regs = i915->uncore.regs;  in ilk_irq_handler()
2398 	void __iomem * const regs = dev_priv->uncore.regs;  in gen8_irq_handler()
2428 	void __iomem * const regs = gt->uncore->regs;  in gen11_gu_misc_irq_ack()
2469 	void __iomem * const regs = i915->uncore.regs;  in gen11_display_irq_handler()
2490 	void __iomem * const regs = i915->uncore.regs;  in __gen11_irq_handler()
2715 	struct intel_uncore *uncore = &dev_priv->uncore;  in ibx_irq_reset()  local
2720 	GEN3_IRQ_RESET(uncore, SDE);  in ibx_irq_reset()
2746 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_reset()  local
2749 		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);  in vlv_display_irq_reset()
2751 		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);  in vlv_display_irq_reset()
2754 	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));  in vlv_display_irq_reset()
2758 	GEN3_IRQ_RESET(uncore, VLV_);  in vlv_display_irq_reset()
2764 	struct intel_uncore *uncore = &dev_priv->uncore;  in vlv_display_irq_postinstall()  local
2790 	GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);  in vlv_display_irq_postinstall()
2797 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_reset()  local
2799 	GEN3_IRQ_RESET(uncore, DE);  in ilk_irq_reset()
2801 		intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);  in ilk_irq_reset()
2804 		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);  in ilk_irq_reset()
2805 		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);  in ilk_irq_reset()
2828 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_reset()  local
2831 	gen8_master_intr_disable(dev_priv->uncore.regs);  in gen8_irq_reset()
2835 	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);  in gen8_irq_reset()
2836 	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);  in gen8_irq_reset()
2841 			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);  in gen8_irq_reset()
2843 	GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);  in gen8_irq_reset()
2844 	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);  in gen8_irq_reset()
2845 	GEN3_IRQ_RESET(uncore, GEN8_PCU_);  in gen8_irq_reset()
2853 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_display_irq_reset()  local
2858 	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);  in gen11_display_irq_reset()
2870 			intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);  in gen11_display_irq_reset()
2871 			intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);  in gen11_display_irq_reset()
2874 		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);  in gen11_display_irq_reset()
2875 		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);  in gen11_display_irq_reset()
2881 			GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);  in gen11_display_irq_reset()
2883 	GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);  in gen11_display_irq_reset()
2884 	GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);  in gen11_display_irq_reset()
2885 	GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);  in gen11_display_irq_reset()
2888 		GEN3_IRQ_RESET(uncore, SDE);  in gen11_display_irq_reset()
2892 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,  in gen11_display_irq_reset()
2894 		intel_uncore_rmw(uncore, SOUTH_CHICKEN1,  in gen11_display_irq_reset()
2901 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_irq_reset()  local
2904 		dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);  in gen11_irq_reset()
2906 		gen11_master_intr_disable(dev_priv->uncore.regs);  in gen11_irq_reset()
2911 	GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);  in gen11_irq_reset()
2912 	GEN3_IRQ_RESET(uncore, GEN8_PCU_);  in gen11_irq_reset()
2918 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_post_enable()  local
2931 		GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,  in gen8_irq_power_well_post_enable()
2941 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_irq_power_well_pre_disable()  local
2952 		GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);  in gen8_irq_power_well_pre_disable()
2962 	struct intel_uncore *uncore = &dev_priv->uncore;  in cherryview_irq_reset()  local
2969 	GEN3_IRQ_RESET(uncore, GEN8_PCU_);  in cherryview_irq_reset()
3281 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);  in ibx_irq_postinstall()
3293 	struct intel_uncore *uncore = &dev_priv->uncore;  in ilk_irq_postinstall()  local
3312 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);  in ilk_irq_postinstall()
3320 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,  in ilk_irq_postinstall()
3385 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen8_de_irq_postinstall()  local
3422 			gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));  in gen8_de_irq_postinstall()
3425 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);  in gen8_de_irq_postinstall()
3433 			GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,  in gen8_de_irq_postinstall()
3438 	GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);  in gen8_de_irq_postinstall()
3439 	GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);  in gen8_de_irq_postinstall()
3446 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,  in gen8_de_irq_postinstall()
3467 	gen8_master_intr_enable(dev_priv->uncore.regs);  in gen8_irq_postinstall()
3478 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);  in icp_irq_postinstall()
3497 	struct intel_uncore *uncore = &dev_priv->uncore;  in gen11_irq_postinstall()  local
3506 	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);  in gen11_irq_postinstall()
3511 		dg1_master_intr_enable(uncore->regs);  in gen11_irq_postinstall()
3514 		gen11_master_intr_enable(uncore->regs);  in gen11_irq_postinstall()
3534 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_reset()  local
3538 	GEN2_IRQ_RESET(uncore);  in i8xx_irq_reset()
3543 	struct intel_uncore *uncore = &dev_priv->uncore;  in i8xx_irq_postinstall()  local
3546 	intel_uncore_write16(uncore,  in i8xx_irq_postinstall()
3563 	GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);  in i8xx_irq_postinstall()
3576 	struct intel_uncore *uncore = &i915->uncore;  in i8xx_error_irq_ack()  local
3579 	*eir = intel_uncore_read16(uncore, EIR);  in i8xx_error_irq_ack()
3582 		intel_uncore_write16(uncore, EIR, *eir);  in i8xx_error_irq_ack()
3584 	*eir_stuck = intel_uncore_read16(uncore, EIR);  in i8xx_error_irq_ack()
3598 	emr = intel_uncore_read16(uncore, EMR);  in i8xx_error_irq_ack()
3599 	intel_uncore_write16(uncore, EMR, 0xffff);  in i8xx_error_irq_ack()
3600 	intel_uncore_write16(uncore, EMR, emr | *eir_stuck);  in i8xx_error_irq_ack()
3667 		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);  in i8xx_irq_handler()
3680 		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);  in i8xx_irq_handler()
3698 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_reset()  local
3707 	GEN3_IRQ_RESET(uncore, GEN2_);  in i915_irq_reset()
3712 	struct intel_uncore *uncore = &dev_priv->uncore;  in i915_irq_postinstall()  local
3739 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i915_irq_postinstall()
3806 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_reset()  local
3813 	GEN3_IRQ_RESET(uncore, GEN2_);  in i965_irq_reset()
3818 	struct intel_uncore *uncore = &dev_priv->uncore;  in i965_irq_postinstall()  local
3856 	GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);  in i965_irq_postinstall()