Lines Matching refs:dev_priv
155 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) in intel_hpd_init_pins() argument
157 struct i915_hotplug *hpd = &dev_priv->hotplug; in intel_hpd_init_pins()
159 if (HAS_GMCH(dev_priv)) { in intel_hpd_init_pins()
160 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
161 IS_CHERRYVIEW(dev_priv)) in intel_hpd_init_pins()
168 if (INTEL_GEN(dev_priv) >= 11) in intel_hpd_init_pins()
170 else if (IS_GEN9_LP(dev_priv)) in intel_hpd_init_pins()
172 else if (INTEL_GEN(dev_priv) >= 8) in intel_hpd_init_pins()
174 else if (INTEL_GEN(dev_priv) >= 7) in intel_hpd_init_pins()
179 if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)) in intel_hpd_init_pins()
182 if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv) || in intel_hpd_init_pins()
183 HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv)) in intel_hpd_init_pins()
185 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) in intel_hpd_init_pins()
187 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) in intel_hpd_init_pins()
189 else if (HAS_PCH_IBX(dev_priv)) in intel_hpd_init_pins()
192 MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); in intel_hpd_init_pins()
196 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
198 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in intel_handle_vblank()
291 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update_locked() argument
297 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
298 drm_WARN_ON(&dev_priv->drm, bits & ~mask); in i915_hotplug_interrupt_update_locked()
318 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, in i915_hotplug_interrupt_update() argument
322 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
323 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); in i915_hotplug_interrupt_update()
324 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
333 void ilk_update_display_irq(struct drm_i915_private *dev_priv, in ilk_update_display_irq() argument
339 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
341 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ilk_update_display_irq()
343 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in ilk_update_display_irq()
346 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
350 if (new_val != dev_priv->irq_mask) { in ilk_update_display_irq()
351 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
352 I915_WRITE(DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
363 static void bdw_update_port_irq(struct drm_i915_private *dev_priv, in bdw_update_port_irq() argument
370 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_port_irq()
372 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_port_irq()
374 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
396 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, in bdw_update_pipe_irq() argument
403 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_pipe_irq()
405 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_pipe_irq()
407 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_pipe_irq()
410 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
414 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
415 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
416 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
427 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, in ibx_display_interrupt_update() argument
435 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ibx_display_interrupt_update()
437 lockdep_assert_held(&dev_priv->irq_lock); in ibx_display_interrupt_update()
439 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
446 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, in i915_pipestat_enable_mask() argument
449 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
452 lockdep_assert_held(&dev_priv->irq_lock); in i915_pipestat_enable_mask()
454 if (INTEL_GEN(dev_priv) < 5) in i915_pipestat_enable_mask()
461 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
468 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
481 drm_WARN_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
490 void i915_enable_pipestat(struct drm_i915_private *dev_priv, in i915_enable_pipestat() argument
496 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_enable_pipestat()
500 lockdep_assert_held(&dev_priv->irq_lock); in i915_enable_pipestat()
501 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
503 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
506 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
507 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_enable_pipestat()
513 void i915_disable_pipestat(struct drm_i915_private *dev_priv, in i915_disable_pipestat() argument
519 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_disable_pipestat()
523 lockdep_assert_held(&dev_priv->irq_lock); in i915_disable_pipestat()
524 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
526 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
529 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
530 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_disable_pipestat()
536 static bool i915_has_asle(struct drm_i915_private *dev_priv) in i915_has_asle() argument
538 if (!dev_priv->opregion.asle) in i915_has_asle()
541 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); in i915_has_asle()
548 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) in i915_enable_asle_pipestat() argument
550 if (!i915_has_asle(dev_priv)) in i915_enable_asle_pipestat()
553 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
555 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
556 if (INTEL_GEN(dev_priv) >= 4) in i915_enable_asle_pipestat()
557 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
560 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
618 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915_get_vblank_counter() local
619 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; in i915_get_vblank_counter()
655 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
663 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
664 low = intel_de_read_fw(dev_priv, low_frame); in i915_get_vblank_counter()
665 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
668 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
684 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in g4x_get_vblank_counter() local
700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in __intel_get_crtc_scanline_from_timestamp() local
722 scan_prev_time = intel_de_read_fw(dev_priv, in __intel_get_crtc_scanline_from_timestamp()
729 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); in __intel_get_crtc_scanline_from_timestamp()
731 scan_post_time = intel_de_read_fw(dev_priv, in __intel_get_crtc_scanline_from_timestamp()
750 struct drm_i915_private *dev_priv = to_i915(dev); in __intel_get_crtc_scanline() local
769 if (IS_GEN(dev_priv, 2)) in __intel_get_crtc_scanline()
770 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
772 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
786 if (HAS_DDI(dev_priv) && !position) { in __intel_get_crtc_scanline()
791 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
813 struct drm_i915_private *dev_priv = to_i915(dev); in i915_get_crtc_scanoutpos() local
819 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 || in i915_get_crtc_scanoutpos()
820 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) || in i915_get_crtc_scanoutpos()
823 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { in i915_get_crtc_scanoutpos()
824 drm_dbg(&dev_priv->drm, in i915_get_crtc_scanoutpos()
847 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
865 …position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIF… in i915_get_crtc_scanoutpos()
902 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
936 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_get_crtc_scanline() local
940 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
942 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
958 struct drm_i915_private *dev_priv = in ivb_parity_work() local
959 container_of(work, typeof(*dev_priv), l3_parity.error_work); in ivb_parity_work()
960 struct intel_gt *gt = &dev_priv->gt; in ivb_parity_work()
970 mutex_lock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
973 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
980 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivb_parity_work()
984 if (drm_WARN_ON_ONCE(&dev_priv->drm, in ivb_parity_work()
985 slice >= NUM_L3_SLICES(dev_priv))) in ivb_parity_work()
988 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivb_parity_work()
1007 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, in ivb_parity_work()
1022 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
1024 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv)); in ivb_parity_work()
1027 mutex_unlock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
1169 static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, in intel_get_hpd_pins() argument
1189 drm_dbg(&dev_priv->drm, in intel_get_hpd_pins()
1195 static void gmbus_irq_handler(struct drm_i915_private *dev_priv) in gmbus_irq_handler() argument
1197 wake_up_all(&dev_priv->gmbus_wait_queue); in gmbus_irq_handler()
1200 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv) in dp_aux_irq_handler() argument
1202 wake_up_all(&dev_priv->gmbus_wait_queue); in dp_aux_irq_handler()
1206 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in display_pipe_crc_irq_handler() argument
1212 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in display_pipe_crc_irq_handler()
1228 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
1241 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in display_pipe_crc_irq_handler() argument
1249 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in hsw_pipe_crc_irq_handler() argument
1252 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
1257 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in ivb_pipe_crc_irq_handler() argument
1260 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
1268 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, in i9xx_pipe_crc_irq_handler() argument
1273 if (INTEL_GEN(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
1278 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
1283 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
1290 static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) in i9xx_pipestat_irq_reset() argument
1294 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
1299 dev_priv->pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
1303 static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, in i9xx_pipestat_irq_ack() argument
1308 spin_lock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1310 if (!dev_priv->display_irqs_enabled) { in i9xx_pipestat_irq_ack()
1311 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1315 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
1343 status_mask |= dev_priv->pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
1350 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_pipestat_irq_ack()
1366 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1369 static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i8xx_pipestat_irq_handler() argument
1374 for_each_pipe(dev_priv, pipe) { in i8xx_pipestat_irq_handler()
1376 intel_handle_vblank(dev_priv, pipe); in i8xx_pipestat_irq_handler()
1379 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
1382 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
1386 static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i915_pipestat_irq_handler() argument
1392 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
1394 intel_handle_vblank(dev_priv, pipe); in i915_pipestat_irq_handler()
1400 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
1403 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
1407 intel_opregion_asle_intr(dev_priv); in i915_pipestat_irq_handler()
1410 static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, in i965_pipestat_irq_handler() argument
1416 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
1418 intel_handle_vblank(dev_priv, pipe); in i965_pipestat_irq_handler()
1424 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
1427 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
1431 intel_opregion_asle_intr(dev_priv); in i965_pipestat_irq_handler()
1434 gmbus_irq_handler(dev_priv); in i965_pipestat_irq_handler()
1437 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, in valleyview_pipestat_irq_handler() argument
1442 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1444 intel_handle_vblank(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1447 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1450 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1454 gmbus_irq_handler(dev_priv); in valleyview_pipestat_irq_handler()
1457 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) in i9xx_hpd_irq_ack() argument
1462 if (IS_G4X(dev_priv) || in i9xx_hpd_irq_ack()
1463 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1488 drm_WARN_ONCE(&dev_priv->drm, 1, in i9xx_hpd_irq_ack()
1495 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, in i9xx_hpd_irq_handler() argument
1501 if (IS_G4X(dev_priv) || in i9xx_hpd_irq_handler()
1502 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
1508 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1510 dev_priv->hotplug.hpd, in i9xx_hpd_irq_handler()
1513 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1516 if ((IS_G4X(dev_priv) || in i9xx_hpd_irq_handler()
1517 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
1519 dp_aux_irq_handler(dev_priv); in i9xx_hpd_irq_handler()
1524 struct drm_i915_private *dev_priv = arg; in valleyview_irq_handler() local
1527 if (!intel_irqs_enabled(dev_priv)) in valleyview_irq_handler()
1531 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1571 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in valleyview_irq_handler()
1575 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in valleyview_irq_handler()
1579 intel_lpe_audio_irq_handler(dev_priv); in valleyview_irq_handler()
1592 gen6_gt_irq_handler(&dev_priv->gt, gt_iir); in valleyview_irq_handler()
1594 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir); in valleyview_irq_handler()
1597 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in valleyview_irq_handler()
1599 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in valleyview_irq_handler()
1602 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1609 struct drm_i915_private *dev_priv = arg; in cherryview_irq_handler() local
1612 if (!intel_irqs_enabled(dev_priv)) in cherryview_irq_handler()
1616 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1649 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); in cherryview_irq_handler()
1652 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in cherryview_irq_handler()
1656 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in cherryview_irq_handler()
1661 intel_lpe_audio_irq_handler(dev_priv); in cherryview_irq_handler()
1674 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in cherryview_irq_handler()
1676 valleyview_pipestat_irq_handler(dev_priv, pipe_stats); in cherryview_irq_handler()
1679 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1684 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, in ibx_hpd_irq_handler() argument
1708 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in ibx_hpd_irq_handler()
1710 dev_priv->hotplug.pch_hpd, in ibx_hpd_irq_handler()
1713 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in ibx_hpd_irq_handler()
1716 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in ibx_irq_handler() argument
1721 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); in ibx_irq_handler()
1726 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", in ibx_irq_handler()
1731 dp_aux_irq_handler(dev_priv); in ibx_irq_handler()
1734 gmbus_irq_handler(dev_priv); in ibx_irq_handler()
1737 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); in ibx_irq_handler()
1740 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); in ibx_irq_handler()
1743 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in ibx_irq_handler()
1746 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1747 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
1753 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); in ibx_irq_handler()
1756 drm_dbg(&dev_priv->drm, in ibx_irq_handler()
1760 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
1763 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
1766 static void ivb_err_int_handler(struct drm_i915_private *dev_priv) in ivb_err_int_handler() argument
1772 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ivb_err_int_handler()
1774 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1776 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1779 if (IS_IVYBRIDGE(dev_priv)) in ivb_err_int_handler()
1780 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1782 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1789 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) in cpt_serr_int_handler() argument
1795 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in cpt_serr_int_handler()
1797 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
1799 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); in cpt_serr_int_handler()
1804 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in cpt_irq_handler() argument
1809 ibx_hpd_irq_handler(dev_priv, hotplug_trigger); in cpt_irq_handler()
1814 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", in cpt_irq_handler()
1819 dp_aux_irq_handler(dev_priv); in cpt_irq_handler()
1822 gmbus_irq_handler(dev_priv); in cpt_irq_handler()
1825 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); in cpt_irq_handler()
1828 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); in cpt_irq_handler()
1831 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
1832 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
1838 cpt_serr_int_handler(dev_priv); in cpt_irq_handler()
1841 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in icp_irq_handler() argument
1846 if (HAS_PCH_TGP(dev_priv)) { in icp_irq_handler()
1849 } else if (HAS_PCH_JSP(dev_priv)) { in icp_irq_handler()
1852 } else if (HAS_PCH_MCC(dev_priv)) { in icp_irq_handler()
1856 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv), in icp_irq_handler()
1858 INTEL_PCH_TYPE(dev_priv)); in icp_irq_handler()
1870 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in icp_irq_handler()
1872 dev_priv->hotplug.pch_hpd, in icp_irq_handler()
1882 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in icp_irq_handler()
1884 dev_priv->hotplug.pch_hpd, in icp_irq_handler()
1889 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in icp_irq_handler()
1892 gmbus_irq_handler(dev_priv); in icp_irq_handler()
1895 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) in spt_irq_handler() argument
1908 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in spt_irq_handler()
1910 dev_priv->hotplug.pch_hpd, in spt_irq_handler()
1920 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in spt_irq_handler()
1922 dev_priv->hotplug.pch_hpd, in spt_irq_handler()
1927 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in spt_irq_handler()
1930 gmbus_irq_handler(dev_priv); in spt_irq_handler()
1933 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, in ilk_hpd_irq_handler() argument
1941 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in ilk_hpd_irq_handler()
1943 dev_priv->hotplug.hpd, in ilk_hpd_irq_handler()
1946 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in ilk_hpd_irq_handler()
1949 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, in ilk_display_irq_handler() argument
1956 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); in ilk_display_irq_handler()
1959 dp_aux_irq_handler(dev_priv); in ilk_display_irq_handler()
1962 intel_opregion_asle_intr(dev_priv); in ilk_display_irq_handler()
1965 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ilk_display_irq_handler()
1967 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
1969 intel_handle_vblank(dev_priv, pipe); in ilk_display_irq_handler()
1972 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
1975 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
1982 if (HAS_PCH_CPT(dev_priv)) in ilk_display_irq_handler()
1983 cpt_irq_handler(dev_priv, pch_iir); in ilk_display_irq_handler()
1985 ibx_irq_handler(dev_priv, pch_iir); in ilk_display_irq_handler()
1991 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) in ilk_display_irq_handler()
1992 gen5_rps_irq_handler(&dev_priv->gt.rps); in ilk_display_irq_handler()
1995 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, in ivb_display_irq_handler() argument
2002 ilk_hpd_irq_handler(dev_priv, hotplug_trigger); in ivb_display_irq_handler()
2005 ivb_err_int_handler(dev_priv); in ivb_display_irq_handler()
2010 intel_psr_irq_handler(dev_priv, psr_iir); in ivb_display_irq_handler()
2015 dp_aux_irq_handler(dev_priv); in ivb_display_irq_handler()
2018 intel_opregion_asle_intr(dev_priv); in ivb_display_irq_handler()
2020 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2022 intel_handle_vblank(dev_priv, pipe); in ivb_display_irq_handler()
2026 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { in ivb_display_irq_handler()
2029 cpt_irq_handler(dev_priv, pch_iir); in ivb_display_irq_handler()
2112 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, in bxt_hpd_irq_handler() argument
2120 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in bxt_hpd_irq_handler()
2122 dev_priv->hotplug.hpd, in bxt_hpd_irq_handler()
2125 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in bxt_hpd_irq_handler()
2128 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) in gen11_hpd_irq_handler() argument
2140 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in gen11_hpd_irq_handler()
2142 dev_priv->hotplug.hpd, in gen11_hpd_irq_handler()
2152 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in gen11_hpd_irq_handler()
2154 dev_priv->hotplug.hpd, in gen11_hpd_irq_handler()
2159 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in gen11_hpd_irq_handler()
2161 drm_err(&dev_priv->drm, in gen11_hpd_irq_handler()
2165 static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) in gen8_de_port_aux_mask() argument
2169 if (INTEL_GEN(dev_priv) >= 12) in gen8_de_port_aux_mask()
2182 if (INTEL_GEN(dev_priv) >= 9) in gen8_de_port_aux_mask()
2187 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11)) in gen8_de_port_aux_mask()
2190 if (IS_GEN(dev_priv, 11)) in gen8_de_port_aux_mask()
2196 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) in gen8_de_pipe_fault_mask() argument
2198 if (IS_ROCKETLAKE(dev_priv)) in gen8_de_pipe_fault_mask()
2200 else if (INTEL_GEN(dev_priv) >= 11) in gen8_de_pipe_fault_mask()
2202 else if (INTEL_GEN(dev_priv) >= 9) in gen8_de_pipe_fault_mask()
2209 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) in gen8_de_misc_irq_handler() argument
2214 intel_opregion_asle_intr(dev_priv); in gen8_de_misc_irq_handler()
2222 if (INTEL_GEN(dev_priv) >= 12) in gen8_de_misc_irq_handler()
2223 iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder); in gen8_de_misc_irq_handler()
2233 intel_psr_irq_handler(dev_priv, psr_iir); in gen8_de_misc_irq_handler()
2237 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); in gen8_de_misc_irq_handler()
2241 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) in gen8_de_irq_handler() argument
2252 gen8_de_misc_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2254 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2259 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { in gen8_de_irq_handler()
2264 gen11_hpd_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2266 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2280 if (iir & gen8_de_port_aux_mask(dev_priv)) { in gen8_de_irq_handler()
2281 dp_aux_irq_handler(dev_priv); in gen8_de_irq_handler()
2285 if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_handler()
2288 bxt_hpd_irq_handler(dev_priv, tmp_mask); in gen8_de_irq_handler()
2291 } else if (IS_BROADWELL(dev_priv)) { in gen8_de_irq_handler()
2294 ilk_hpd_irq_handler(dev_priv, tmp_mask); in gen8_de_irq_handler()
2299 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { in gen8_de_irq_handler()
2300 gmbus_irq_handler(dev_priv); in gen8_de_irq_handler()
2305 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2309 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2313 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
2321 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2330 intel_handle_vblank(dev_priv, pipe); in gen8_de_irq_handler()
2333 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
2336 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
2338 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); in gen8_de_irq_handler()
2340 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2346 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && in gen8_de_irq_handler()
2358 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in gen8_de_irq_handler()
2359 icp_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2360 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) in gen8_de_irq_handler()
2361 spt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2363 cpt_irq_handler(dev_priv, iir); in gen8_de_irq_handler()
2369 drm_dbg(&dev_priv->drm, in gen8_de_irq_handler()
2397 struct drm_i915_private *dev_priv = arg; in gen8_irq_handler() local
2398 void __iomem * const regs = dev_priv->uncore.regs; in gen8_irq_handler()
2401 if (!intel_irqs_enabled(dev_priv)) in gen8_irq_handler()
2411 gen8_gt_irq_handler(&dev_priv->gt, master_ctl); in gen8_irq_handler()
2415 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2416 gen8_de_irq_handler(dev_priv, master_ctl); in gen8_irq_handler()
2417 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2572 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_enable_vblank() local
2576 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2577 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
2578 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2585 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_enable_vblank() local
2593 if (dev_priv->vblank_enabled++ == 0) in i915gm_enable_vblank()
2601 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_enable_vblank() local
2605 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2606 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
2608 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2615 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_enable_vblank() local
2618 u32 bit = INTEL_GEN(dev_priv) >= 7 ? in ilk_enable_vblank()
2621 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2622 ilk_enable_display_irq(dev_priv, bit); in ilk_enable_vblank()
2623 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2628 if (HAS_PSR(dev_priv)) in ilk_enable_vblank()
2636 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in bdw_enable_vblank() local
2640 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2641 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_enable_vblank()
2642 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2647 if (HAS_PSR(dev_priv)) in bdw_enable_vblank()
2658 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_disable_vblank() local
2662 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2663 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
2664 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2669 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_disable_vblank() local
2673 if (--dev_priv->vblank_enabled == 0) in i915gm_disable_vblank()
2679 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_disable_vblank() local
2683 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2684 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
2686 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2691 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_disable_vblank() local
2694 u32 bit = INTEL_GEN(dev_priv) >= 7 ? in ilk_disable_vblank()
2697 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2698 ilk_disable_display_irq(dev_priv, bit); in ilk_disable_vblank()
2699 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2704 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in bdw_disable_vblank() local
2708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
2709 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_disable_vblank()
2710 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
2713 static void ibx_irq_reset(struct drm_i915_private *dev_priv) in ibx_irq_reset() argument
2715 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_reset()
2717 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_reset()
2722 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
2734 static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv) in ibx_irq_pre_postinstall() argument
2736 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_pre_postinstall()
2739 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0); in ibx_irq_pre_postinstall()
2744 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) in vlv_display_irq_reset() argument
2746 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_reset()
2748 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_reset()
2753 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); in vlv_display_irq_reset()
2756 i9xx_pipestat_irq_reset(dev_priv); in vlv_display_irq_reset()
2759 dev_priv->irq_mask = ~0u; in vlv_display_irq_reset()
2762 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) in vlv_display_irq_postinstall() argument
2764 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_postinstall()
2772 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
2773 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
2774 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
2782 if (IS_CHERRYVIEW(dev_priv)) in vlv_display_irq_postinstall()
2786 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
2788 dev_priv->irq_mask = ~enable_mask; in vlv_display_irq_postinstall()
2790 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
2795 static void ilk_irq_reset(struct drm_i915_private *dev_priv) in ilk_irq_reset() argument
2797 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_reset()
2800 if (IS_GEN(dev_priv, 7)) in ilk_irq_reset()
2803 if (IS_HASWELL(dev_priv)) { in ilk_irq_reset()
2808 gen5_gt_irq_reset(&dev_priv->gt); in ilk_irq_reset()
2810 ibx_irq_reset(dev_priv); in ilk_irq_reset()
2813 static void valleyview_irq_reset(struct drm_i915_private *dev_priv) in valleyview_irq_reset() argument
2818 gen5_gt_irq_reset(&dev_priv->gt); in valleyview_irq_reset()
2820 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
2821 if (dev_priv->display_irqs_enabled) in valleyview_irq_reset()
2822 vlv_display_irq_reset(dev_priv); in valleyview_irq_reset()
2823 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
2826 static void gen8_irq_reset(struct drm_i915_private *dev_priv) in gen8_irq_reset() argument
2828 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_reset()
2831 gen8_master_intr_disable(dev_priv->uncore.regs); in gen8_irq_reset()
2833 gen8_gt_irq_reset(&dev_priv->gt); in gen8_irq_reset()
2838 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
2839 if (intel_display_power_is_enabled(dev_priv, in gen8_irq_reset()
2847 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_reset()
2848 ibx_irq_reset(dev_priv); in gen8_irq_reset()
2851 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) in gen11_display_irq_reset() argument
2853 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_display_irq_reset()
2860 if (INTEL_GEN(dev_priv) >= 12) { in gen11_display_irq_reset()
2863 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { in gen11_display_irq_reset()
2867 if (!intel_display_power_is_enabled(dev_priv, domain)) in gen11_display_irq_reset()
2878 for_each_pipe(dev_priv, pipe) in gen11_display_irq_reset()
2879 if (intel_display_power_is_enabled(dev_priv, in gen11_display_irq_reset()
2887 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in gen11_display_irq_reset()
2891 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) { in gen11_display_irq_reset()
2899 static void gen11_irq_reset(struct drm_i915_private *dev_priv) in gen11_irq_reset() argument
2901 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_reset()
2903 if (HAS_MASTER_UNIT_IRQ(dev_priv)) in gen11_irq_reset()
2904 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs); in gen11_irq_reset()
2906 gen11_master_intr_disable(dev_priv->uncore.regs); in gen11_irq_reset()
2908 gen11_gt_irq_reset(&dev_priv->gt); in gen11_irq_reset()
2909 gen11_display_irq_reset(dev_priv); in gen11_irq_reset()
2915 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_post_enable() argument
2918 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_post_enable()
2923 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
2925 if (!intel_irqs_enabled(dev_priv)) { in gen8_irq_power_well_post_enable()
2926 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
2930 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
2932 dev_priv->de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
2933 ~dev_priv->de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
2935 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
2938 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_pre_disable() argument
2941 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_pre_disable()
2944 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
2946 if (!intel_irqs_enabled(dev_priv)) { in gen8_irq_power_well_pre_disable()
2947 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
2951 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
2954 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
2957 intel_synchronize_irq(dev_priv); in gen8_irq_power_well_pre_disable()
2960 static void cherryview_irq_reset(struct drm_i915_private *dev_priv) in cherryview_irq_reset() argument
2962 struct intel_uncore *uncore = &dev_priv->uncore; in cherryview_irq_reset()
2967 gen8_gt_irq_reset(&dev_priv->gt); in cherryview_irq_reset()
2971 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
2972 if (dev_priv->display_irqs_enabled) in cherryview_irq_reset()
2973 vlv_display_irq_reset(dev_priv); in cherryview_irq_reset()
2974 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
2977 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, in intel_hpd_enabled_irqs() argument
2983 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_enabled_irqs()
2984 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) in intel_hpd_enabled_irqs()
2990 static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, in intel_hpd_hotplug_irqs() argument
2996 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_hotplug_irqs()
3002 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) in ibx_hpd_detection_setup() argument
3022 if (HAS_PCH_LPT_LP(dev_priv)) in ibx_hpd_detection_setup()
3027 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) in ibx_hpd_irq_setup() argument
3031 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in ibx_hpd_irq_setup()
3032 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in ibx_hpd_irq_setup()
3034 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in ibx_hpd_irq_setup()
3036 ibx_hpd_detection_setup(dev_priv); in ibx_hpd_irq_setup()
3039 static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv, in icp_ddi_hpd_detection_setup() argument
3049 static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv, in icp_tc_hpd_detection_setup() argument
3059 static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv, in icp_hpd_irq_setup() argument
3064 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in icp_hpd_irq_setup()
3065 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in icp_hpd_irq_setup()
3067 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP) in icp_hpd_irq_setup()
3070 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in icp_hpd_irq_setup()
3072 icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask); in icp_hpd_irq_setup()
3074 icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask); in icp_hpd_irq_setup()
3081 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv) in mcc_hpd_irq_setup() argument
3083 icp_hpd_irq_setup(dev_priv, in mcc_hpd_irq_setup()
3092 static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv) in jsp_hpd_irq_setup() argument
3094 icp_hpd_irq_setup(dev_priv, in jsp_hpd_irq_setup()
3098 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv) in gen11_hpd_detection_setup() argument
3121 static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) in gen11_hpd_irq_setup() argument
3126 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in gen11_hpd_irq_setup()
3127 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in gen11_hpd_irq_setup()
3135 gen11_hpd_detection_setup(dev_priv); in gen11_hpd_irq_setup()
3137 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP) in gen11_hpd_irq_setup()
3138 icp_hpd_irq_setup(dev_priv, in gen11_hpd_irq_setup()
3140 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in gen11_hpd_irq_setup()
3141 icp_hpd_irq_setup(dev_priv, in gen11_hpd_irq_setup()
3145 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) in spt_hpd_detection_setup() argument
3150 if (HAS_PCH_CNP(dev_priv)) { in spt_hpd_detection_setup()
3170 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) in spt_hpd_irq_setup() argument
3174 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in spt_hpd_irq_setup()
3177 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in spt_hpd_irq_setup()
3178 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd); in spt_hpd_irq_setup()
3180 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in spt_hpd_irq_setup()
3182 spt_hpd_detection_setup(dev_priv); in spt_hpd_irq_setup()
3185 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) in ilk_hpd_detection_setup() argument
3201 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) in ilk_hpd_irq_setup() argument
3205 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in ilk_hpd_irq_setup()
3206 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in ilk_hpd_irq_setup()
3208 if (INTEL_GEN(dev_priv) >= 8) in ilk_hpd_irq_setup()
3209 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3211 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); in ilk_hpd_irq_setup()
3213 ilk_hpd_detection_setup(dev_priv); in ilk_hpd_irq_setup()
3215 ibx_hpd_irq_setup(dev_priv); in ilk_hpd_irq_setup()
3218 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv, in __bxt_hpd_detection_setup() argument
3228 drm_dbg_kms(&dev_priv->drm, in __bxt_hpd_detection_setup()
3238 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A)) in __bxt_hpd_detection_setup()
3241 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B)) in __bxt_hpd_detection_setup()
3244 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C)) in __bxt_hpd_detection_setup()
3250 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) in bxt_hpd_detection_setup() argument
3252 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK); in bxt_hpd_detection_setup()
3255 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) in bxt_hpd_irq_setup() argument
3259 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd); in bxt_hpd_irq_setup()
3260 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd); in bxt_hpd_irq_setup()
3262 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); in bxt_hpd_irq_setup()
3264 __bxt_hpd_detection_setup(dev_priv, enabled_irqs); in bxt_hpd_irq_setup()
3267 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) in ibx_irq_postinstall() argument
3271 if (HAS_PCH_NOP(dev_priv)) in ibx_irq_postinstall()
3274 if (HAS_PCH_IBX(dev_priv)) in ibx_irq_postinstall()
3276 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
3281 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); in ibx_irq_postinstall()
3284 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || in ibx_irq_postinstall()
3285 HAS_PCH_LPT(dev_priv)) in ibx_irq_postinstall()
3286 ibx_hpd_detection_setup(dev_priv); in ibx_irq_postinstall()
3288 spt_hpd_detection_setup(dev_priv); in ibx_irq_postinstall()
3291 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) in ilk_irq_postinstall() argument
3293 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_postinstall()
3296 if (INTEL_GEN(dev_priv) >= 7) { in ilk_irq_postinstall()
3311 if (IS_HASWELL(dev_priv)) { in ilk_irq_postinstall()
3316 dev_priv->irq_mask = ~display_mask; in ilk_irq_postinstall()
3318 ibx_irq_pre_postinstall(dev_priv); in ilk_irq_postinstall()
3320 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, in ilk_irq_postinstall()
3323 gen5_gt_irq_postinstall(&dev_priv->gt); in ilk_irq_postinstall()
3325 ilk_hpd_detection_setup(dev_priv); in ilk_irq_postinstall()
3327 ibx_irq_postinstall(dev_priv); in ilk_irq_postinstall()
3329 if (IS_IRONLAKE_M(dev_priv)) { in ilk_irq_postinstall()
3335 spin_lock_irq(&dev_priv->irq_lock); in ilk_irq_postinstall()
3336 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT); in ilk_irq_postinstall()
3337 spin_unlock_irq(&dev_priv->irq_lock); in ilk_irq_postinstall()
3341 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_enable_display_irqs() argument
3343 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
3345 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
3348 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
3350 if (intel_irqs_enabled(dev_priv)) { in valleyview_enable_display_irqs()
3351 vlv_display_irq_reset(dev_priv); in valleyview_enable_display_irqs()
3352 vlv_display_irq_postinstall(dev_priv); in valleyview_enable_display_irqs()
3356 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_disable_display_irqs() argument
3358 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
3360 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
3363 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
3365 if (intel_irqs_enabled(dev_priv)) in valleyview_disable_display_irqs()
3366 vlv_display_irq_reset(dev_priv); in valleyview_disable_display_irqs()
3370 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) in valleyview_irq_postinstall() argument
3372 gen5_gt_irq_postinstall(&dev_priv->gt); in valleyview_irq_postinstall()
3374 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3375 if (dev_priv->display_irqs_enabled) in valleyview_irq_postinstall()
3376 vlv_display_irq_postinstall(dev_priv); in valleyview_irq_postinstall()
3377 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3383 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_de_irq_postinstall() argument
3385 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_de_irq_postinstall()
3387 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | in gen8_de_irq_postinstall()
3390 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); in gen8_de_irq_postinstall()
3397 if (INTEL_GEN(dev_priv) <= 10) in gen8_de_irq_postinstall()
3400 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
3407 if (IS_GEN9_LP(dev_priv)) in gen8_de_irq_postinstall()
3409 else if (IS_BROADWELL(dev_priv)) in gen8_de_irq_postinstall()
3412 if (INTEL_GEN(dev_priv) >= 12) { in gen8_de_irq_postinstall()
3415 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) { in gen8_de_irq_postinstall()
3419 if (!intel_display_power_is_enabled(dev_priv, domain)) in gen8_de_irq_postinstall()
3428 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
3429 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3431 if (intel_display_power_is_enabled(dev_priv, in gen8_de_irq_postinstall()
3434 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3441 if (INTEL_GEN(dev_priv) >= 11) { in gen8_de_irq_postinstall()
3448 gen11_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
3449 } else if (IS_GEN9_LP(dev_priv)) { in gen8_de_irq_postinstall()
3450 bxt_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
3451 } else if (IS_BROADWELL(dev_priv)) { in gen8_de_irq_postinstall()
3452 ilk_hpd_detection_setup(dev_priv); in gen8_de_irq_postinstall()
3456 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_irq_postinstall() argument
3458 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_postinstall()
3459 ibx_irq_pre_postinstall(dev_priv); in gen8_irq_postinstall()
3461 gen8_gt_irq_postinstall(&dev_priv->gt); in gen8_irq_postinstall()
3462 gen8_de_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3464 if (HAS_PCH_SPLIT(dev_priv)) in gen8_irq_postinstall()
3465 ibx_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3467 gen8_master_intr_enable(dev_priv->uncore.regs); in gen8_irq_postinstall()
3470 static void icp_irq_postinstall(struct drm_i915_private *dev_priv) in icp_irq_postinstall() argument
3474 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0); in icp_irq_postinstall()
3478 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR); in icp_irq_postinstall()
3481 if (HAS_PCH_TGP(dev_priv)) { in icp_irq_postinstall()
3482 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); in icp_irq_postinstall()
3483 icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK); in icp_irq_postinstall()
3484 } else if (HAS_PCH_JSP(dev_priv)) { in icp_irq_postinstall()
3485 icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK); in icp_irq_postinstall()
3486 } else if (HAS_PCH_MCC(dev_priv)) { in icp_irq_postinstall()
3487 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); in icp_irq_postinstall()
3488 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1)); in icp_irq_postinstall()
3490 icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK); in icp_irq_postinstall()
3491 icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK); in icp_irq_postinstall()
3495 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) in gen11_irq_postinstall() argument
3497 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_irq_postinstall()
3500 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in gen11_irq_postinstall()
3501 icp_irq_postinstall(dev_priv); in gen11_irq_postinstall()
3503 gen11_gt_irq_postinstall(&dev_priv->gt); in gen11_irq_postinstall()
3504 gen8_de_irq_postinstall(dev_priv); in gen11_irq_postinstall()
3510 if (HAS_MASTER_UNIT_IRQ(dev_priv)) { in gen11_irq_postinstall()
3519 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) in cherryview_irq_postinstall() argument
3521 gen8_gt_irq_postinstall(&dev_priv->gt); in cherryview_irq_postinstall()
3523 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3524 if (dev_priv->display_irqs_enabled) in cherryview_irq_postinstall()
3525 vlv_display_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
3526 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3532 static void i8xx_irq_reset(struct drm_i915_private *dev_priv) in i8xx_irq_reset() argument
3534 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_reset()
3536 i9xx_pipestat_irq_reset(dev_priv); in i8xx_irq_reset()
3541 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv) in i8xx_irq_postinstall() argument
3543 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_postinstall()
3552 dev_priv->irq_mask = in i8xx_irq_postinstall()
3563 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
3567 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3568 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3569 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3570 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3603 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, in i8xx_error_irq_handler() argument
3609 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", in i8xx_error_irq_handler()
3613 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, in i9xx_error_irq_ack() argument
3641 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, in i9xx_error_irq_handler() argument
3647 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", in i9xx_error_irq_handler()
3653 struct drm_i915_private *dev_priv = arg; in i8xx_irq_handler() local
3656 if (!intel_irqs_enabled(dev_priv)) in i8xx_irq_handler()
3660 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
3667 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
3675 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
3678 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i8xx_irq_handler()
3680 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
3683 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); in i8xx_irq_handler()
3686 i8xx_error_irq_handler(dev_priv, eir, eir_stuck); in i8xx_irq_handler()
3688 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i8xx_irq_handler()
3691 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
3696 static void i915_irq_reset(struct drm_i915_private *dev_priv) in i915_irq_reset() argument
3698 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_reset()
3700 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_reset()
3701 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i915_irq_reset()
3705 i9xx_pipestat_irq_reset(dev_priv); in i915_irq_reset()
3710 static void i915_irq_postinstall(struct drm_i915_private *dev_priv) in i915_irq_postinstall() argument
3712 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_postinstall()
3719 dev_priv->irq_mask = in i915_irq_postinstall()
3732 if (I915_HAS_HOTPLUG(dev_priv)) { in i915_irq_postinstall()
3736 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
3739 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
3743 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
3744 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3745 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3746 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
3748 i915_enable_asle_pipestat(dev_priv); in i915_irq_postinstall()
3753 struct drm_i915_private *dev_priv = arg; in i915_irq_handler() local
3756 if (!intel_irqs_enabled(dev_priv)) in i915_irq_handler()
3760 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
3774 if (I915_HAS_HOTPLUG(dev_priv) && in i915_irq_handler()
3776 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i915_irq_handler()
3780 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i915_irq_handler()
3783 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i915_irq_handler()
3788 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); in i915_irq_handler()
3791 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i915_irq_handler()
3794 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i915_irq_handler()
3796 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i915_irq_handler()
3799 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
3804 static void i965_irq_reset(struct drm_i915_private *dev_priv) in i965_irq_reset() argument
3806 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_reset()
3808 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); in i965_irq_reset()
3811 i9xx_pipestat_irq_reset(dev_priv); in i965_irq_reset()
3816 static void i965_irq_postinstall(struct drm_i915_private *dev_priv) in i965_irq_postinstall() argument
3818 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_postinstall()
3826 if (IS_G4X(dev_priv)) { in i965_irq_postinstall()
3838 dev_priv->irq_mask = in i965_irq_postinstall()
3853 if (IS_G4X(dev_priv)) in i965_irq_postinstall()
3856 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
3860 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
3861 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3862 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
3863 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
3864 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
3866 i915_enable_asle_pipestat(dev_priv); in i965_irq_postinstall()
3869 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) in i915_hpd_irq_setup() argument
3873 lockdep_assert_held(&dev_priv->irq_lock); in i915_hpd_irq_setup()
3877 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); in i915_hpd_irq_setup()
3882 if (IS_G4X(dev_priv)) in i915_hpd_irq_setup()
3887 i915_hotplug_interrupt_update_locked(dev_priv, in i915_hpd_irq_setup()
3896 struct drm_i915_private *dev_priv = arg; in i965_irq_handler() local
3899 if (!intel_irqs_enabled(dev_priv)) in i965_irq_handler()
3903 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
3918 hotplug_status = i9xx_hpd_irq_ack(dev_priv); in i965_irq_handler()
3922 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); in i965_irq_handler()
3925 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); in i965_irq_handler()
3930 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]); in i965_irq_handler()
3933 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]); in i965_irq_handler()
3936 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); in i965_irq_handler()
3939 i9xx_hpd_irq_handler(dev_priv, hotplug_status); in i965_irq_handler()
3941 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); in i965_irq_handler()
3944 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
3956 void intel_irq_init(struct drm_i915_private *dev_priv) in intel_irq_init() argument
3958 struct drm_device *dev = &dev_priv->drm; in intel_irq_init()
3961 intel_hpd_init_pins(dev_priv); in intel_irq_init()
3963 intel_hpd_init_work(dev_priv); in intel_irq_init()
3965 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); in intel_irq_init()
3967 dev_priv->l3_parity.remap_info[i] = NULL; in intel_irq_init()
3970 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11) in intel_irq_init()
3971 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16; in intel_irq_init()
3981 dev_priv->display_irqs_enabled = true; in intel_irq_init()
3982 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
3983 dev_priv->display_irqs_enabled = false; in intel_irq_init()
3985 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; in intel_irq_init()
3992 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); in intel_irq_init()
3994 if (HAS_GMCH(dev_priv)) { in intel_irq_init()
3995 if (I915_HAS_HOTPLUG(dev_priv)) in intel_irq_init()
3996 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
3998 if (HAS_PCH_JSP(dev_priv)) in intel_irq_init()
3999 dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup; in intel_irq_init()
4000 else if (HAS_PCH_MCC(dev_priv)) in intel_irq_init()
4001 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup; in intel_irq_init()
4002 else if (INTEL_GEN(dev_priv) >= 11) in intel_irq_init()
4003 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; in intel_irq_init()
4004 else if (IS_GEN9_LP(dev_priv)) in intel_irq_init()
4005 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; in intel_irq_init()
4006 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) in intel_irq_init()
4007 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; in intel_irq_init()
4009 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; in intel_irq_init()
4027 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) in intel_irq_handler() argument
4029 if (HAS_GMCH(dev_priv)) { in intel_irq_handler()
4030 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_handler()
4032 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
4034 else if (IS_GEN(dev_priv, 4)) in intel_irq_handler()
4036 else if (IS_GEN(dev_priv, 3)) in intel_irq_handler()
4041 if (HAS_MASTER_UNIT_IRQ(dev_priv)) in intel_irq_handler()
4043 if (INTEL_GEN(dev_priv) >= 11) in intel_irq_handler()
4045 else if (INTEL_GEN(dev_priv) >= 8) in intel_irq_handler()
4052 static void intel_irq_reset(struct drm_i915_private *dev_priv) in intel_irq_reset() argument
4054 if (HAS_GMCH(dev_priv)) { in intel_irq_reset()
4055 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_reset()
4056 cherryview_irq_reset(dev_priv); in intel_irq_reset()
4057 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
4058 valleyview_irq_reset(dev_priv); in intel_irq_reset()
4059 else if (IS_GEN(dev_priv, 4)) in intel_irq_reset()
4060 i965_irq_reset(dev_priv); in intel_irq_reset()
4061 else if (IS_GEN(dev_priv, 3)) in intel_irq_reset()
4062 i915_irq_reset(dev_priv); in intel_irq_reset()
4064 i8xx_irq_reset(dev_priv); in intel_irq_reset()
4066 if (INTEL_GEN(dev_priv) >= 11) in intel_irq_reset()
4067 gen11_irq_reset(dev_priv); in intel_irq_reset()
4068 else if (INTEL_GEN(dev_priv) >= 8) in intel_irq_reset()
4069 gen8_irq_reset(dev_priv); in intel_irq_reset()
4071 ilk_irq_reset(dev_priv); in intel_irq_reset()
4075 static void intel_irq_postinstall(struct drm_i915_private *dev_priv) in intel_irq_postinstall() argument
4077 if (HAS_GMCH(dev_priv)) { in intel_irq_postinstall()
4078 if (IS_CHERRYVIEW(dev_priv)) in intel_irq_postinstall()
4079 cherryview_irq_postinstall(dev_priv); in intel_irq_postinstall()
4080 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
4081 valleyview_irq_postinstall(dev_priv); in intel_irq_postinstall()
4082 else if (IS_GEN(dev_priv, 4)) in intel_irq_postinstall()
4083 i965_irq_postinstall(dev_priv); in intel_irq_postinstall()
4084 else if (IS_GEN(dev_priv, 3)) in intel_irq_postinstall()
4085 i915_irq_postinstall(dev_priv); in intel_irq_postinstall()
4087 i8xx_irq_postinstall(dev_priv); in intel_irq_postinstall()
4089 if (INTEL_GEN(dev_priv) >= 11) in intel_irq_postinstall()
4090 gen11_irq_postinstall(dev_priv); in intel_irq_postinstall()
4091 else if (INTEL_GEN(dev_priv) >= 8) in intel_irq_postinstall()
4092 gen8_irq_postinstall(dev_priv); in intel_irq_postinstall()
4094 ilk_irq_postinstall(dev_priv); in intel_irq_postinstall()
4109 int intel_irq_install(struct drm_i915_private *dev_priv) in intel_irq_install() argument
4111 int irq = dev_priv->drm.pdev->irq; in intel_irq_install()
4119 dev_priv->runtime_pm.irqs_enabled = true; in intel_irq_install()
4121 dev_priv->drm.irq_enabled = true; in intel_irq_install()
4123 intel_irq_reset(dev_priv); in intel_irq_install()
4125 ret = request_irq(irq, intel_irq_handler(dev_priv), in intel_irq_install()
4126 IRQF_SHARED, DRIVER_NAME, dev_priv); in intel_irq_install()
4128 dev_priv->drm.irq_enabled = false; in intel_irq_install()
4132 intel_irq_postinstall(dev_priv); in intel_irq_install()
4144 void intel_irq_uninstall(struct drm_i915_private *dev_priv) in intel_irq_uninstall() argument
4146 int irq = dev_priv->drm.pdev->irq; in intel_irq_uninstall()
4154 if (!dev_priv->drm.irq_enabled) in intel_irq_uninstall()
4157 dev_priv->drm.irq_enabled = false; in intel_irq_uninstall()
4159 intel_irq_reset(dev_priv); in intel_irq_uninstall()
4161 free_irq(irq, dev_priv); in intel_irq_uninstall()
4163 intel_hpd_cancel_work(dev_priv); in intel_irq_uninstall()
4164 dev_priv->runtime_pm.irqs_enabled = false; in intel_irq_uninstall()
4174 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_disable_interrupts() argument
4176 intel_irq_reset(dev_priv); in intel_runtime_pm_disable_interrupts()
4177 dev_priv->runtime_pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4178 intel_synchronize_irq(dev_priv); in intel_runtime_pm_disable_interrupts()
4188 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable_interrupts() argument
4190 dev_priv->runtime_pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4191 intel_irq_reset(dev_priv); in intel_runtime_pm_enable_interrupts()
4192 intel_irq_postinstall(dev_priv); in intel_runtime_pm_enable_interrupts()
4195 bool intel_irqs_enabled(struct drm_i915_private *dev_priv) in intel_irqs_enabled() argument
4201 return dev_priv->runtime_pm.irqs_enabled; in intel_irqs_enabled()