14 	struct drm_i915_private *i915 = to_i915(dev);  in i915_getparam_ioctl()  local
15 	const struct sseu_dev_info *sseu = &i915->gt.info.sseu;  in i915_getparam_ioctl()
27 		value = i915->drm.pdev->device;  in i915_getparam_ioctl()
30 		value = i915->drm.pdev->revision;  in i915_getparam_ioctl()
33 		value = i915->ggtt.num_fences;  in i915_getparam_ioctl()
36 		value = !!i915->overlay;  in i915_getparam_ioctl()
39 		value = !!intel_engine_lookup_user(i915,  in i915_getparam_ioctl()
43 		value = !!intel_engine_lookup_user(i915,  in i915_getparam_ioctl()
47 		value = !!intel_engine_lookup_user(i915,  in i915_getparam_ioctl()
51 		value = !!intel_engine_lookup_user(i915,  in i915_getparam_ioctl()
55 		value = HAS_LLC(i915);  in i915_getparam_ioctl()
58 		value = HAS_WT(i915);  in i915_getparam_ioctl()
61 		value = INTEL_PPGTT(i915);  in i915_getparam_ioctl()
64 		value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);  in i915_getparam_ioctl()
67 		value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);  in i915_getparam_ioctl()
70 		value = i915_cmd_parser_get_version(i915);  in i915_getparam_ioctl()
83 		value = i915->params.enable_hangcheck &&  in i915_getparam_ioctl()
84 			intel_has_gpu_reset(&i915->gt);  in i915_getparam_ioctl()
85 		if (value && intel_has_reset_engine(&i915->gt))  in i915_getparam_ioctl()
92 		value = HAS_POOLED_EU(i915);  in i915_getparam_ioctl()
98 		value = intel_huc_check_status(&i915->gt.uc.huc);  in i915_getparam_ioctl()
110 		value = i915->caps.scheduler;  in i915_getparam_ioctl()
144 		value = intel_engines_has_context_isolation(i915);  in i915_getparam_ioctl()
157 		value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;  in i915_getparam_ioctl()
160 		value = INTEL_INFO(i915)->has_coherent_ggtt;  in i915_getparam_ioctl()