196 	struct drm_i915_private *dev_priv;  member
263 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
265 	void (*set_cdclk)(struct drm_i915_private *dev_priv,
269 	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
305 	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
306 	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
532 	struct drm_i915_private *dev_priv;  member
1291 #define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)  argument
1292 #define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)  argument
1293 #define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)  argument
1295 #define INTEL_GEN(dev_priv)	(INTEL_INFO(dev_priv)->gen)  argument
1296 #define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)  argument
1299 #define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)  argument
1307 #define IS_GEN_RANGE(dev_priv, s, e) \  argument
1308 	(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1310 #define IS_GEN(dev_priv, n) \  argument
1312 	 INTEL_INFO(dev_priv)->gen == (n))
1314 #define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)  argument
1386 #define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)  argument
1387 #define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)  argument
1389 #define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)  argument
1390 #define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)  argument
1391 #define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)  argument
1392 #define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)  argument
1393 #define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)  argument
1394 #define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)  argument
1395 #define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)  argument
1396 #define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)  argument
1397 #define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)  argument
1398 #define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)  argument
1399 #define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)  argument
1400 #define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)  argument
1401 #define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))  argument
1402 #define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)  argument
1403 #define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)  argument
1404 #define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)  argument
1405 #define IS_IRONLAKE_M(dev_priv) \  argument
1406 	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1407 #define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)  argument
1408 #define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \  argument
1409 				 INTEL_INFO(dev_priv)->gt == 1)
1410 #define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)  argument
1411 #define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)  argument
1412 #define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)  argument
1413 #define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)  argument
1414 #define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)  argument
1415 #define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)  argument
1416 #define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)  argument
1417 #define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)  argument
1418 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)  argument
1419 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)  argument
1420 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)  argument
1421 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)  argument
1422 #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)  argument
1423 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)  argument
1424 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)  argument
1425 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)  argument
1426 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \  argument
1427 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1428 #define IS_BDW_ULT(dev_priv) \  argument
1429 	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1430 #define IS_BDW_ULX(dev_priv) \  argument
1431 	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1432 #define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \  argument
1433 				 INTEL_INFO(dev_priv)->gt == 3)
1434 #define IS_HSW_ULT(dev_priv) \  argument
1435 	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1436 #define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \  argument
1437 				 INTEL_INFO(dev_priv)->gt == 3)
1438 #define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \  argument
1439 				 INTEL_INFO(dev_priv)->gt == 1)
1441 #define IS_HSW_ULX(dev_priv) \  argument
1442 	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1443 #define IS_SKL_ULT(dev_priv) \  argument
1444 	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1445 #define IS_SKL_ULX(dev_priv) \  argument
1446 	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1447 #define IS_KBL_ULT(dev_priv) \  argument
1448 	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1449 #define IS_KBL_ULX(dev_priv) \  argument
1450 	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1451 #define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
1452 				 INTEL_INFO(dev_priv)->gt == 2)
1453 #define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
1454 				 INTEL_INFO(dev_priv)->gt == 3)
1455 #define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \  argument
1456 				 INTEL_INFO(dev_priv)->gt == 4)
1457 #define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \  argument
1458 				 INTEL_INFO(dev_priv)->gt == 2)
1459 #define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \  argument
1460 				 INTEL_INFO(dev_priv)->gt == 3)
1461 #define IS_CFL_ULT(dev_priv) \  argument
1462 	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
1463 #define IS_CFL_ULX(dev_priv) \  argument
1464 	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
1465 #define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \  argument
1466 				 INTEL_INFO(dev_priv)->gt == 2)
1467 #define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \  argument
1468 				 INTEL_INFO(dev_priv)->gt == 3)
1470 #define IS_CML_ULT(dev_priv) \  argument
1471 	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
1472 #define IS_CML_ULX(dev_priv) \  argument
1473 	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
1474 #define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \  argument
1475 				 INTEL_INFO(dev_priv)->gt == 2)
1477 #define IS_CNL_WITH_PORT_F(dev_priv) \  argument
1478 	IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
1479 #define IS_ICL_WITH_PORT_F(dev_priv) \  argument
1480 	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
1482 #define IS_TGL_U(dev_priv) \  argument
1483 	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)
1485 #define IS_TGL_Y(dev_priv) \  argument
1486 	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)
1505 #define IS_BXT_REVID(dev_priv, since, until) \  argument
1506 	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
1528 #define IS_KBL_GT_REVID(dev_priv, since, until) \  argument
1529 	(IS_KABYLAKE(dev_priv) && \
1530 	 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \
1531 	 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until)
1532 #define IS_KBL_DISP_REVID(dev_priv, since, until) \  argument
1533 	(IS_KABYLAKE(dev_priv) && \
1534 	 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \
1535 	 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until)
1542 #define IS_GLK_REVID(dev_priv, since, until) \  argument
1543 	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
1578 tgl_revids_get(struct drm_i915_private *dev_priv)  in tgl_revids_get()  argument
1580 	if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv))  in tgl_revids_get()
1615 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)  argument
1616 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))  argument
1617 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))  argument
1637 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)  argument
1639 #define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)  argument
1640 #define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)  argument
1641 #define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)  argument
1642 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)  argument
1643 #define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \  argument
1644 				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
1646 #define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)  argument
1648 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \  argument
1649 		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
1650 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \  argument
1651 		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
1652 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \  argument
1653 		(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
1655 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq)  argument
1657 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)  argument
1659 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)  argument
1660 #define HAS_PPGTT(dev_priv) \  argument
1661 	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
1662 #define HAS_FULL_PPGTT(dev_priv) \  argument
1663 	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
1665 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \  argument
1667 	((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
1670 #define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)  argument
1671 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \  argument
1672 		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
1675 #define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))  argument
1677 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\  argument
1678 	(IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
1681 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\  argument
1682 	(IS_CANNONLAKE(dev_priv) ||					\
1683 	 IS_SKL_GT3(dev_priv) ||					\
1684 	 IS_SKL_GT4(dev_priv))
1686 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)  argument
1687 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \  argument
1688 					IS_GEMINILAKE(dev_priv) || \
1689 					IS_KABYLAKE(dev_priv))
1694 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \  argument
1695 					 !(IS_I915G(dev_priv) || \
1696 					 IS_I915GM(dev_priv)))
1697 #define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)  argument
1698 #define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)  argument
1700 #define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)  argument
1701 #define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.has_fbc)  argument
1702 #define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)  argument
1704 #define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))  argument
1706 #define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)  argument
1708 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)  argument
1709 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)  argument
1710 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)  argument
1711 #define HAS_PSR_HW_TRACKING(dev_priv) \  argument
1712 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
1713 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (INTEL_GEN(dev_priv) >= 12)  argument
1714 #define HAS_TRANSCODER(dev_priv, trans)	 ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) …  argument
1716 #define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)  argument
1717 #define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)  argument
1718 #define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */  argument
1720 #define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)  argument
1722 #define HAS_CSR(dev_priv)	(INTEL_INFO(dev_priv)->display.has_csr)  argument
1724 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)  argument
1725 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)  argument
1727 #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)  argument
1732 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)  argument
1734 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)  argument
1736 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)  argument
1739 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)  argument
1741 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)  argument
1744 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)  argument
1745 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \  argument
1746 				 2 : HAS_L3_DPF(dev_priv))
1751 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))  argument
1753 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)  argument
1756 #define INTEL_DISPLAY_ENABLED(dev_priv) \  argument
1757 	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
1770 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)  in intel_scanout_needs_vtd_wa()  argument
1772 	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();  in intel_scanout_needs_vtd_wa()
1776 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)  in intel_ggtt_update_needs_vtd_wa()  argument
1778 	return IS_BROXTON(dev_priv) && intel_vtd_active();  in intel_ggtt_update_needs_vtd_wa()
1794 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
1795 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
1796 void i915_gem_init_early(struct drm_i915_private *dev_priv);
1797 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
1798 int i915_gem_freeze(struct drm_i915_private *dev_priv);
1799 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
1860 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
1879 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
1882 void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
1883 void i915_gem_driver_release(struct drm_i915_private *dev_priv);
1884 void i915_gem_suspend(struct drm_i915_private *dev_priv);
1885 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
1886 void i915_gem_resume(struct drm_i915_private *dev_priv);
1931 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
1943 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
1945 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
1951 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
1964 mkwrite_device_info(struct drm_i915_private *dev_priv)  in mkwrite_device_info()  argument
1966 	return (struct intel_device_info *)INTEL_INFO(dev_priv);  in mkwrite_device_info()
1975 #define I915_READ(reg__)	 __I915_REG_OP(read, dev_priv, (reg__))
1976 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
1978 #define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))
2006 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2007 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))