75 	void *p_data, unsigned int bytes)  in read_vreg()  argument
77 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);  in read_vreg()
81 	void *p_data, unsigned int bytes)  in write_vreg()  argument
83 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);  in write_vreg()
195 		unsigned int fence_num, void *p_data, unsigned int bytes)  in sanitize_fence_mmio_access()  argument
211 		memset(p_data, 0, bytes);  in sanitize_fence_mmio_access()
218 		unsigned int offset, void *p_data, unsigned int bytes)  in gamw_echo_dev_rw_ia_write()  argument
220 	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;  in gamw_echo_dev_rw_ia_write()
238 	write_vreg(vgpu, offset, p_data, bytes);  in gamw_echo_dev_rw_ia_write()
243 		void *p_data, unsigned int bytes)  in fence_mmio_read()  argument
248 			p_data, bytes);  in fence_mmio_read()
251 	read_vreg(vgpu, off, p_data, bytes);  in fence_mmio_read()
256 		void *p_data, unsigned int bytes)  in fence_mmio_write()  argument
262 	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);  in fence_mmio_write()
265 	write_vreg(vgpu, off, p_data, bytes);  in fence_mmio_write()
280 		unsigned int offset, void *p_data, unsigned int bytes)  in mul_force_wake_write()  argument
286 	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);  in mul_force_wake_write()
314 			    void *p_data, unsigned int bytes)  in gdrst_mmio_write()  argument
319 	write_vreg(vgpu, offset, p_data, bytes);  in gdrst_mmio_write()
363 		void *p_data, unsigned int bytes)  in gmbus_mmio_read()  argument
365 	return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);  in gmbus_mmio_read()
369 		void *p_data, unsigned int bytes)  in gmbus_mmio_write()  argument
371 	return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);  in gmbus_mmio_write()
375 		unsigned int offset, void *p_data, unsigned int bytes)  in pch_pp_control_mmio_write()  argument
377 	write_vreg(vgpu, offset, p_data, bytes);  in pch_pp_control_mmio_write()
393 		unsigned int offset, void *p_data, unsigned int bytes)  in transconf_mmio_write()  argument
395 	write_vreg(vgpu, offset, p_data, bytes);  in transconf_mmio_write()
405 		void *p_data, unsigned int bytes)  in lcpll_ctl_mmio_write()  argument
407 	write_vreg(vgpu, offset, p_data, bytes);  in lcpll_ctl_mmio_write()
423 		void *p_data, unsigned int bytes)  in dpy_reg_mmio_read()  argument
442 	read_vreg(vgpu, offset, p_data, bytes);  in dpy_reg_mmio_read()
447 		void *p_data, unsigned int bytes)  in pipeconf_mmio_write()  argument
451 	write_vreg(vgpu, offset, p_data, bytes);  in pipeconf_mmio_write()
520 	unsigned int offset, void *p_data, unsigned int bytes)  in force_nonpriv_write()  argument
522 	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);  in force_nonpriv_write()
537 		intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);  in force_nonpriv_write()
543 		void *p_data, unsigned int bytes)  in ddi_buf_ctl_mmio_write()  argument
545 	write_vreg(vgpu, offset, p_data, bytes);  in ddi_buf_ctl_mmio_write()
559 		unsigned int offset, void *p_data, unsigned int bytes)  in fdi_rx_iir_mmio_write()  argument
561 	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;  in fdi_rx_iir_mmio_write()
650 		unsigned int offset, void *p_data, unsigned int bytes)  in update_fdi_rx_iir_status()  argument
667 	write_vreg(vgpu, offset, p_data, bytes);  in update_fdi_rx_iir_status()
694 		void *p_data, unsigned int bytes)  in dp_tp_ctl_mmio_write()  argument
700 	write_vreg(vgpu, offset, p_data, bytes);  in dp_tp_ctl_mmio_write()
712 		unsigned int offset, void *p_data, unsigned int bytes)  in dp_tp_status_mmio_write()  argument
717 	reg_val = *((u32 *)p_data);  in dp_tp_status_mmio_write()
727 		unsigned int offset, void *p_data, unsigned int bytes)  in pch_adpa_mmio_write()  argument
731 	write_vreg(vgpu, offset, p_data, bytes);  in pch_adpa_mmio_write()
740 		unsigned int offset, void *p_data, unsigned int bytes)  in south_chicken2_mmio_write()  argument
744 	write_vreg(vgpu, offset, p_data, bytes);  in south_chicken2_mmio_write()
758 		void *p_data, unsigned int bytes)  in pri_surf_mmio_write()  argument
764 	write_vreg(vgpu, offset, p_data, bytes);  in pri_surf_mmio_write()
781 		void *p_data, unsigned int bytes)  in spr_surf_mmio_write()  argument
786 	write_vreg(vgpu, offset, p_data, bytes);  in spr_surf_mmio_write()
798 			       unsigned int offset, void *p_data,  in reg50080_mmio_write()  argument
806 	write_vreg(vgpu, offset, p_data, bytes);  in reg50080_mmio_write()
911 		unsigned int offset, void *p_data, unsigned int bytes)  in dp_aux_ch_ctl_mmio_write()  argument
925 	write_vreg(vgpu, offset, p_data, bytes);  in dp_aux_ch_ctl_mmio_write()
1073 	intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);  in dp_aux_ch_ctl_mmio_write()
1081 		void *p_data, unsigned int bytes)  in mbctl_write()  argument
1083 	*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);  in mbctl_write()
1084 	write_vreg(vgpu, offset, p_data, bytes);  in mbctl_write()
1089 		void *p_data, unsigned int bytes)  in vga_control_mmio_write()  argument
1093 	write_vreg(vgpu, offset, p_data, bytes);  in vga_control_mmio_write()
1143 		void *p_data, unsigned int bytes)  in sbi_data_mmio_read()  argument
1152 	read_vreg(vgpu, offset, p_data, bytes);  in sbi_data_mmio_read()
1157 		void *p_data, unsigned int bytes)  in sbi_ctl_mmio_write()  argument
1161 	write_vreg(vgpu, offset, p_data, bytes);  in sbi_ctl_mmio_write()
1187 		void *p_data, unsigned int bytes)  in pvinfo_mmio_read()  argument
1191 	read_vreg(vgpu, offset, p_data, bytes);  in pvinfo_mmio_read()
1213 				offset, bytes, *(u32 *)p_data);  in pvinfo_mmio_read()
1263 		void *p_data, unsigned int bytes)  in pvinfo_mmio_write()  argument
1265 	u32 data = *(u32 *)p_data;  in pvinfo_mmio_write()
1301 		write_vreg(vgpu, offset, p_data, bytes);  in pvinfo_mmio_write()
1307 		unsigned int offset, void *p_data, unsigned int bytes)  in pf_write()  argument
1310 	u32 val = *(u32 *)p_data;  in pf_write()
1321 	return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);  in pf_write()
1325 		unsigned int offset, void *p_data, unsigned int bytes)  in power_well_ctl_mmio_write()  argument
1327 	write_vreg(vgpu, offset, p_data, bytes);  in power_well_ctl_mmio_write()
1340 		unsigned int offset, void *p_data, unsigned int bytes)  in gen9_dbuf_ctl_mmio_write()  argument
1342 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_dbuf_ctl_mmio_write()
1353 	unsigned int offset, void *p_data, unsigned int bytes)  in fpga_dbg_mmio_write()  argument
1355 	write_vreg(vgpu, offset, p_data, bytes);  in fpga_dbg_mmio_write()
1363 		void *p_data, unsigned int bytes)  in dma_ctrl_write()  argument
1368 	write_vreg(vgpu, offset, p_data, bytes);  in dma_ctrl_write()
1382 		void *p_data, unsigned int bytes)  in gen9_trtte_write()  argument
1385 	u32 trtte = *(u32 *)p_data;  in gen9_trtte_write()
1393 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtte_write()
1399 		void *p_data, unsigned int bytes)  in gen9_trtt_chicken_write()  argument
1401 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtt_chicken_write()
1406 		void *p_data, unsigned int bytes)  in dpll_status_read()  argument
1424 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in dpll_status_read()
1428 		void *p_data, unsigned int bytes)  in mailbox_write()  argument
1430 	u32 value = *(u32 *)p_data;  in mailbox_write()
1486 		void *p_data, unsigned int bytes)  in hws_pga_write()  argument
1488 	u32 value = *(u32 *)p_data;  in hws_pga_write()
1517 		unsigned int offset, void *p_data, unsigned int bytes)  in skl_power_well_ctl_write()  argument
1519 	u32 v = *(u32 *)p_data;  in skl_power_well_ctl_write()
1532 		void *p_data, unsigned int bytes)  in skl_lcpll_write()  argument
1534 	u32 v = *(u32 *)p_data;  in skl_lcpll_write()
1546 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_de_pll_enable_write()  argument
1548 	u32 v = *(u32 *)p_data;  in bxt_de_pll_enable_write()
1559 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_port_pll_enable_write()  argument
1561 	u32 v = *(u32 *)p_data;  in bxt_port_pll_enable_write()
1572 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_phy_ctl_family_write()  argument
1574 	u32 v = *(u32 *)p_data;  in bxt_phy_ctl_family_write()
1593 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_port_tx_dw3_read()  argument
1601 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in bxt_port_tx_dw3_read()
1605 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_pcs_dw12_grp_write()  argument
1607 	u32 v = *(u32 *)p_data;  in bxt_pcs_dw12_grp_write()
1623 		unsigned int offset, void *p_data, unsigned int bytes)  in bxt_gt_disp_pwron_write()  argument
1625 	u32 v = *(u32 *)p_data;  in bxt_gt_disp_pwron_write()
1648 		unsigned int offset, void *p_data, unsigned int bytes)  in edp_psr_imr_iir_write()  argument
1665 			      void *p_data, unsigned int bytes)  in bxt_ppat_low_write()  argument
1683 			   unsigned int offset, void *p_data,  in guc_status_read()  argument
1687 	read_vreg(vgpu, offset, p_data, bytes);  in guc_status_read()
1693 		unsigned int offset, void *p_data, unsigned int bytes)  in mmio_read_from_hw()  argument
1716 	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);  in mmio_read_from_hw()
1720 		void *p_data, unsigned int bytes)  in elsp_mmio_write()  argument
1725 	u32 data = *(u32 *)p_data;  in elsp_mmio_write()
1747 		void *p_data, unsigned int bytes)  in ring_mode_mmio_write()  argument
1749 	u32 data = *(u32 *)p_data;  in ring_mode_mmio_write()
1755 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);  in ring_mode_mmio_write()
1758 		(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);  in ring_mode_mmio_write()
1759 	write_vreg(vgpu, offset, p_data, bytes);  in ring_mode_mmio_write()
1806 		unsigned int offset, void *p_data, unsigned int bytes)  in gvt_reg_tlb_control_handler()  argument
1810 	write_vreg(vgpu, offset, p_data, bytes);  in gvt_reg_tlb_control_handler()
1838 	unsigned int offset, void *p_data, unsigned int bytes)  in ring_reset_ctl_write()  argument
1842 	write_vreg(vgpu, offset, p_data, bytes);  in ring_reset_ctl_write()
1855 				    unsigned int offset, void *p_data,  in csfe_chicken1_mmio_write()  argument
1858 	u32 data = *(u32 *)p_data;  in csfe_chicken1_mmio_write()
1860 	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);  in csfe_chicken1_mmio_write()
1861 	write_vreg(vgpu, offset, p_data, bytes);  in csfe_chicken1_mmio_write()
3526 		void *p_data, unsigned int bytes)  in intel_vgpu_default_mmio_read()  argument
3528 	read_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_default_mmio_read()
3543 		void *p_data, unsigned int bytes)  in intel_vgpu_default_mmio_write()  argument
3545 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_default_mmio_write()
3560 		void *p_data, unsigned int bytes)  in intel_vgpu_mask_mmio_write()  argument
3565 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_mask_mmio_write()