2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4  * Permission is hereby granted, free of charge, to any person obtaining a
51 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in edid_get_byte()
54 	if (edid->state == I2C_NOT_SPECIFIED || !edid->slave_selected) {  in edid_get_byte()
58 	if (edid->current_edid_read >= EDID_SIZE) {  in edid_get_byte()
63 	if (!edid->edid_available) {  in edid_get_byte()
68 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {  in edid_get_byte()
70 			intel_vgpu_port(vgpu, edid->port)->edid;  in edid_get_byte()
72 		chr = edid_data->edid_block[edid->current_edid_read];  in edid_get_byte()
73 		edid->current_edid_read++;  in edid_get_byte()
83 	int port = -EINVAL;  in cnp_get_port_from_gmbus0()
99 	int port = -EINVAL;  in bxt_get_port_from_gmbus0()
113 	int port = -EINVAL;  in get_port_from_gmbus0()
129 	if (!vgpu->display.i2c_edid.edid_available)  in reset_gmbus_controller()
131 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in reset_gmbus_controller()
138 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus0_mmio_write()
156 	if (drm_WARN_ON(&i915->drm, port < 0))  in gmbus0_mmio_write()
159 	vgpu->display.i2c_edid.state = I2C_GMBUS;  in gmbus0_mmio_write()
160 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus0_mmio_write()
167 		vgpu->display.i2c_edid.port = port;  in gmbus0_mmio_write()
168 		vgpu->display.i2c_edid.edid_available = true;  in gmbus0_mmio_write()
178 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus1_mmio_write()
208 		i2c_edid->gmbus.total_byte_count =  in gmbus1_mmio_write()
214 			i2c_edid->slave_selected = true;  in gmbus1_mmio_write()
219 					vgpu->id, slave_addr);  in gmbus1_mmio_write()
223 			i2c_edid->current_edid_read =  in gmbus1_mmio_write()
226 		i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);  in gmbus1_mmio_write()
246 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus1_mmio_write()
256 			 * START (-->INDEX) -->DATA  in gmbus1_mmio_write()
258 			i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;  in gmbus1_mmio_write()
279 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in gmbus3_mmio_write()
281 	drm_WARN_ON(&i915->drm, 1);  in gmbus3_mmio_write()
290 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in gmbus3_mmio_read()
291 	int byte_left = i2c_edid->gmbus.total_byte_count -  in gmbus3_mmio_read()
292 				i2c_edid->current_edid_read;  in gmbus3_mmio_read()
314 			switch (i2c_edid->gmbus.cycle_type) {  in gmbus3_mmio_read()
317 				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;  in gmbus3_mmio_read()
322 				i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;  in gmbus3_mmio_read()
329 		 * return the latest written value  in gmbus3_mmio_read()
341 	u32 value = vgpu_vreg(vgpu, offset);  in gmbus2_mmio_read()  local
345 	memcpy(p_data, (void *)&value, bytes);  in gmbus2_mmio_read()
356 	/* All other bits are read-only */  in gmbus2_mmio_write()
361  * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
376 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_read()
378 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_read()
379 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_read()
391  * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
406 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_gmbus_write()
408 	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))  in intel_gvt_i2c_handle_gmbus_write()
409 		return -EINVAL;  in intel_gvt_i2c_handle_gmbus_write()
457 		reg = -1;  in get_aux_ch_reg()
468  * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
482 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_gvt_i2c_handle_aux_ch_write()
483 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;  in intel_gvt_i2c_handle_aux_ch_write()
485 	int msg, addr, ctrl, op;  in intel_gvt_i2c_handle_aux_ch_write()  local
486 	u32 value = *(u32 *)p_data;  in intel_gvt_i2c_handle_aux_ch_write()  local
491 		vgpu_vreg(vgpu, offset) = value;  in intel_gvt_i2c_handle_aux_ch_write()
495 	msg_length = AUX_CTL_MSG_LENGTH(value);  in intel_gvt_i2c_handle_aux_ch_write()
499 	ctrl = (msg >> 24) & 0xff;  in intel_gvt_i2c_handle_aux_ch_write()
500 	op = ctrl >> 4;  in intel_gvt_i2c_handle_aux_ch_write()
501 	if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {  in intel_gvt_i2c_handle_aux_ch_write()
506 	/* Always set the wanted value for vms. */  in intel_gvt_i2c_handle_aux_ch_write()
519 			i2c_edid->aux_ch.i2c_over_aux_ch = true;  in intel_gvt_i2c_handle_aux_ch_write()
520 			i2c_edid->aux_ch.aux_ch_mot = true;  in intel_gvt_i2c_handle_aux_ch_write()
525 				i2c_edid->state = I2C_AUX_CH;  in intel_gvt_i2c_handle_aux_ch_write()
526 				i2c_edid->port = port_idx;  in intel_gvt_i2c_handle_aux_ch_write()
527 				i2c_edid->slave_selected = true;  in intel_gvt_i2c_handle_aux_ch_write()
531 					i2c_edid->edid_available = true;  in intel_gvt_i2c_handle_aux_ch_write()
542 		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))  in intel_gvt_i2c_handle_aux_ch_write()
544 		if (drm_WARN_ON(&i915->drm, msg_length != 4))  in intel_gvt_i2c_handle_aux_ch_write()
546 		if (i2c_edid->edid_available && i2c_edid->slave_selected) {  in intel_gvt_i2c_handle_aux_ch_write()
553 	/* write the return value in AUX_CH_DATA reg which includes:  in intel_gvt_i2c_handle_aux_ch_write()
562  * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
570 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;  in intel_vgpu_init_i2c_edid()
572 	edid->state = I2C_NOT_SPECIFIED;  in intel_vgpu_init_i2c_edid()
574 	edid->port = -1;  in intel_vgpu_init_i2c_edid()
575 	edid->slave_selected = false;  in intel_vgpu_init_i2c_edid()
576 	edid->edid_available = false;  in intel_vgpu_init_i2c_edid()
577 	edid->current_edid_read = 0;  in intel_vgpu_init_i2c_edid()
579 	memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));  in intel_vgpu_init_i2c_edid()
581 	edid->aux_ch.i2c_over_aux_ch = false;  in intel_vgpu_init_i2c_edid()
582 	edid->aux_ch.aux_ch_mot = false;  in intel_vgpu_init_i2c_edid()