Lines Matching refs:rgvswctl
396 u16 rgvswctl; in gen5_rps_set() local
400 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); in gen5_rps_set()
401 if (rgvswctl & MEMCTL_CMD_STS) { in gen5_rps_set()
410 rgvswctl = in gen5_rps_set()
414 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); in gen5_rps_set()
417 rgvswctl |= MEMCTL_CMD_STS; in gen5_rps_set()
418 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl); in gen5_rps_set()
570 u16 rgvswctl; in gen5_rps_disable() local
574 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); in gen5_rps_disable()
590 rgvswctl |= MEMCTL_CMD_STS; in gen5_rps_disable()
591 intel_uncore_write(uncore, MEMSWCTL, rgvswctl); in gen5_rps_disable()