Lines Matching refs:i915
33 return rps_to_gt(rps)->i915; in rps_to_i915()
200 if (INTEL_GEN(gt->i915) >= 11) in rps_reset_interrupts()
220 intel_synchronize_irq(gt->i915); in rps_disable_interrupts()
250 struct drm_i915_private *i915 = rps_to_i915(rps); in gen5_rps_init() local
256 if (i915->fsb_freq <= 3200) in gen5_rps_init()
258 else if (i915->fsb_freq <= 4800) in gen5_rps_init()
264 if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) { in gen5_rps_init()
278 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", in gen5_rps_init()
349 static u32 pvid_to_extvid(struct drm_i915_private *i915, u8 pxvid) in pvid_to_extvid() argument
353 if (INTEL_INFO(i915)->is_mobile) in pvid_to_extvid()
546 drm_err(&uncore->i915->drm, in gen5_rps_enable()
658 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
676 (INTEL_GEN(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) | in rps_set_power()
747 struct drm_i915_private *i915 = rps_to_i915(rps); in gen6_rps_set() local
750 if (INTEL_GEN(i915) >= 9) in gen6_rps_set()
752 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in gen6_rps_set()
768 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_set() local
771 vlv_punit_get(i915); in vlv_rps_set()
772 err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val); in vlv_rps_set()
773 vlv_punit_put(i915); in vlv_rps_set()
783 struct drm_i915_private *i915 = rps_to_i915(rps); in rps_set() local
786 if (INTEL_GEN(i915) < 6) in rps_set()
792 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
953 struct drm_i915_private *i915 = rps_to_i915(rps); in gen6_rps_init() local
959 if (IS_GEN9_LP(i915)) { in gen6_rps_init()
977 if (IS_HASWELL(i915) || IS_BROADWELL(i915) || in gen6_rps_init()
978 IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) { in gen6_rps_init()
981 if (sandybridge_pcode_read(i915, in gen6_rps_init()
991 if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) { in gen6_rps_init()
1005 struct drm_i915_private *i915 = rps_to_i915(rps); in rps_reset() local
1012 drm_err(&i915->drm, "Failed to reset RPS to initial values\n"); in rps_reset()
1027 if (IS_GEN(gt->i915, 9)) in gen9_rps_enable()
1069 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_max_freq() local
1073 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1097 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_rpe_freq() local
1100 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1108 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_guar_freq() local
1111 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1118 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_min_freq() local
1121 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1130 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_enable() local
1155 vlv_punit_get(i915); in chv_rps_enable()
1158 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); in chv_rps_enable()
1160 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1162 vlv_punit_put(i915); in chv_rps_enable()
1165 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, in chv_rps_enable()
1168 drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE)); in chv_rps_enable()
1169 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); in chv_rps_enable()
1176 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_guar_freq() local
1179 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); in vlv_rps_guar_freq()
1189 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_max_freq() local
1192 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); in vlv_rps_max_freq()
1203 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_rpe_freq() local
1206 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO); in vlv_rps_rpe_freq()
1208 val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI); in vlv_rps_rpe_freq()
1216 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_min_freq() local
1219 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1233 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_enable() local
1255 vlv_punit_get(i915); in vlv_rps_enable()
1259 vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); in vlv_rps_enable()
1261 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
1263 vlv_punit_put(i915); in vlv_rps_enable()
1266 drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, in vlv_rps_enable()
1269 drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE)); in vlv_rps_enable()
1270 drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val); in vlv_rps_enable()
1328 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_rps_enable() local
1332 if (!HAS_RPS(i915)) in intel_rps_enable()
1340 else if (IS_CHERRYVIEW(i915)) in intel_rps_enable()
1342 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1344 else if (INTEL_GEN(i915) >= 9) in intel_rps_enable()
1346 else if (INTEL_GEN(i915) >= 8) in intel_rps_enable()
1348 else if (INTEL_GEN(i915) >= 6) in intel_rps_enable()
1350 else if (IS_IRONLAKE_M(i915)) in intel_rps_enable()
1353 MISSING_CASE(INTEL_GEN(i915)); in intel_rps_enable()
1372 else if (INTEL_GEN(i915) >= 6) in intel_rps_enable()
1387 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_rps_disable() local
1393 if (INTEL_GEN(i915) >= 6) in intel_rps_disable()
1395 else if (IS_IRONLAKE_M(i915)) in intel_rps_disable()
1430 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_gpu_freq() local
1432 if (INTEL_GEN(i915) >= 9) in intel_gpu_freq()
1435 else if (IS_CHERRYVIEW(i915)) in intel_gpu_freq()
1437 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1445 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_freq_opcode() local
1447 if (INTEL_GEN(i915) >= 9) in intel_freq_opcode()
1450 else if (IS_CHERRYVIEW(i915)) in intel_freq_opcode()
1452 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
1460 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_init_gpll_ref_freq() local
1463 vlv_get_cck_clock(i915, "GPLL ref", in vlv_init_gpll_ref_freq()
1465 i915->czclk_freq); in vlv_init_gpll_ref_freq()
1467 drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n", in vlv_init_gpll_ref_freq()
1473 struct drm_i915_private *i915 = rps_to_i915(rps); in vlv_rps_init() local
1476 vlv_iosf_sb_get(i915, in vlv_rps_init()
1483 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_init()
1487 i915->mem_freq = 800; in vlv_rps_init()
1490 i915->mem_freq = 1066; in vlv_rps_init()
1493 i915->mem_freq = 1333; in vlv_rps_init()
1496 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); in vlv_rps_init()
1500 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1504 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1508 drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1512 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", in vlv_rps_init()
1515 vlv_iosf_sb_put(i915, in vlv_rps_init()
1523 struct drm_i915_private *i915 = rps_to_i915(rps); in chv_rps_init() local
1526 vlv_iosf_sb_get(i915, in chv_rps_init()
1533 val = vlv_cck_read(i915, CCK_FUSE_REG); in chv_rps_init()
1537 i915->mem_freq = 2000; in chv_rps_init()
1540 i915->mem_freq = 1600; in chv_rps_init()
1543 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); in chv_rps_init()
1547 drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n", in chv_rps_init()
1551 drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n", in chv_rps_init()
1555 drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n", in chv_rps_init()
1559 drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n", in chv_rps_init()
1562 vlv_iosf_sb_put(i915, in chv_rps_init()
1567 drm_WARN_ONCE(&i915->drm, (rps->max_freq | rps->efficient_freq | in chv_rps_init()
1623 struct drm_i915_private *i915 = rps_to_i915(rps); in rps_work() local
1664 adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1; in rps_work()
1680 adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1; in rps_work()
1696 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n"); in rps_work()
1745 if (INTEL_GEN(gt->i915) >= 8) in gen6_rps_irq_handler()
1802 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_rps_init() local
1804 if (IS_CHERRYVIEW(i915)) in intel_rps_init()
1806 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
1808 else if (INTEL_GEN(i915) >= 6) in intel_rps_init()
1810 else if (IS_IRONLAKE_M(i915)) in intel_rps_init()
1818 if (IS_GEN(i915, 6) || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) { in intel_rps_init()
1821 sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS, in intel_rps_init()
1824 drm_dbg(&i915->drm, in intel_rps_init()
1847 if (INTEL_GEN(i915) <= 7) in intel_rps_init()
1850 if (INTEL_GEN(i915) >= 8 && INTEL_GEN(i915) < 11) in intel_rps_init()
1862 struct drm_i915_private *i915 = rps_to_i915(rps); in intel_rps_get_cagf() local
1865 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
1867 else if (INTEL_GEN(i915) >= 9) in intel_rps_get_cagf()
1869 else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) in intel_rps_get_cagf()
1879 struct drm_i915_private *i915 = rps_to_i915(rps); in read_cagf() local
1882 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in read_cagf()
1883 vlv_punit_get(i915); in read_cagf()
1884 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in read_cagf()
1885 vlv_punit_put(i915); in read_cagf()
1937 if (IS_GEN(gt->i915, 5)) { in intel_rps_driver_register()
1939 rcu_assign_pointer(ips_mchdev, gt->i915); in intel_rps_driver_register()
1952 struct drm_i915_private *i915; in mchdev_get() local
1955 i915 = rcu_dereference(ips_mchdev); in mchdev_get()
1956 if (!kref_get_unless_zero(&i915->drm.ref)) in mchdev_get()
1957 i915 = NULL; in mchdev_get()
1960 return i915; in mchdev_get()
1971 struct drm_i915_private *i915; in i915_read_mch_val() local
1976 i915 = mchdev_get(); in i915_read_mch_val()
1977 if (!i915) in i915_read_mch_val()
1980 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { in i915_read_mch_val()
1981 struct intel_ips *ips = &i915->gt.rps.ips; in i915_read_mch_val()
1989 drm_dev_put(&i915->drm); in i915_read_mch_val()
2001 struct drm_i915_private *i915; in i915_gpu_raise() local
2004 i915 = mchdev_get(); in i915_gpu_raise()
2005 if (!i915) in i915_gpu_raise()
2008 rps = &i915->gt.rps; in i915_gpu_raise()
2015 drm_dev_put(&i915->drm); in i915_gpu_raise()
2028 struct drm_i915_private *i915; in i915_gpu_lower() local
2031 i915 = mchdev_get(); in i915_gpu_lower()
2032 if (!i915) in i915_gpu_lower()
2035 rps = &i915->gt.rps; in i915_gpu_lower()
2042 drm_dev_put(&i915->drm); in i915_gpu_lower()
2054 struct drm_i915_private *i915; in i915_gpu_busy() local
2057 i915 = mchdev_get(); in i915_gpu_busy()
2058 if (!i915) in i915_gpu_busy()
2061 ret = i915->gt.awake; in i915_gpu_busy()
2063 drm_dev_put(&i915->drm); in i915_gpu_busy()
2076 struct drm_i915_private *i915; in i915_gpu_turbo_disable() local
2080 i915 = mchdev_get(); in i915_gpu_turbo_disable()
2081 if (!i915) in i915_gpu_turbo_disable()
2084 rps = &i915->gt.rps; in i915_gpu_turbo_disable()
2088 ret = gen5_rps_set(&i915->gt.rps, rps->min_freq); in i915_gpu_turbo_disable()
2091 drm_dev_put(&i915->drm); in i915_gpu_turbo_disable()