49 	return rc6_to_gt(rc)->i915;  in rc6_to_i915()
113 	if (INTEL_GEN(gt->i915) >= 12) {  in gen11_rc6_enable()
219 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in gen6_rc6_enable()  local
242 	if (HAS_RC6p(i915))  in gen6_rc6_enable()
244 	if (HAS_RC6pp(i915))  in gen6_rc6_enable()
252 	ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,  in gen6_rc6_enable()
254 	if (IS_GEN(i915, 6) && ret) {  in gen6_rc6_enable()
255 		drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");  in gen6_rc6_enable()
256 	} else if (IS_GEN(i915, 6) &&  in gen6_rc6_enable()
258 		drm_dbg(&i915->drm,  in gen6_rc6_enable()
263 		ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);  in gen6_rc6_enable()
265 			drm_err(&i915->drm,  in gen6_rc6_enable()
274 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in chv_rc6_init()  local
281 		drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");  in chv_rc6_init()
282 		paddr = i915->dsm.end + 1 - pctx_size;  in chv_rc6_init()
294 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in vlv_rc6_init()  local
306 		pcbr_offset = (pcbr & ~4095) - i915->dsm.start;  in vlv_rc6_init()
307 		pctx = i915_gem_object_create_stolen_for_preallocated(i915,  in vlv_rc6_init()
316 	drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");  in vlv_rc6_init()
326 	pctx = i915_gem_object_create_stolen(i915, pctx_size);  in vlv_rc6_init()
328 		drm_dbg(&i915->drm,  in vlv_rc6_init()
334 					 i915->dsm.start,  in vlv_rc6_init()
337 	pctx_paddr = i915->dsm.start + pctx->stolen->start;  in vlv_rc6_init()
403 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in bxt_check_bios_rc6_setup()  local
411 	drm_dbg(&i915->drm, "BIOS enabled RC states: "  in bxt_check_bios_rc6_setup()
418 		drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");  in bxt_check_bios_rc6_setup()
428 	if (!(rc6_ctx_base >= i915->dsm_reserved.start &&  in bxt_check_bios_rc6_setup()
429 	      rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) {  in bxt_check_bios_rc6_setup()
430 		drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");  in bxt_check_bios_rc6_setup()
438 		drm_dbg(&i915->drm,  in bxt_check_bios_rc6_setup()
446 		drm_dbg(&i915->drm, "Pushbus not setup properly.\n");  in bxt_check_bios_rc6_setup()
451 		drm_dbg(&i915->drm, "GFX pause not setup properly.\n");  in bxt_check_bios_rc6_setup()
456 		drm_dbg(&i915->drm, "GPM control not setup properly.\n");  in bxt_check_bios_rc6_setup()
465 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in rc6_supported()  local
467 	if (!HAS_RC6(i915))  in rc6_supported()
470 	if (intel_vgpu_active(i915))  in rc6_supported()
476 	if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {  in rc6_supported()
477 		drm_notice(&i915->drm,  in rc6_supported()
501 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in pctx_corrupted()  local
503 	if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))  in pctx_corrupted()
509 	drm_notice(&i915->drm,  in pctx_corrupted()
516 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in __intel_rc6_disable()  local
520 	if (INTEL_GEN(i915) >= 9)  in __intel_rc6_disable()
529 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in intel_rc6_init()  local
538 	if (IS_CHERRYVIEW(i915))  in intel_rc6_init()
540 	else if (IS_VALLEYVIEW(i915))  in intel_rc6_init()
566 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in intel_rc6_enable()  local
576 	if (IS_CHERRYVIEW(i915))  in intel_rc6_enable()
578 	else if (IS_VALLEYVIEW(i915))  in intel_rc6_enable()
580 	else if (INTEL_GEN(i915) >= 11)  in intel_rc6_enable()
582 	else if (INTEL_GEN(i915) >= 9)  in intel_rc6_enable()
584 	else if (IS_BROADWELL(i915))  in intel_rc6_enable()
586 	else if (INTEL_GEN(i915) >= 6)  in intel_rc6_enable()
590 	if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))  in intel_rc6_enable()
714 	struct drm_i915_private *i915 = rc6_to_i915(rc6);  in intel_rc6_residency_ns()  local
734 	if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency)))  in intel_rc6_residency_ns()
743 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {  in intel_rc6_residency_ns()
745 		div = i915->czclk_freq;  in intel_rc6_residency_ns()
750 		if (IS_GEN9_LP(i915)) {  in intel_rc6_residency_ns()