52 #define __ENGINE_REG_OP(op__, engine__, ...) \  argument
53 	intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
55 #define __ENGINE_READ_OP(op__, engine__, reg__) \  argument
56 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
64 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \  argument
65 	__ENGINE_REG_OP(read64_2x32, (engine__), \
66 			lower_reg__((engine__)->mmio_base), \
67 			upper_reg__((engine__)->mmio_base))
69 #define ENGINE_READ_IDX(engine__, reg__, idx__) \  argument
70 	__ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
72 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \  argument
73 	__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
79 #define GEN6_RING_FAULT_REG_READ(engine__) \  argument
80 	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
82 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \  argument
83 	intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
85 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \  argument
89 	__val = intel_uncore_read((engine__)->uncore, \
90 				  RING_FAULT_REG(engine__)); \
93 	intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \