Lines Matching +full:0 +full:- +full:15
1 // SPDX-License-Identifier: MIT
15 ROW_INDEX_6BPP = 0,
24 COLUMN_INDEX_8BPC = 0,
56 { 768, 15, 6144, 3, 13, 11, 11, {
57 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
58 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
59 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
60 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
64 { 768, 15, 6144, 7, 17, 15, 15, {
65 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
66 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
67 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
68 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
69 { 17, 18, -12 }
73 { 768, 15, 6144, 11, 21, 19, 19, {
74 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
75 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
76 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
77 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
78 { 21, 22, -12 }
82 { 768, 15, 6144, 15, 25, 23, 27, {
83 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
84 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
85 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
86 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
87 { 25, 26, -12 }
91 { 768, 15, 6144, 19, 29, 27, 27, {
92 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
93 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
94 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
95 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
96 { 29, 30, -12 }
103 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
104 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
105 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
106 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
110 { 512, 12, 6144, 7, 16, 15, 15, {
111 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
112 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
113 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
114 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
119 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
120 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
121 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
122 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
123 { 21, 23, -12 }
127 { 512, 12, 6144, 15, 24, 23, 23, {
128 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
129 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
130 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
131 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
132 { 24, 25, -12 }
137 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
138 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
139 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
140 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
141 { 28, 29, -12 }
147 { 410, 15, 5632, 3, 12, 11, 11, {
148 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
149 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
150 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
151 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
155 { 410, 15, 5632, 7, 16, 15, 15, {
156 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
157 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
158 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
159 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
163 { 410, 15, 5632, 11, 20, 19, 19, {
164 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
165 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
166 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
167 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
168 { 19, 20, -12 }
172 { 410, 15, 5632, 15, 24, 23, 23, {
173 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
174 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
175 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
176 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
177 { 23, 24, -12 }
181 { 410, 15, 5632, 19, 28, 27, 27, {
182 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
183 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
184 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
185 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
186 { 27, 28, -12 }
192 { 341, 15, 2048, 3, 12, 11, 11, {
193 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
194 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
195 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
196 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
200 { 341, 15, 2048, 7, 16, 15, 15, {
201 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
202 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
203 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
204 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
208 { 341, 15, 2048, 11, 20, 19, 19, {
209 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
210 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
211 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
212 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
213 { 21, 23, -12 }
217 { 341, 15, 2048, 15, 24, 23, 23, {
218 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
219 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
220 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
221 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
222 { 22, 23, -12 }
226 { 341, 15, 2048, 19, 28, 27, 27, {
227 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
228 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
229 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
230 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
231 { 26, 27, -12 }
236 /* 15BPP/8BPC */
237 { 273, 15, 2048, 3, 12, 11, 11, {
238 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
239 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
240 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
241 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
244 /* 15BPP/10BPC */
245 { 273, 15, 2048, 7, 16, 15, 15, {
246 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
247 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
248 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
249 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
252 /* 15BPP/12BPC */
253 { 273, 15, 2048, 11, 20, 19, 19, {
254 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
255 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
256 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
257 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
258 { 16, 17, -12 }
261 /* 15BPP/14BPC */
262 { 273, 15, 2048, 15, 24, 23, 23, {
263 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
264 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
265 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
266 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
267 { 20, 21, -12 }
270 /* 15BPP/16BPC */
271 { 273, 15, 2048, 19, 28, 27, 27, {
272 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
273 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
274 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
275 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
276 { 24, 25, -12 }
294 case 15: in get_row_index_for_rc_params()
297 return -EINVAL; in get_row_index_for_rc_params()
315 return -EINVAL; in get_column_index_for_rc_params()
325 if (row_index < 0) in get_rc_params()
329 if (column_index < 0) in get_rc_params()
338 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_source_support()
339 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsc_source_support()
340 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
341 enum pipe pipe = crtc->pipe; in intel_dsc_source_support()
343 if (!INTEL_INFO(i915)->display.has_dsc) in intel_dsc_source_support()
362 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in is_pipe_dsc()
363 const struct drm_i915_private *i915 = to_i915(crtc->base.dev); in is_pipe_dsc()
364 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in is_pipe_dsc()
375 drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); in is_pipe_dsc()
383 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
384 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
386 u8 i = 0; in intel_dsc_compute_params()
388 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
389 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_dsc_compute_params()
390 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
391 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
394 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
396 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
399 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()
400 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
402 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_compute_params()
404 * six 0s are appended to the lsb of each threshold value in intel_dsc_compute_params()
408 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6; in intel_dsc_compute_params()
416 vdsc_cfg->rc_buf_thresh[12] = 0x7C; in intel_dsc_compute_params()
417 vdsc_cfg->rc_buf_thresh[13] = 0x7D; in intel_dsc_compute_params()
420 rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component); in intel_dsc_compute_params()
422 return -EINVAL; in intel_dsc_compute_params()
424 vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset; in intel_dsc_compute_params()
425 vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay; in intel_dsc_compute_params()
426 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()
427 vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp; in intel_dsc_compute_params()
428 vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp; in intel_dsc_compute_params()
429 vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0; in intel_dsc_compute_params()
430 vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1; in intel_dsc_compute_params()
432 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_compute_params()
433 vdsc_cfg->rc_range_params[i].range_min_qp = in intel_dsc_compute_params()
434 rc_params->rc_range_params[i].range_min_qp; in intel_dsc_compute_params()
435 vdsc_cfg->rc_range_params[i].range_max_qp = in intel_dsc_compute_params()
436 rc_params->rc_range_params[i].range_max_qp; in intel_dsc_compute_params()
441 vdsc_cfg->rc_range_params[i].range_bpg_offset = in intel_dsc_compute_params()
442 rc_params->rc_range_params[i].range_bpg_offset & in intel_dsc_compute_params()
452 if (vdsc_cfg->bits_per_component == 8 || in intel_dsc_compute_params()
453 vdsc_cfg->bits_per_component == 10) in intel_dsc_compute_params()
454 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in intel_dsc_compute_params()
455 else if (vdsc_cfg->bits_per_component == 12) in intel_dsc_compute_params()
456 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; in intel_dsc_compute_params()
459 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dsc_compute_params()
461 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()
462 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
464 return 0; in intel_dsc_compute_params()
470 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_power_domain()
471 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_dsc_power_domain()
472 enum pipe pipe = crtc->pipe; in intel_dsc_power_domain()
478 * - ICL eDP/DSI transcoder in intel_dsc_power_domain()
479 * - Gen12+ (except RKL) pipe A in intel_dsc_power_domain()
496 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_pps_configure()
497 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsc_pps_configure()
498 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
499 enum pipe pipe = crtc->pipe; in intel_dsc_pps_configure()
500 u32 pps_val = 0; in intel_dsc_pps_configure()
503 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; in intel_dsc_pps_configure()
504 int i = 0; in intel_dsc_pps_configure()
507 pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << in intel_dsc_pps_configure()
509 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | in intel_dsc_pps_configure()
510 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; in intel_dsc_pps_configure()
511 if (vdsc_cfg->block_pred_enable) in intel_dsc_pps_configure()
513 if (vdsc_cfg->convert_rgb) in intel_dsc_pps_configure()
515 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()
517 if (vdsc_cfg->vbr_enable) in intel_dsc_pps_configure()
519 drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
527 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
534 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
541 pps_val = 0; in intel_dsc_pps_configure()
542 pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); in intel_dsc_pps_configure()
543 drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
551 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
558 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
565 pps_val = 0; in intel_dsc_pps_configure()
566 pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | in intel_dsc_pps_configure()
567 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); in intel_dsc_pps_configure()
568 drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
576 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
583 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
590 pps_val = 0; in intel_dsc_pps_configure()
591 pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | in intel_dsc_pps_configure()
592 DSC_SLICE_WIDTH(vdsc_cfg->slice_width); in intel_dsc_pps_configure()
593 drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
601 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
608 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
615 pps_val = 0; in intel_dsc_pps_configure()
616 pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | in intel_dsc_pps_configure()
617 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); in intel_dsc_pps_configure()
618 drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
626 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
633 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
640 pps_val = 0; in intel_dsc_pps_configure()
641 pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | in intel_dsc_pps_configure()
642 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); in intel_dsc_pps_configure()
643 drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
651 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
658 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
665 pps_val = 0; in intel_dsc_pps_configure()
666 pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | in intel_dsc_pps_configure()
667 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | in intel_dsc_pps_configure()
668 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | in intel_dsc_pps_configure()
669 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); in intel_dsc_pps_configure()
670 drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
678 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
685 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
692 pps_val = 0; in intel_dsc_pps_configure()
693 pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | in intel_dsc_pps_configure()
694 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); in intel_dsc_pps_configure()
695 drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
703 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
710 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
717 pps_val = 0; in intel_dsc_pps_configure()
718 pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | in intel_dsc_pps_configure()
719 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
720 drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
728 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
735 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
742 pps_val = 0; in intel_dsc_pps_configure()
745 drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
753 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
760 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
767 pps_val = 0; in intel_dsc_pps_configure()
768 pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | in intel_dsc_pps_configure()
769 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | in intel_dsc_pps_configure()
772 drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
780 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
787 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
794 pps_val = 0; in intel_dsc_pps_configure()
795 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
796 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / in intel_dsc_pps_configure()
797 vdsc_cfg->slice_width) | in intel_dsc_pps_configure()
798 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / in intel_dsc_pps_configure()
799 vdsc_cfg->slice_height); in intel_dsc_pps_configure()
800 drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); in intel_dsc_pps_configure()
808 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
815 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
822 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); in intel_dsc_pps_configure()
823 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { in intel_dsc_pps_configure()
825 (u32)(vdsc_cfg->rc_buf_thresh[i] << in intel_dsc_pps_configure()
827 drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, in intel_dsc_pps_configure()
832 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
839 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
841 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
851 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
858 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
861 rc_buf_thresh_dword[0]); in intel_dsc_pps_configure()
875 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); in intel_dsc_pps_configure()
876 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { in intel_dsc_pps_configure()
878 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
880 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
882 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
884 drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, in intel_dsc_pps_configure()
889 rc_range_params_dword[0]); in intel_dsc_pps_configure()
904 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
906 rc_range_params_dword[0]); in intel_dsc_pps_configure()
928 rc_range_params_dword[0]); in intel_dsc_pps_configure()
947 if (crtc_state->dsc.dsc_split) { in intel_dsc_pps_configure()
950 rc_range_params_dword[0]); in intel_dsc_pps_configure()
979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsc_get_config()
980 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_get_config()
981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_get_config()
982 enum pipe pipe = crtc->pipe; in intel_dsc_get_config()
1004 crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; in intel_dsc_get_config()
1005 if (!crtc_state->dsc.compression_enable) in intel_dsc_get_config()
1008 crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && in intel_dsc_get_config()
1019 vdsc_cfg->bits_per_pixel = val; in intel_dsc_get_config()
1020 crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; in intel_dsc_get_config()
1028 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dsi_pps_write()
1036 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsc_dsi_pps_write()
1037 dsi = intel_dsi->dsi_hosts[port]->device; in intel_dsc_dsi_pps_write()
1049 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_dp_pps_write()
1052 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ in intel_dsc_dp_pps_write()
1055 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ in intel_dsc_dp_pps_write()
1058 dig_port->write_infoframe(encoder, crtc_state, in intel_dsc_dp_pps_write()
1066 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_enable()
1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsc_enable()
1068 enum pipe pipe = crtc->pipe; in intel_dsc_enable()
1070 u32 dss_ctl1_val = 0; in intel_dsc_enable()
1071 u32 dss_ctl2_val = 0; in intel_dsc_enable()
1073 if (!crtc_state->dsc.compression_enable) in intel_dsc_enable()
1082 if (encoder->type == INTEL_OUTPUT_DSI) in intel_dsc_enable()
1095 if (crtc_state->dsc.dsc_split) { in intel_dsc_enable()
1105 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in intel_dsc_disable()
1106 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsc_disable()
1107 enum pipe pipe = crtc->pipe; in intel_dsc_disable()
1109 u32 dss_ctl1_val = 0, dss_ctl2_val = 0; in intel_dsc_disable()
1111 if (!old_crtc_state->dsc.compression_enable) in intel_dsc_disable()