94 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,  in get_gmbus_pin()  argument
97 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in get_gmbus_pin()
99 	else if (HAS_PCH_CNP(dev_priv))  in get_gmbus_pin()
101 	else if (IS_GEN9_LP(dev_priv))  in get_gmbus_pin()
103 	else if (IS_GEN9_BC(dev_priv))  in get_gmbus_pin()
105 	else if (IS_BROADWELL(dev_priv))  in get_gmbus_pin()
111 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,  in intel_gmbus_is_valid_pin()  argument
116 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)  in intel_gmbus_is_valid_pin()
118 	else if (HAS_PCH_CNP(dev_priv))  in intel_gmbus_is_valid_pin()
120 	else if (IS_GEN9_LP(dev_priv))  in intel_gmbus_is_valid_pin()
122 	else if (IS_GEN9_BC(dev_priv))  in intel_gmbus_is_valid_pin()
124 	else if (IS_BROADWELL(dev_priv))  in intel_gmbus_is_valid_pin()
129 	return pin < size && get_gmbus_pin(dev_priv, pin)->name;  in intel_gmbus_is_valid_pin()
143 intel_gmbus_reset(struct drm_i915_private *dev_priv)  in intel_gmbus_reset()  argument
145 	intel_de_write(dev_priv, GMBUS0, 0);  in intel_gmbus_reset()
146 	intel_de_write(dev_priv, GMBUS4, 0);  in intel_gmbus_reset()
149 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,  in pnv_gmbus_clock_gating()  argument
155 	val = intel_de_read(dev_priv, DSPCLK_GATE_D);  in pnv_gmbus_clock_gating()
160 	intel_de_write(dev_priv, DSPCLK_GATE_D, val);  in pnv_gmbus_clock_gating()
163 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,  in pch_gmbus_clock_gating()  argument
168 	val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D);  in pch_gmbus_clock_gating()
173 	intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val);  in pch_gmbus_clock_gating()
176 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,  in bxt_gmbus_clock_gating()  argument
181 	val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4);  in bxt_gmbus_clock_gating()
186 	intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val);  in bxt_gmbus_clock_gating()
191 	struct drm_i915_private *i915 = bus->dev_priv;  in get_reserved()
207 	struct intel_uncore *uncore = &bus->dev_priv->uncore;  in get_clock()
222 	struct intel_uncore *uncore = &bus->dev_priv->uncore;  in get_data()
237 	struct intel_uncore *uncore = &bus->dev_priv->uncore;  in set_clock()
256 	struct intel_uncore *uncore = &bus->dev_priv->uncore;  in set_data()
276 	struct drm_i915_private *dev_priv = bus->dev_priv;  in intel_gpio_pre_xfer()  local
278 	intel_gmbus_reset(dev_priv);  in intel_gpio_pre_xfer()
280 	if (IS_PINEVIEW(dev_priv))  in intel_gpio_pre_xfer()
281 		pnv_gmbus_clock_gating(dev_priv, false);  in intel_gpio_pre_xfer()
295 	struct drm_i915_private *dev_priv = bus->dev_priv;  in intel_gpio_post_xfer()  local
300 	if (IS_PINEVIEW(dev_priv))  in intel_gpio_post_xfer()
301 		pnv_gmbus_clock_gating(dev_priv, true);  in intel_gpio_post_xfer()
307 	struct drm_i915_private *dev_priv = bus->dev_priv;  in intel_gpio_setup()  local
312 	bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);  in intel_gpio_setup()
325 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)  in gmbus_wait()  argument
335 	if (!HAS_GMBUS_IRQ(dev_priv))  in gmbus_wait()
338 	add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);  in gmbus_wait()
339 	intel_de_write_fw(dev_priv, GMBUS4, irq_en);  in gmbus_wait()
342 	ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,  in gmbus_wait()
345 		ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status,  in gmbus_wait()
348 	intel_de_write_fw(dev_priv, GMBUS4, 0);  in gmbus_wait()
349 	remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);  in gmbus_wait()
358 gmbus_wait_idle(struct drm_i915_private *dev_priv)  in gmbus_wait_idle()  argument
366 	if (HAS_GMBUS_IRQ(dev_priv))  in gmbus_wait_idle()
369 	add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);  in gmbus_wait_idle()
370 	intel_de_write_fw(dev_priv, GMBUS4, irq_enable);  in gmbus_wait_idle()
372 	ret = intel_wait_for_register_fw(&dev_priv->uncore,  in gmbus_wait_idle()
376 	intel_de_write_fw(dev_priv, GMBUS4, 0);  in gmbus_wait_idle()
377 	remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);  in gmbus_wait_idle()
382 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)  in gmbus_max_xfer_size()  argument
384 	return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :  in gmbus_max_xfer_size()
389 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,  in gmbus_xfer_read_chunk()  argument
394 	bool burst_read = len > gmbus_max_xfer_size(dev_priv);  in gmbus_xfer_read_chunk()
407 		intel_de_write_fw(dev_priv, GMBUS0,  in gmbus_xfer_read_chunk()
411 	intel_de_write_fw(dev_priv, GMBUS1,  in gmbus_xfer_read_chunk()
417 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);  in gmbus_xfer_read_chunk()
421 		val = intel_de_read_fw(dev_priv, GMBUS3);  in gmbus_xfer_read_chunk()
432 			intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg);  in gmbus_xfer_read_chunk()
449 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,  in gmbus_xfer_read()  argument
458 		if (HAS_GMBUS_BURST_READ(dev_priv))  in gmbus_xfer_read()
461 			len = min(rx_size, gmbus_max_xfer_size(dev_priv));  in gmbus_xfer_read()
463 		ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,  in gmbus_xfer_read()
476 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,  in gmbus_xfer_write_chunk()  argument
489 	intel_de_write_fw(dev_priv, GMBUS3, val);  in gmbus_xfer_write_chunk()
490 	intel_de_write_fw(dev_priv, GMBUS1,  in gmbus_xfer_write_chunk()
500 		intel_de_write_fw(dev_priv, GMBUS3, val);  in gmbus_xfer_write_chunk()
502 		ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);  in gmbus_xfer_write_chunk()
511 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,  in gmbus_xfer_write()  argument
520 		len = min(tx_size, gmbus_max_xfer_size(dev_priv));  in gmbus_xfer_write()
522 		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,  in gmbus_xfer_write()
549 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,  in gmbus_index_xfer()  argument
565 		intel_de_write_fw(dev_priv, GMBUS5, gmbus5);  in gmbus_index_xfer()
568 		ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,  in gmbus_index_xfer()
571 		ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);  in gmbus_index_xfer()
575 		intel_de_write_fw(dev_priv, GMBUS5, 0);  in gmbus_index_xfer()
587 	struct drm_i915_private *dev_priv = bus->dev_priv;  in do_gmbus_xfer()  local
592 	if (IS_GEN9_LP(dev_priv))  in do_gmbus_xfer()
593 		bxt_gmbus_clock_gating(dev_priv, false);  in do_gmbus_xfer()
594 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))  in do_gmbus_xfer()
595 		pch_gmbus_clock_gating(dev_priv, false);  in do_gmbus_xfer()
598 	intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0);  in do_gmbus_xfer()
603 			ret = gmbus_index_xfer(dev_priv, &msgs[i],  in do_gmbus_xfer()
607 			ret = gmbus_xfer_read(dev_priv, &msgs[i],  in do_gmbus_xfer()
610 			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);  in do_gmbus_xfer()
614 			ret = gmbus_wait(dev_priv,  in do_gmbus_xfer()
626 	intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);  in do_gmbus_xfer()
632 	if (gmbus_wait_idle(dev_priv)) {  in do_gmbus_xfer()
633 		drm_dbg_kms(&dev_priv->drm,  in do_gmbus_xfer()
638 	intel_de_write_fw(dev_priv, GMBUS0, 0);  in do_gmbus_xfer()
657 	if (gmbus_wait_idle(dev_priv)) {  in do_gmbus_xfer()
658 		drm_dbg_kms(&dev_priv->drm,  in do_gmbus_xfer()
668 	intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT);  in do_gmbus_xfer()
669 	intel_de_write_fw(dev_priv, GMBUS1, 0);  in do_gmbus_xfer()
670 	intel_de_write_fw(dev_priv, GMBUS0, 0);  in do_gmbus_xfer()
672 	drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",  in do_gmbus_xfer()
683 		drm_dbg_kms(&dev_priv->drm,  in do_gmbus_xfer()
692 	drm_dbg_kms(&dev_priv->drm,  in do_gmbus_xfer()
695 	intel_de_write_fw(dev_priv, GMBUS0, 0);  in do_gmbus_xfer()
705 	if (IS_GEN9_LP(dev_priv))  in do_gmbus_xfer()
706 		bxt_gmbus_clock_gating(dev_priv, true);  in do_gmbus_xfer()
707 	else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))  in do_gmbus_xfer()
708 		pch_gmbus_clock_gating(dev_priv, true);  in do_gmbus_xfer()
718 	struct drm_i915_private *dev_priv = bus->dev_priv;  in gmbus_xfer()  local
722 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);  in gmbus_xfer()
734 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);  in gmbus_xfer()
743 	struct drm_i915_private *dev_priv = bus->dev_priv;  in intel_gmbus_output_aksv()  local
763 	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);  in intel_gmbus_output_aksv()
764 	mutex_lock(&dev_priv->gmbus_mutex);  in intel_gmbus_output_aksv()
773 	mutex_unlock(&dev_priv->gmbus_mutex);  in intel_gmbus_output_aksv()
774 	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);  in intel_gmbus_output_aksv()
797 	struct drm_i915_private *dev_priv = bus->dev_priv;  in gmbus_lock_bus()  local
799 	mutex_lock(&dev_priv->gmbus_mutex);  in gmbus_lock_bus()
806 	struct drm_i915_private *dev_priv = bus->dev_priv;  in gmbus_trylock_bus()  local
808 	return mutex_trylock(&dev_priv->gmbus_mutex);  in gmbus_trylock_bus()
815 	struct drm_i915_private *dev_priv = bus->dev_priv;  in gmbus_unlock_bus()  local
817 	mutex_unlock(&dev_priv->gmbus_mutex);  in gmbus_unlock_bus()
830 int intel_gmbus_setup(struct drm_i915_private *dev_priv)  in intel_gmbus_setup()  argument
832 	struct pci_dev *pdev = dev_priv->drm.pdev;  in intel_gmbus_setup()
837 	if (!HAS_DISPLAY(dev_priv))  in intel_gmbus_setup()
840 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_gmbus_setup()
841 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;  in intel_gmbus_setup()
842 	else if (!HAS_GMCH(dev_priv))  in intel_gmbus_setup()
847 		dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;  in intel_gmbus_setup()
849 	mutex_init(&dev_priv->gmbus_mutex);  in intel_gmbus_setup()
850 	init_waitqueue_head(&dev_priv->gmbus_wait_queue);  in intel_gmbus_setup()
852 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {  in intel_gmbus_setup()
853 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))  in intel_gmbus_setup()
856 		bus = &dev_priv->gmbus[pin];  in intel_gmbus_setup()
863 			 get_gmbus_pin(dev_priv, pin)->name);  in intel_gmbus_setup()
866 		bus->dev_priv = dev_priv;  in intel_gmbus_setup()
881 		if (IS_I830(dev_priv))  in intel_gmbus_setup()
891 	intel_gmbus_reset(dev_priv);  in intel_gmbus_setup()
897 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))  in intel_gmbus_setup()
900 		bus = &dev_priv->gmbus[pin];  in intel_gmbus_setup()
906 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,  in intel_gmbus_get_adapter()  argument
909 	if (drm_WARN_ON(&dev_priv->drm,  in intel_gmbus_get_adapter()
910 			!intel_gmbus_is_valid_pin(dev_priv, pin)))  in intel_gmbus_get_adapter()
913 	return &dev_priv->gmbus[pin].adapter;  in intel_gmbus_get_adapter()
926 	struct drm_i915_private *dev_priv = bus->dev_priv;  in intel_gmbus_force_bit()  local
928 	mutex_lock(&dev_priv->gmbus_mutex);  in intel_gmbus_force_bit()
931 	drm_dbg_kms(&dev_priv->drm,  in intel_gmbus_force_bit()
936 	mutex_unlock(&dev_priv->gmbus_mutex);  in intel_gmbus_force_bit()
946 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)  in intel_gmbus_teardown()  argument
951 	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {  in intel_gmbus_teardown()
952 		if (!intel_gmbus_is_valid_pin(dev_priv, pin))  in intel_gmbus_teardown()
955 		bus = &dev_priv->gmbus[pin];  in intel_gmbus_teardown()