43  * occurrence until the next modeset on a given pipe.
46  * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
58 	enum pipe pipe;  in ivb_can_enable_err_int()  local
62 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
63 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in ivb_can_enable_err_int()
75 	enum pipe pipe;  in cpt_can_enable_serr_int()  local
80 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
81 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in cpt_can_enable_serr_int()
93 	i915_reg_t reg = PIPESTAT(crtc->pipe);  in i9xx_check_fifo_underruns()
101 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
105 	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
106 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
110 					     enum pipe pipe,  in i9xx_set_fifo_underrun_reporting()  argument
114 	i915_reg_t reg = PIPESTAT(pipe);  in i9xx_set_fifo_underrun_reporting()
119 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_set_fifo_underrun_reporting()
126 			drm_err(&dev_priv->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
127 				pipe_name(pipe));  in i9xx_set_fifo_underrun_reporting()
132 					    enum pipe pipe, bool enable)  in ilk_set_fifo_underrun_reporting()  argument
135 	u32 bit = (pipe == PIPE_A) ?  in ilk_set_fifo_underrun_reporting()
147 	enum pipe pipe = crtc->pipe;  in ivb_check_fifo_underruns()  local
152 	if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0)  in ivb_check_fifo_underruns()
155 	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_check_fifo_underruns()
158 	trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in ivb_check_fifo_underruns()
159 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
163 					    enum pipe pipe, bool enable,  in ivb_set_fifo_underrun_reporting()  argument
169 			       ERR_INT_FIFO_UNDERRUN(pipe));  in ivb_set_fifo_underrun_reporting()
179 		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivb_set_fifo_underrun_reporting()
181 				"uncleared fifo underrun on pipe %c\n",  in ivb_set_fifo_underrun_reporting()
182 				pipe_name(pipe));  in ivb_set_fifo_underrun_reporting()
188 					    enum pipe pipe, bool enable)  in bdw_set_fifo_underrun_reporting()  argument
193 		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
195 		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in bdw_set_fifo_underrun_reporting()
199 					    enum pipe pch_transcoder,  in ibx_set_fifo_underrun_reporting()
215 	enum pipe pch_transcoder = crtc->pipe;  in cpt_check_pch_fifo_underruns()
233 					    enum pipe pch_transcoder,  in cpt_set_fifo_underrun_reporting()
259 						    enum pipe pipe, bool enable)  in __intel_set_cpu_fifo_underrun_reporting()  argument
262 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
271 		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
273 		ilk_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
275 		ivb_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
277 		bdw_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
285  * @pipe: (CPU) pipe to set state for
288  * This function sets the fifo underrun state for @pipe. It is used in the
290  * expected when disabling or enabling the pipe.
292  * Notice that on some platforms disabling underrun reports for one pipe
293  * disables for all due to shared interrupts. Actual reporting is still per-pipe
299 					   enum pipe pipe, bool enable)  in intel_set_cpu_fifo_underrun_reporting()  argument
305 	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,  in intel_set_cpu_fifo_underrun_reporting()
315  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
327 					   enum pipe pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
336 	 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT  in intel_set_pch_fifo_underrun_reporting()
338 	 * pch transcoder -> pipe lookups from interrupt code simply store the  in intel_set_pch_fifo_underrun_reporting()
365  * @pipe: (CPU) pipe to set state for
372 					 enum pipe pipe)  in intel_cpu_fifo_underrun_irq_handler()  argument
374 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
385 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
386 		trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
387 		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",  in intel_cpu_fifo_underrun_irq_handler()
388 			pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
397  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
404 					 enum pipe pch_transcoder)  in intel_pch_fifo_underrun_irq_handler()