101 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in i8xx_fbc_activate()
152 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in g4x_fbc_activate()
192 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in i8xx_fbc_recompress()
203 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in i965_fbc_recompress()
215 	struct intel_fbc *fbc = &dev_priv->fbc;  in snb_fbc_recompress()  local
217 	trace_intel_fbc_nuke(fbc->crtc);  in snb_fbc_recompress()
235 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in ilk_fbc_activate()
237 	int threshold = dev_priv->fbc.threshold;  in ilk_fbc_activate()
300 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in gen7_fbc_activate()
302 	int threshold = dev_priv->fbc.threshold;  in gen7_fbc_activate()
347 	if (dev_priv->fbc.false_color)  in gen7_fbc_activate()
367 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_activate()  local
369 	trace_intel_fbc_activate(fbc->crtc);  in intel_fbc_hw_activate()
371 	fbc->active = true;  in intel_fbc_hw_activate()
372 	fbc->activated = true;  in intel_fbc_hw_activate()
386 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_deactivate()  local
388 	trace_intel_fbc_deactivate(fbc->crtc);  in intel_fbc_hw_deactivate()
390 	fbc->active = false;  in intel_fbc_hw_deactivate()
411 	return dev_priv->fbc.active;  in intel_fbc_is_active()
417 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_deactivate()  local
419 	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));  in intel_fbc_deactivate()
421 	if (fbc->active)  in intel_fbc_deactivate()
424 	fbc->no_fbc_reason = reason;  in intel_fbc_deactivate()
489 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_alloc_cfb()  local
494 		    drm_mm_node_allocated(&fbc->compressed_fb));  in intel_fbc_alloc_cfb()
496 	ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,  in intel_fbc_alloc_cfb()
505 	fbc->threshold = ret;  in intel_fbc_alloc_cfb()
509 			       fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
512 			       fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
523 		fbc->compressed_llb = compressed_llb;  in intel_fbc_alloc_cfb()
526 						 fbc->compressed_fb.start,  in intel_fbc_alloc_cfb()
529 						 fbc->compressed_llb->start,  in intel_fbc_alloc_cfb()
532 			       dev_priv->dsm.start + fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
539 		    fbc->compressed_fb.size, fbc->threshold);  in intel_fbc_alloc_cfb()
545 	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);  in intel_fbc_alloc_cfb()
554 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_cleanup_cfb()  local
559 	if (!drm_mm_node_allocated(&fbc->compressed_fb))  in __intel_fbc_cleanup_cfb()
562 	if (fbc->compressed_llb) {  in __intel_fbc_cleanup_cfb()
563 		i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);  in __intel_fbc_cleanup_cfb()
564 		kfree(fbc->compressed_llb);  in __intel_fbc_cleanup_cfb()
567 	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);  in __intel_fbc_cleanup_cfb()
572 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_cleanup_cfb()  local
577 	mutex_lock(&fbc->lock);  in intel_fbc_cleanup_cfb()
579 	mutex_unlock(&fbc->lock);  in intel_fbc_cleanup_cfb()
653 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_tracking_covers_screen()  local
670 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,  in intel_fbc_hw_tracking_covers_screen()
672 	effective_w += fbc->state_cache.plane.adjusted_x;  in intel_fbc_hw_tracking_covers_screen()
673 	effective_h += fbc->state_cache.plane.adjusted_y;  in intel_fbc_hw_tracking_covers_screen()
699 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_update_state_cache()  local
700 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_update_state_cache()
749 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_cfb_size_changed()  local
751 	return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >  in intel_fbc_cfb_size_changed()
752 		fbc->compressed_fb.size * fbc->threshold;  in intel_fbc_cfb_size_changed()
757 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_gen9_wa_cfb_stride()  local
758 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_gen9_wa_cfb_stride()
762 		return DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;  in intel_fbc_gen9_wa_cfb_stride()
769 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_gen9_wa_cfb_stride_changed()  local
771 	return fbc->params.gen9_wa_cfb_stride != intel_fbc_gen9_wa_cfb_stride(dev_priv);  in intel_fbc_gen9_wa_cfb_stride_changed()
776 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_can_enable()  local
779 		fbc->no_fbc_reason = "VGPU is active";  in intel_fbc_can_enable()
784 		fbc->no_fbc_reason = "disabled per module param or by default";  in intel_fbc_can_enable()
788 	if (fbc->underrun_detected) {  in intel_fbc_can_enable()
789 		fbc->no_fbc_reason = "underrun detected";  in intel_fbc_can_enable()
799 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_can_activate()  local
800 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_can_activate()
806 		fbc->no_fbc_reason = "primary plane not visible";  in intel_fbc_can_activate()
813 	if (fbc->underrun_detected) {  in intel_fbc_can_activate()
814 		fbc->no_fbc_reason = "underrun detected";  in intel_fbc_can_activate()
819 		fbc->no_fbc_reason = "incompatible mode";  in intel_fbc_can_activate()
824 		fbc->no_fbc_reason = "mode too large for compression";  in intel_fbc_can_activate()
846 		fbc->no_fbc_reason = "framebuffer not tiled or fenced";  in intel_fbc_can_activate()
851 		fbc->no_fbc_reason = "pixel format is invalid";  in intel_fbc_can_activate()
857 		fbc->no_fbc_reason = "rotation unsupported";  in intel_fbc_can_activate()
862 		fbc->no_fbc_reason = "tiling unsupported";  in intel_fbc_can_activate()
867 		fbc->no_fbc_reason = "framebuffer stride not supported";  in intel_fbc_can_activate()
873 		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";  in intel_fbc_can_activate()
880 		fbc->no_fbc_reason = "pixel rate is too big";  in intel_fbc_can_activate()
895 		fbc->no_fbc_reason = "CFB requirements changed";  in intel_fbc_can_activate()
905 	    (fbc->state_cache.plane.adjusted_y & 3)) {  in intel_fbc_can_activate()
906 		fbc->no_fbc_reason = "plane Y offset is misaligned";  in intel_fbc_can_activate()
917 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_get_reg_params()  local
918 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_get_reg_params()
948 	const struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_can_flip_nuke()  local
949 	const struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_can_flip_nuke()
950 	const struct intel_fbc_reg_params *params = &fbc->params;  in intel_fbc_can_flip_nuke()
988 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_pre_update()  local
995 	mutex_lock(&fbc->lock);  in intel_fbc_pre_update()
997 	if (fbc->crtc != crtc)  in intel_fbc_pre_update()
1001 	fbc->flip_pending = true;  in intel_fbc_pre_update()
1019 		if (fbc->activated &&  in intel_fbc_pre_update()
1022 		fbc->activated = false;  in intel_fbc_pre_update()
1025 	mutex_unlock(&fbc->lock);  in intel_fbc_pre_update()
1039 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_disable()  local
1040 	struct intel_crtc *crtc = fbc->crtc;  in __intel_fbc_disable()
1042 	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));  in __intel_fbc_disable()
1043 	drm_WARN_ON(&dev_priv->drm, !fbc->crtc);  in __intel_fbc_disable()
1044 	drm_WARN_ON(&dev_priv->drm, fbc->active);  in __intel_fbc_disable()
1051 	fbc->crtc = NULL;  in __intel_fbc_disable()
1057 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_post_update()  local
1059 	drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));  in __intel_fbc_post_update()
1061 	if (fbc->crtc != crtc)  in __intel_fbc_post_update()
1064 	fbc->flip_pending = false;  in __intel_fbc_post_update()
1073 	intel_fbc_get_reg_params(crtc, &fbc->params);  in __intel_fbc_post_update()
1078 	if (!fbc->busy_bits)  in __intel_fbc_post_update()
1091 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_post_update()  local
1096 	mutex_lock(&fbc->lock);  in intel_fbc_post_update()
1098 	mutex_unlock(&fbc->lock);  in intel_fbc_post_update()
1101 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)  in intel_fbc_get_frontbuffer_bit()  argument
1103 	if (fbc->crtc)  in intel_fbc_get_frontbuffer_bit()
1104 		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;  in intel_fbc_get_frontbuffer_bit()
1106 		return fbc->possible_framebuffer_bits;  in intel_fbc_get_frontbuffer_bit()
1113 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_invalidate()  local
1121 	mutex_lock(&fbc->lock);  in intel_fbc_invalidate()
1123 	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;  in intel_fbc_invalidate()
1125 	if (fbc->crtc && fbc->busy_bits)  in intel_fbc_invalidate()
1128 	mutex_unlock(&fbc->lock);  in intel_fbc_invalidate()
1134 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_flush()  local
1147 	mutex_lock(&fbc->lock);  in intel_fbc_flush()
1149 	fbc->busy_bits &= ~frontbuffer_bits;  in intel_fbc_flush()
1154 	if (!fbc->busy_bits && fbc->crtc &&  in intel_fbc_flush()
1155 	    (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {  in intel_fbc_flush()
1156 		if (fbc->active)  in intel_fbc_flush()
1158 		else if (!fbc->flip_pending)  in intel_fbc_flush()
1159 			__intel_fbc_post_update(fbc->crtc);  in intel_fbc_flush()
1163 	mutex_unlock(&fbc->lock);  in intel_fbc_flush()
1181 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_choose_crtc()  local
1187 	mutex_lock(&fbc->lock);  in intel_fbc_choose_crtc()
1190 	if (fbc->crtc &&  in intel_fbc_choose_crtc()
1191 	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))  in intel_fbc_choose_crtc()
1219 		fbc->no_fbc_reason = "no suitable CRTC for FBC";  in intel_fbc_choose_crtc()
1222 	mutex_unlock(&fbc->lock);  in intel_fbc_choose_crtc()
1244 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_enable()  local
1245 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_enable()
1250 	mutex_lock(&fbc->lock);  in intel_fbc_enable()
1252 	if (fbc->crtc) {  in intel_fbc_enable()
1253 		if (fbc->crtc != crtc ||  in intel_fbc_enable()
1261 	drm_WARN_ON(&dev_priv->drm, fbc->active);  in intel_fbc_enable()
1273 		fbc->no_fbc_reason = "not enough stolen memory";  in intel_fbc_enable()
1281 	fbc->no_fbc_reason = "FBC enabled but not active yet\n";  in intel_fbc_enable()
1283 	fbc->crtc = crtc;  in intel_fbc_enable()
1285 	mutex_unlock(&fbc->lock);  in intel_fbc_enable()
1298 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_disable()  local
1303 	mutex_lock(&fbc->lock);  in intel_fbc_disable()
1304 	if (fbc->crtc == crtc)  in intel_fbc_disable()
1306 	mutex_unlock(&fbc->lock);  in intel_fbc_disable()
1317 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_global_disable()  local
1322 	mutex_lock(&fbc->lock);  in intel_fbc_global_disable()
1323 	if (fbc->crtc) {  in intel_fbc_global_disable()
1324 		drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);  in intel_fbc_global_disable()
1327 	mutex_unlock(&fbc->lock);  in intel_fbc_global_disable()
1333 		container_of(work, struct drm_i915_private, fbc.underrun_work);  in intel_fbc_underrun_work_fn()
1334 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_underrun_work_fn()  local
1336 	mutex_lock(&fbc->lock);  in intel_fbc_underrun_work_fn()
1339 	if (fbc->underrun_detected || !fbc->crtc)  in intel_fbc_underrun_work_fn()
1343 	fbc->underrun_detected = true;  in intel_fbc_underrun_work_fn()
1347 	mutex_unlock(&fbc->lock);  in intel_fbc_underrun_work_fn()
1361 	cancel_work_sync(&dev_priv->fbc.underrun_work);  in intel_fbc_reset_underrun()
1363 	ret = mutex_lock_interruptible(&dev_priv->fbc.lock);  in intel_fbc_reset_underrun()
1367 	if (dev_priv->fbc.underrun_detected) {  in intel_fbc_reset_underrun()
1370 		dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";  in intel_fbc_reset_underrun()
1373 	dev_priv->fbc.underrun_detected = false;  in intel_fbc_reset_underrun()
1374 	mutex_unlock(&dev_priv->fbc.lock);  in intel_fbc_reset_underrun()
1395 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_handle_fifo_underrun_irq()  local
1406 	if (READ_ONCE(fbc->underrun_detected))  in intel_fbc_handle_fifo_underrun_irq()
1409 	schedule_work(&fbc->underrun_work);  in intel_fbc_handle_fifo_underrun_irq()
1463 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_init()  local
1465 	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);  in intel_fbc_init()
1466 	mutex_init(&fbc->lock);  in intel_fbc_init()
1467 	fbc->active = false;  in intel_fbc_init()
1480 		fbc->no_fbc_reason = "unsupported by this chipset";  in intel_fbc_init()