Lines Matching refs:free_pos
106 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_indexed_reg_write()
130 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_indexed_reg_write()
132 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_indexed_reg_write()
135 buf[dsb->free_pos++] = 1; in intel_dsb_indexed_reg_write()
138 buf[dsb->free_pos++] = (DSB_OPCODE_INDEXED_WRITE << in intel_dsb_indexed_reg_write()
143 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
146 buf[dsb->free_pos++] = val; in intel_dsb_indexed_reg_write()
153 if (dsb->free_pos & 0x1) in intel_dsb_indexed_reg_write()
154 buf[dsb->free_pos] = 0; in intel_dsb_indexed_reg_write()
184 if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { in intel_dsb_reg_write()
189 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_reg_write()
190 buf[dsb->free_pos++] = val; in intel_dsb_reg_write()
191 buf[dsb->free_pos++] = (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | in intel_dsb_reg_write()
212 if (!(dsb && dsb->free_pos)) in intel_dsb_commit()
226 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); in intel_dsb_commit()
227 if (tail > dsb->free_pos * 4) in intel_dsb_commit()
228 memset(&dsb->cmd_buf[dsb->free_pos], 0, in intel_dsb_commit()
229 (tail - dsb->free_pos * 4)); in intel_dsb_commit()
248 dsb->free_pos = 0; in intel_dsb_commit()
307 dsb->free_pos = 0; in intel_dsb_prepare()