904 			refclk = dev_priv->dpll.ref_clks.nssc;  in hsw_ddi_wrpll_get_freq()
1063 		i915->dpll.ref_clks.nssc = 24000;  in hsw_update_dpll_ref_clks()
1065 		i915->dpll.ref_clks.nssc = 135000;  in hsw_update_dpll_ref_clks()
1556 				     i915->dpll.ref_clks.nssc,  in skl_ddi_hdmi_pll_dividers()
1583 	int ref_clock = i915->dpll.ref_clks.nssc;  in skl_ddi_wrpll_get_freq()
1776 	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;  in skl_update_dpll_ref_clks()
2221 	return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);  in bxt_ddi_pll_get_freq()
2260 	i915->dpll.ref_clks.nssc = 100000;  in bxt_update_dpll_ref_clks()
2595 					 i915->dpll.ref_clks.nssc);  in cnl_ddi_calculate_wrpll()
2684 	return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc);  in cnl_ddi_wrpll_get_freq()
2831 	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;  in cnl_update_dpll_ref_clks()
2966 		dev_priv->dpll.ref_clks.nssc == 24000 ?  in icl_calc_dp_combo_pll()
2989 		switch (dev_priv->dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
2991 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
3004 		switch (dev_priv->dpll.ref_clks.nssc) {  in icl_calc_tbt_pll()
3006 			MISSING_CASE(dev_priv->dpll.ref_clks.nssc);  in icl_calc_tbt_pll()
3035 	int ref_clock = i915->dpll.ref_clks.nssc;  in icl_wrpll_ref_clock()
3178 	int refclk_khz = dev_priv->dpll.ref_clks.nssc;  in icl_calc_mg_pll_state()
3386 	ref_clock = dev_priv->dpll.ref_clks.nssc;  in icl_ddi_mg_pll_get_freq()
3713 	if (dev_priv->dpll.ref_clks.nssc == 38400) {  in mg_pll_get_hw_state()
4194 	i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;  in icl_update_dpll_ref_clks()