1062 			!(IS_VALLEYVIEW(dev_priv) ||  in intel_power_sequencer_reset()
1111 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pps_get_registers()
1160 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in edp_notify_handler()
1187 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_power()
1200 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_vdd()
1854 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_set_clock()
3908 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_enable_dp()
3918 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_enable_dp()
4582 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_link_down()
6612 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_dp_encoder_reset()
6617 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_encoder_reset()
7114 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_init_panel_power_sequencer_registers()
7166 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_pps_init()
7252 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
7257 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
7673 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_edp_init_connector()
7786 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_init_connector()
7798 	if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||  in intel_dp_init_connector()
7904 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_init()
7925 	else if (IS_VALLEYVIEW(dev_priv))  in intel_dp_init()
7934 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||  in intel_dp_init()