7919 				      pipe_config->pipe_bpp);  in ilk_fdi_compute_config()
7923 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,  in ilk_fdi_compute_config()
7930 	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {  in ilk_fdi_compute_config()
7931 		pipe_config->pipe_bpp -= 2*3;  in ilk_fdi_compute_config()
7934 			    pipe_config->pipe_bpp);  in ilk_fdi_compute_config()
7959 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
8995 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
8999 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
9489 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
9492 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
9495 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
10098 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
10175 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipemisc()
10189 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipemisc()
10724 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
10727 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
10730 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
10733 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
12889 	if (bpp < pipe_config->pipe_bpp) {  in compute_sink_pipe_bpp()
12896 			    pipe_config->pipe_bpp);  in compute_sink_pipe_bpp()
12898 		pipe_config->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
12922 	pipe_config->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
13104 		    pipe_config->pipe_bpp, pipe_config->dither);  in intel_dump_pipe_config()
13389 	base_bpp = pipe_config->pipe_bpp;  in intel_modeset_pipe_config()
13487 	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
13491 		    base_bpp, pipe_config->pipe_bpp, pipe_config->dither);  in intel_modeset_pipe_config()
14025 		PIPE_CONF_CHECK_I(pipe_bpp);  in intel_pipe_config_compare()