7660 	struct intel_cdclk_state *cdclk_state =  in intel_crtc_disable_noatomic()  local
7733 	cdclk_state->min_cdclk[pipe] = 0;  in intel_crtc_disable_noatomic()
7734 	cdclk_state->min_voltage_level[pipe] = 0;  in intel_crtc_disable_noatomic()
7735 	cdclk_state->active_pipes &= ~BIT(pipe);  in intel_crtc_disable_noatomic()
8002 		const struct intel_cdclk_state *cdclk_state;  in hsw_compute_ips_config()  local
8004 		cdclk_state = intel_atomic_get_cdclk_state(state);  in hsw_compute_ips_config()
8005 		if (IS_ERR(cdclk_state))  in hsw_compute_ips_config()
8006 			return PTR_ERR(cdclk_state);  in hsw_compute_ips_config()
8009 		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)  in hsw_compute_ips_config()
12681 			       const struct intel_cdclk_state *cdclk_state)  in hsw_ips_linetime_wm()  argument
12691 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
12723 	const struct intel_cdclk_state *cdclk_state;  in hsw_compute_linetime_wm()  local
12733 	cdclk_state = intel_atomic_get_cdclk_state(state);  in hsw_compute_linetime_wm()
12734 	if (IS_ERR(cdclk_state))  in hsw_compute_linetime_wm()
12735 		return PTR_ERR(cdclk_state);  in hsw_compute_linetime_wm()
12738 						       cdclk_state);  in hsw_compute_linetime_wm()
17573 	struct intel_cdclk_state *cdclk_state =  in intel_modeset_init_hw()  local
17580 	cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;  in intel_modeset_init_hw()
18467 	struct intel_cdclk_state *cdclk_state =  in intel_modeset_readout_hw_state()  local
18501 	dev_priv->active_pipes = cdclk_state->active_pipes =  in intel_modeset_readout_hw_state()
18638 		cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;  in intel_modeset_readout_hw_state()
18639 		cdclk_state->min_voltage_level[crtc->pipe] =  in intel_modeset_readout_hw_state()