1340 	int clock = crtc_state->port_clock;  in icl_pll_to_ddi_clk_sel()
1547 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
1550 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in ddi_dotclock_get()
1553 		dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;  in ddi_dotclock_get()
1555 		dotclock = pipe_config->port_clock;  in ddi_dotclock_get()
1576 		pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,  in intel_ddi_clock_get()
1579 		pipe_config->port_clock =  in intel_ddi_clock_get()
3290 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,  in tgl_ddi_pre_enable_dp()
3363 	tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,  in tgl_ddi_pre_enable_dp()
3437 	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,  in hsw_ddi_pre_enable_dp()
3452 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,  in hsw_ddi_pre_enable_dp()
3530 		tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,  in intel_ddi_pre_enable_hdmi()
3533 		icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,  in intel_ddi_pre_enable_hdmi()
4232 	if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
4234 	else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
4236 	else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
4238 	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
4561 		crtc_state1->port_clock == crtc_state2->port_clock &&  in crtcs_port_sync_compatible()