Lines Matching +full:pre +full:- +full:emphasis
54 u32 trans1; /* balance leg enable, de-emph level */
360 /* BSpec has 2 recommended values - entries 0 and 8.
592 /* Voltage swing pre-emphasis */
606 /* Voltage swing pre-emphasis */
620 /* HDMI Preset VS Pre-emph */
626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
640 /* VS pre-emp Non-trans mV Pre-emph dB */
654 /* VS pre-emp Non-trans mV Pre-emph dB */
668 /* HDMI Preset VS Pre-emph */
674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
724 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
728 /* VS pre-emp */
748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bdw_get_buf_trans_edp()
750 if (dev_priv->vbt.edp.low_vswing) { in bdw_get_buf_trans_edp()
762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_get_buf_trans_dp()
779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in kbl_get_buf_trans_dp()
800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_get_buf_trans_edp()
802 if (dev_priv->vbt.edp.low_vswing) { in skl_get_buf_trans_edp()
856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_buf_trans_dp()
863 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); in intel_ddi_get_buf_trans_dp()
868 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); in intel_ddi_get_buf_trans_dp()
885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_buf_trans_edp()
890 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); in intel_ddi_get_buf_trans_edp()
923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_buf_trans_hdmi()
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_get_buf_trans_edp()
951 if (dev_priv->vbt.edp.low_vswing) { in bxt_get_buf_trans_edp()
969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cnl_get_buf_trans_hdmi()
991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cnl_get_buf_trans_dp()
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cnl_get_buf_trans_edp()
1016 if (dev_priv->vbt.edp.low_vswing) { in cnl_get_buf_trans_edp()
1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_get_combo_buf_trans()
1048 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { in icl_get_combo_buf_trans()
1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ehl_get_combo_buf_trans()
1084 if (dev_priv->vbt.edp.low_vswing) { in ehl_get_combo_buf_trans()
1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_get_combo_buf_trans()
1112 if (dev_priv->vbt.edp.hobl) { in tgl_get_combo_buf_trans()
1115 if (!intel_dp->hobl_failed && rate <= 540000) { in tgl_get_combo_buf_trans()
1125 } else if (dev_priv->vbt.edp.low_vswing) { in tgl_get_combo_buf_trans()
1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_hdmi_level()
1167 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_hdmi_level()
1176 default_entry = n_entries - 1; in intel_ddi_hdmi_level()
1184 default_entry = n_entries - 1; in intel_ddi_hdmi_level()
1187 default_entry = n_entries - 1; in intel_ddi_hdmi_level()
1190 default_entry = n_entries - 1; in intel_ddi_hdmi_level()
1201 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); in intel_ddi_hdmi_level()
1205 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) in intel_ddi_hdmi_level()
1212 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) in intel_ddi_hdmi_level()
1213 level = n_entries - 1; in intel_ddi_hdmi_level()
1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_prepare_dp_ddi_buffers()
1229 enum port port = encoder->port; in intel_prepare_dp_ddi_buffers()
1262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_prepare_hdmi_ddi_buffers()
1265 enum port port = encoder->port; in intel_prepare_hdmi_ddi_buffers()
1270 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) in intel_prepare_hdmi_ddi_buffers()
1272 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) in intel_prepare_hdmi_ddi_buffers()
1273 level = n_entries - 1; in intel_prepare_hdmi_ddi_buffers()
1296 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
1311 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
1317 switch (pll->info->id) { in hsw_pll_to_ddi_pll_sel()
1331 MISSING_CASE(pll->info->id); in hsw_pll_to_ddi_pll_sel()
1339 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1340 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
1341 const enum intel_dpll_id id = pll->info->id; in icl_pll_to_ddi_clk_sel()
1376 * connection to the PCH-located connectors. For this, it is necessary to train
1387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_fdi_link_train()
1388 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in hsw_fdi_link_train()
1395 * - TP1 to TP2 time with the default value in hsw_fdi_link_train()
1396 * - FDI delay to 90h in hsw_fdi_link_train()
1404 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | in hsw_fdi_link_train()
1406 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in hsw_fdi_link_train()
1416 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); in hsw_fdi_link_train()
1418 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()
1420 /* Start the training iterating through available voltages and emphasis, in hsw_fdi_link_train()
1423 /* Configure DP_TP_CTL with auto-training */ in hsw_fdi_link_train()
1435 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); in hsw_fdi_link_train()
1443 /* Enable PCH FDI Receiver with auto-training */ in hsw_fdi_link_train()
1462 drm_dbg_kms(&dev_priv->drm, in hsw_fdi_link_train()
1471 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { in hsw_fdi_link_train()
1472 drm_err(&dev_priv->drm, "FDI link training failed!\n"); in hsw_fdi_link_train()
1515 intel_dp->DP = dig_port->saved_port_bits | in intel_ddi_init_dp_buf_reg()
1517 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1546 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
1547 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1548 &pipe_config->fdi_m_n); in ddi_dotclock_get()
1550 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in ddi_dotclock_get()
1551 &pipe_config->dp_m_n); in ddi_dotclock_get()
1552 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in ddi_dotclock_get()
1553 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
1555 dotclock = pipe_config->port_clock; in ddi_dotclock_get()
1557 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && in ddi_dotclock_get()
1561 if (pipe_config->pixel_multiplier) in ddi_dotclock_get()
1562 dotclock /= pipe_config->pixel_multiplier; in ddi_dotclock_get()
1564 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; in ddi_dotclock_get()
1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_clock_get()
1571 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_clock_get()
1574 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == in intel_ddi_clock_get()
1576 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, in intel_ddi_clock_get()
1577 encoder->port); in intel_ddi_clock_get()
1579 pipe_config->port_clock = in intel_ddi_clock_get()
1580 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); in intel_ddi_clock_get()
1588 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_set_dp_msa()
1589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_set_dp_msa()
1590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_set_dp_msa()
1596 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
1600 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
1614 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
1619 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
1620 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_ddi_set_dp_msa()
1622 if (crtc_state->limited_color_range) in intel_ddi_set_dp_msa()
1630 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_ddi_set_dp_msa()
1663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_transcoder_func_reg_val_get()
1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_transcoder_func_reg_val_get()
1665 enum pipe pipe = crtc->pipe; in intel_ddi_transcoder_func_reg_val_get()
1666 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_transcoder_func_reg_val_get()
1667 enum port port = encoder->port; in intel_ddi_transcoder_func_reg_val_get()
1677 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
1694 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) in intel_ddi_transcoder_func_reg_val_get()
1696 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) in intel_ddi_transcoder_func_reg_val_get()
1702 /* On Haswell, can only use the always-on power well for in intel_ddi_transcoder_func_reg_val_get()
1706 if (crtc_state->pch_pfit.force_thru) in intel_ddi_transcoder_func_reg_val_get()
1724 if (crtc_state->has_hdmi_sink) in intel_ddi_transcoder_func_reg_val_get()
1729 if (crtc_state->hdmi_scrambling) in intel_ddi_transcoder_func_reg_val_get()
1731 if (crtc_state->hdmi_high_tmds_clock_ratio) in intel_ddi_transcoder_func_reg_val_get()
1735 temp |= (crtc_state->fdi_lanes - 1) << 1; in intel_ddi_transcoder_func_reg_val_get()
1738 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
1743 master = crtc_state->mst_master_transcoder; in intel_ddi_transcoder_func_reg_val_get()
1744 drm_WARN_ON(&dev_priv->drm, in intel_ddi_transcoder_func_reg_val_get()
1750 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
1754 crtc_state->master_transcoder != INVALID_TRANSCODER) { in intel_ddi_transcoder_func_reg_val_get()
1756 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); in intel_ddi_transcoder_func_reg_val_get()
1768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_func()
1769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_func()
1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_func()
1773 enum transcoder master_transcoder = crtc_state->master_transcoder; in intel_ddi_enable_transcoder_func()
1801 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_config_transcoder_func()
1802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_config_transcoder_func()
1803 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_func()
1813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_disable_transcoder_func()
1814 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_disable_transcoder_func()
1815 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_func()
1824 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); in intel_ddi_disable_transcoder_func()
1843 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && in intel_ddi_disable_transcoder_func()
1845 drm_dbg_kms(&dev_priv->drm, in intel_ddi_disable_transcoder_func()
1856 struct drm_device *dev = intel_encoder->base.dev; in intel_ddi_toggle_hdcp_signalling()
1863 intel_encoder->power_domain); in intel_ddi_toggle_hdcp_signalling()
1865 return -ENXIO; in intel_ddi_toggle_hdcp_signalling()
1873 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_signalling()
1879 struct drm_device *dev = intel_connector->base.dev; in intel_ddi_connector_get_hw_state()
1882 int type = intel_connector->base.connector_type; in intel_ddi_connector_get_hw_state()
1883 enum port port = encoder->port; in intel_ddi_connector_get_hw_state()
1891 encoder->power_domain); in intel_ddi_connector_get_hw_state()
1895 if (!encoder->get_hw_state(encoder, &pipe)) { in intel_ddi_connector_get_hw_state()
1934 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
1942 struct drm_device *dev = encoder->base.dev; in intel_ddi_get_encoder_pipes()
1944 enum port port = encoder->port; in intel_ddi_get_encoder_pipes()
1954 encoder->power_domain); in intel_ddi_get_encoder_pipes()
2020 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
2022 encoder->base.base.id, encoder->base.name); in intel_ddi_get_encoder_pipes()
2025 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
2027 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
2029 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
2033 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
2034 … "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", in intel_ddi_get_encoder_pipes()
2035 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
2046 drm_err(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
2048 encoder->base.base.id, encoder->base.name, tmp); in intel_ddi_get_encoder_pipes()
2051 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
2065 *pipe = ffs(pipe_mask) - 1; in intel_ddi_get_hw_state()
2078 * However, for non-A AUX ports the corresponding non-EDP transcoders in intel_ddi_main_link_aux_domain()
2085 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : in intel_ddi_main_link_aux_domain()
2092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_power_domains()
2094 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_get_power_domains()
2098 * happen since fake-MST encoders don't set their get_power_domains() in intel_ddi_get_power_domains()
2101 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_get_power_domains()
2108 dig_port->tc_mode != TC_PORT_TBT_ALT) in intel_ddi_get_power_domains()
2110 dig_port->ddi_io_power_domain); in intel_ddi_get_power_domains()
2124 if (crtc_state->dsc.compression_enable) in intel_ddi_get_power_domains()
2132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_pipe_clock()
2133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_pipe_clock()
2134 enum port port = encoder->port; in intel_ddi_enable_pipe_clock()
2135 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_pipe_clock()
2151 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_disable_pipe_clock()
2152 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_pipe_clock()
2184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_ddi_set_iboost()
2205 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) in skl_ddi_set_iboost()
2207 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) in skl_ddi_set_iboost()
2208 level = n_entries - 1; in skl_ddi_set_iboost()
2215 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
2219 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); in skl_ddi_set_iboost()
2221 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
2228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_ddi_vswing_sequence()
2230 enum port port = encoder->port; in bxt_ddi_vswing_sequence()
2240 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) in bxt_ddi_vswing_sequence()
2242 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) in bxt_ddi_vswing_sequence()
2243 level = n_entries - 1; in bxt_ddi_vswing_sequence()
2254 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_dp_voltage_max()
2255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_dp_voltage_max()
2256 enum port port = encoder->port; in intel_ddi_dp_voltage_max()
2262 tgl_get_combo_buf_trans(encoder, encoder->type, in intel_ddi_dp_voltage_max()
2263 intel_dp->link_rate, &n_entries); in intel_ddi_dp_voltage_max()
2265 tgl_get_dkl_buf_trans(encoder, encoder->type, in intel_ddi_dp_voltage_max()
2266 intel_dp->link_rate, &n_entries); in intel_ddi_dp_voltage_max()
2269 ehl_get_combo_buf_trans(encoder, encoder->type, in intel_ddi_dp_voltage_max()
2270 intel_dp->link_rate, &n_entries); in intel_ddi_dp_voltage_max()
2272 icl_get_combo_buf_trans(encoder, encoder->type, in intel_ddi_dp_voltage_max()
2273 intel_dp->link_rate, &n_entries); in intel_ddi_dp_voltage_max()
2275 icl_get_mg_buf_trans(encoder, encoder->type, in intel_ddi_dp_voltage_max()
2276 intel_dp->link_rate, &n_entries); in intel_ddi_dp_voltage_max()
2278 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_dp_voltage_max()
2283 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_dp_voltage_max()
2288 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_dp_voltage_max()
2294 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
2296 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_dp_voltage_max()
2300 return index_to_dp_signal_levels[n_entries - 1] & in intel_ddi_dp_voltage_max()
2305 * We assume that the full set of pre-emphasis values can be
2317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cnl_ddi_vswing_program()
2319 enum port port = encoder->port; in cnl_ddi_vswing_program()
2330 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) in cnl_ddi_vswing_program()
2332 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) in cnl_ddi_vswing_program()
2333 level = n_entries - 1; in cnl_ddi_vswing_program()
2381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cnl_ddi_vswing_sequence()
2382 enum port port = encoder->port; in cnl_ddi_vswing_sequence()
2392 width = intel_dp->lane_count; in cnl_ddi_vswing_sequence()
2393 rate = intel_dp->link_rate; in cnl_ddi_vswing_sequence()
2436 /* 5. Program swing and de-emphasis */ in cnl_ddi_vswing_sequence()
2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_ddi_combo_vswing_program()
2449 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_ddi_combo_vswing_program()
2467 drm_dbg_kms(&dev_priv->drm, in icl_ddi_combo_vswing_program()
2469 level, n_entries - 1); in icl_ddi_combo_vswing_program()
2470 level = n_entries - 1; in icl_ddi_combo_vswing_program()
2477 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); in icl_ddi_combo_vswing_program()
2479 intel_dp->hobl_active ? val : 0); in icl_ddi_combo_vswing_program()
2524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_combo_phy_ddi_vswing_sequence()
2525 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_combo_phy_ddi_vswing_sequence()
2537 width = intel_dp->lane_count; in icl_combo_phy_ddi_vswing_sequence()
2538 rate = intel_dp->link_rate; in icl_combo_phy_ddi_vswing_sequence()
2581 /* 5. Program swing and de-emphasis */ in icl_combo_phy_ddi_vswing_sequence()
2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_mg_phy_ddi_vswing_sequence()
2595 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in icl_mg_phy_ddi_vswing_sequence()
2603 rate = intel_dp->link_rate; in icl_mg_phy_ddi_vswing_sequence()
2610 drm_dbg_kms(&dev_priv->drm, in icl_mg_phy_ddi_vswing_sequence()
2612 level, n_entries - 2); in icl_mg_phy_ddi_vswing_sequence()
2613 level = n_entries - 2; in icl_mg_phy_ddi_vswing_sequence()
2725 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_ddi_vswing_sequence()
2726 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_ddi_vswing_sequence()
2739 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_dkl_phy_ddi_vswing_sequence()
2740 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); in tgl_dkl_phy_ddi_vswing_sequence()
2748 rate = intel_dp->link_rate; in tgl_dkl_phy_ddi_vswing_sequence()
2751 ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate, in tgl_dkl_phy_ddi_vswing_sequence()
2755 level = n_entries - 1; in tgl_dkl_phy_ddi_vswing_sequence()
2792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_ddi_vswing_sequence()
2793 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in tgl_ddi_vswing_sequence()
2811 drm_WARN(&i915->drm, 1, in translate_signal_level()
2812 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", in translate_signal_level()
2820 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level()
2830 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in tgl_set_signal_levels()
2833 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, in tgl_set_signal_levels()
2834 level, encoder->type); in tgl_set_signal_levels()
2840 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in icl_set_signal_levels()
2843 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, in icl_set_signal_levels()
2844 level, encoder->type); in icl_set_signal_levels()
2850 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in cnl_set_signal_levels()
2853 cnl_ddi_vswing_sequence(encoder, level, encoder->type); in cnl_set_signal_levels()
2859 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in bxt_set_signal_levels()
2862 bxt_ddi_vswing_sequence(encoder, level, encoder->type); in bxt_set_signal_levels()
2868 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in hsw_set_signal_levels()
2869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_signal_levels()
2871 enum port port = encoder->port; in hsw_set_signal_levels()
2876 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
2879 intel_dp->DP &= ~DDI_BUF_EMP_MASK; in hsw_set_signal_levels()
2880 intel_dp->DP |= signal_levels; in hsw_set_signal_levels()
2883 skl_ddi_set_iboost(encoder, level, encoder->type); in hsw_set_signal_levels()
2885 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
2909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_map_plls_to_ports()
2910 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_map_plls_to_ports()
2911 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_map_plls_to_ports()
2914 mutex_lock(&dev_priv->dpll.lock); in icl_map_plls_to_ports()
2917 drm_WARN_ON(&dev_priv->drm, in icl_map_plls_to_ports()
2925 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in icl_map_plls_to_ports()
2928 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in icl_map_plls_to_ports()
2950 mutex_unlock(&dev_priv->dpll.lock); in icl_map_plls_to_ports()
2955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_unmap_plls_to_ports()
2956 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in icl_unmap_plls_to_ports()
2959 mutex_lock(&dev_priv->dpll.lock); in icl_unmap_plls_to_ports()
2965 mutex_unlock(&dev_priv->dpll.lock); in icl_unmap_plls_to_ports()
2987 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) in icl_sanitize_port_clk_off()
2990 drm_notice(&dev_priv->drm, in icl_sanitize_port_clk_off()
3000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_sanitize_encoder_pll_mapping()
3008 if (encoder->type == INTEL_OUTPUT_DP_MST) in icl_sanitize_encoder_pll_mapping()
3011 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { in icl_sanitize_encoder_pll_mapping()
3020 if (drm_WARN_ON(&dev_priv->drm, is_mst)) in icl_sanitize_encoder_pll_mapping()
3024 port_mask = BIT(encoder->port); in icl_sanitize_encoder_pll_mapping()
3025 ddi_clk_needed = encoder->base.crtc; in icl_sanitize_encoder_pll_mapping()
3027 if (encoder->type == INTEL_OUTPUT_DSI) { in icl_sanitize_encoder_pll_mapping()
3035 for_each_intel_encoder(&dev_priv->drm, other_encoder) { in icl_sanitize_encoder_pll_mapping()
3039 if (drm_WARN_ON(&dev_priv->drm, in icl_sanitize_encoder_pll_mapping()
3040 port_mask & BIT(other_encoder->port))) in icl_sanitize_encoder_pll_mapping()
3056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_clk_select()
3057 enum port port = encoder->port; in intel_ddi_clk_select()
3060 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_ddi_clk_select()
3062 if (drm_WARN_ON(&dev_priv->drm, !pll)) in intel_ddi_clk_select()
3065 mutex_lock(&dev_priv->dpll.lock); in intel_ddi_clk_select()
3082 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); in intel_ddi_clk_select()
3094 /* DDI -> PLL mapping */ in intel_ddi_clk_select()
3099 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | in intel_ddi_clk_select()
3109 mutex_unlock(&dev_priv->dpll.lock); in intel_ddi_clk_select()
3114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_clk_disable()
3115 enum port port = encoder->port; in intel_ddi_clk_disable()
3139 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_program_mg_dp_mode()
3140 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); in icl_program_mg_dp_mode()
3144 if (dig_port->tc_mode == TC_PORT_TBT_ALT) in icl_program_mg_dp_mode()
3164 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
3168 drm_WARN_ON(&dev_priv->drm, in icl_program_mg_dp_mode()
3169 dig_port->tc_mode != TC_PORT_LEGACY); in icl_program_mg_dp_mode()
3231 if (!crtc_state->fec_enable) in intel_dp_sink_set_fec_ready()
3234 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) in intel_dp_sink_set_fec_ready()
3235 drm_dbg_kms(&i915->drm, in intel_dp_sink_set_fec_ready()
3242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_enable_fec()
3246 if (!crtc_state->fec_enable) in intel_ddi_enable_fec()
3250 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_enable_fec()
3252 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); in intel_ddi_enable_fec()
3254 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, in intel_ddi_enable_fec()
3256 drm_err(&dev_priv->drm, in intel_ddi_enable_fec()
3263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_disable_fec_state()
3267 if (!crtc_state->fec_enable) in intel_ddi_disable_fec_state()
3271 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_disable_fec_state()
3273 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); in intel_ddi_disable_fec_state()
3274 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_disable_fec_state()
3283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_ddi_pre_enable_dp()
3284 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in tgl_ddi_pre_enable_dp()
3288 enum transcoder transcoder = crtc_state->cpu_transcoder; in tgl_ddi_pre_enable_dp()
3290 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
3291 crtc_state->lane_count, is_mst); in tgl_ddi_pre_enable_dp()
3293 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); in tgl_ddi_pre_enable_dp()
3294 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); in tgl_ddi_pre_enable_dp()
3307 * 3. For non-TBT Type-C ports, set FIA lane count in tgl_ddi_pre_enable_dp()
3311 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). in tgl_ddi_pre_enable_dp()
3318 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only in tgl_ddi_pre_enable_dp()
3325 dig_port->tc_mode != TC_PORT_TBT_ALT) in tgl_ddi_pre_enable_dp()
3327 dig_port->ddi_io_power_domain); in tgl_ddi_pre_enable_dp()
3338 * stream or multi-stream master transcoder" can just be performed in tgl_ddi_pre_enable_dp()
3363 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, in tgl_ddi_pre_enable_dp()
3364 encoder->type); in tgl_ddi_pre_enable_dp()
3372 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in tgl_ddi_pre_enable_dp()
3375 crtc_state->lane_count, in tgl_ddi_pre_enable_dp()
3403 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in tgl_ddi_pre_enable_dp()
3424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_ddi_pre_enable_dp()
3425 enum port port = encoder->port; in hsw_ddi_pre_enable_dp()
3432 drm_WARN_ON(&dev_priv->drm, in hsw_ddi_pre_enable_dp()
3435 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
3437 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
3438 crtc_state->lane_count, is_mst); in hsw_ddi_pre_enable_dp()
3445 dig_port->tc_mode != TC_PORT_TBT_ALT) in hsw_ddi_pre_enable_dp()
3447 dig_port->ddi_io_power_domain); in hsw_ddi_pre_enable_dp()
3452 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
3453 level, encoder->type); in hsw_ddi_pre_enable_dp()
3455 cnl_ddi_vswing_sequence(encoder, level, encoder->type); in hsw_ddi_pre_enable_dp()
3457 bxt_ddi_vswing_sequence(encoder, level, encoder->type); in hsw_ddi_pre_enable_dp()
3463 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in hsw_ddi_pre_enable_dp()
3466 crtc_state->lane_count, in hsw_ddi_pre_enable_dp()
3495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_dp()
3518 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_pre_enable_hdmi()
3519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_hdmi()
3525 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); in intel_ddi_pre_enable_hdmi()
3530 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, in intel_ddi_pre_enable_hdmi()
3533 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, in intel_ddi_pre_enable_hdmi()
3547 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable_hdmi()
3548 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
3557 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_enable()
3558 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_pre_enable()
3559 enum pipe pipe = crtc->pipe; in intel_ddi_pre_enable()
3563 * - conn_state will be NULL in intel_ddi_pre_enable()
3564 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_pre_enable()
3565 * - the main connector associated with this port in intel_ddi_pre_enable()
3567 * - crtc_state will be the state of the first stream to in intel_ddi_pre_enable()
3574 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
3592 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) in intel_ddi_pre_enable()
3593 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable()
3594 crtc_state->has_infoframe, in intel_ddi_pre_enable()
3602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_ddi_buf()
3603 enum port port = encoder->port; in intel_disable_ddi_buf()
3617 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_disable_ddi_buf()
3620 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); in intel_disable_ddi_buf()
3635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_dp()
3637 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_post_disable_dp()
3640 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_post_disable_dp()
3654 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_ddi_post_disable_dp()
3673 * From TGL spec: "If single stream or multi-stream master transcoder: in intel_ddi_post_disable_dp()
3684 dig_port->tc_mode != TC_PORT_TBT_ALT) in intel_ddi_post_disable_dp()
3686 dig_port->ddi_io_power_domain); in intel_ddi_post_disable_dp()
3696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi()
3698 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_post_disable_hdmi()
3700 dig_port->set_infoframes(encoder, false, in intel_ddi_post_disable_hdmi()
3708 dig_port->ddi_io_power_domain); in intel_ddi_post_disable_hdmi()
3720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable()
3722 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_post_disable()
3742 * - old_conn_state will be NULL in intel_ddi_post_disable()
3743 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_post_disable()
3744 * - the main connector associated with this port in intel_ddi_post_disable()
3746 * - old_crtc_state will be the state of the last stream to in intel_ddi_post_disable()
3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_fdi_post_disable()
3814 if (!crtc_state->sync_mode_slaves_mask) in trans_port_sync_stop_link_train()
3817 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in trans_port_sync_stop_link_train()
3819 to_intel_encoder(conn_state->best_encoder); in trans_port_sync_stop_link_train()
3820 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); in trans_port_sync_stop_link_train()
3829 if (slave_crtc_state->master_transcoder != in trans_port_sync_stop_link_train()
3830 crtc_state->cpu_transcoder) in trans_port_sync_stop_link_train()
3846 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_dp()
3848 enum port port = encoder->port; in intel_enable_ddi_dp()
3858 if (crtc_state->has_audio) in intel_enable_ddi_dp()
3876 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); in gen9_chicken_trans_reg_by_port()
3878 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_hdmi()
3891 struct drm_connector *connector = conn_state->connector; in intel_enable_ddi_hdmi()
3892 enum port port = encoder->port; in intel_enable_ddi_hdmi()
3895 crtc_state->hdmi_high_tmds_clock_ratio, in intel_enable_ddi_hdmi()
3896 crtc_state->hdmi_scrambling)) in intel_enable_ddi_hdmi()
3897 drm_dbg_kms(&dev_priv->drm, in intel_enable_ddi_hdmi()
3899 connector->base.id, connector->name); in intel_enable_ddi_hdmi()
3936 /* In HDMI/DVI mode, the port width, and swing/emphasis values in intel_enable_ddi_hdmi()
3941 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); in intel_enable_ddi_hdmi()
3943 if (crtc_state->has_audio) in intel_enable_ddi_hdmi()
3952 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in intel_enable_ddi()
3966 if (conn_state->content_protection == in intel_enable_ddi()
3968 intel_hdcp_enable(to_intel_connector(conn_state->connector), in intel_enable_ddi()
3969 crtc_state->cpu_transcoder, in intel_enable_ddi()
3970 (u8)conn_state->hdcp_content_type); in intel_enable_ddi()
3980 intel_dp->link_trained = false; in intel_disable_ddi_dp()
3982 if (old_crtc_state->has_audio) in intel_disable_ddi_dp()
3999 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_disable_ddi_hdmi()
4000 struct drm_connector *connector = old_conn_state->connector; in intel_disable_ddi_hdmi()
4002 if (old_crtc_state->has_audio) in intel_disable_ddi_hdmi()
4008 drm_dbg_kms(&i915->drm, in intel_disable_ddi_hdmi()
4010 connector->base.id, connector->name); in intel_disable_ddi_hdmi()
4018 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); in intel_disable_ddi()
4065 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
4067 drm_WARN_ON(state->base.dev, crtc && crtc->active); in intel_ddi_update_prepare()
4071 if (crtc_state && crtc_state->hw.active) in intel_ddi_update_prepare()
4089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_pll_enable()
4091 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); in intel_ddi_pre_pll_enable()
4095 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
4101 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) in intel_ddi_pre_pll_enable()
4104 * Type-C ports. Skip this step for TBT. in intel_ddi_pre_pll_enable()
4106 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
4109 crtc_state->lane_lat_optim_mask); in intel_ddi_pre_pll_enable()
4115 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_prepare_link_retrain()
4116 enum port port = dig_port->base.port; in intel_ddi_prepare_link_retrain()
4120 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_prepare_link_retrain()
4132 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); in intel_ddi_prepare_link_retrain()
4133 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_prepare_link_retrain()
4140 if (intel_dp->link_mst) in intel_ddi_prepare_link_retrain()
4144 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_ddi_prepare_link_retrain()
4147 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); in intel_ddi_prepare_link_retrain()
4148 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_prepare_link_retrain()
4150 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
4151 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in intel_ddi_prepare_link_retrain()
4161 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); in intel_ddi_set_link_train()
4164 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_set_link_train()
4185 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); in intel_ddi_set_link_train()
4190 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_idle_link_train()
4191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_idle_link_train()
4192 enum port port = encoder->port; in intel_ddi_set_idle_link_train()
4195 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); in intel_ddi_set_idle_link_train()
4198 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); in intel_ddi_set_idle_link_train()
4203 * issue where we enable the pipe while not in idle link-training mode. in intel_ddi_set_idle_link_train()
4210 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, in intel_ddi_set_idle_link_train()
4212 drm_err(&dev_priv->drm, in intel_ddi_set_idle_link_train()
4232 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) in intel_ddi_compute_min_voltage_level()
4233 crtc_state->min_voltage_level = 2; in intel_ddi_compute_min_voltage_level()
4234 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) in intel_ddi_compute_min_voltage_level()
4235 crtc_state->min_voltage_level = 3; in intel_ddi_compute_min_voltage_level()
4236 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) in intel_ddi_compute_min_voltage_level()
4237 crtc_state->min_voltage_level = 1; in intel_ddi_compute_min_voltage_level()
4238 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) in intel_ddi_compute_min_voltage_level()
4239 crtc_state->min_voltage_level = 2; in intel_ddi_compute_min_voltage_level()
4266 return master_select - 1; in bdw_transcoder_master_readout()
4271 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in bdw_get_trans_port_sync_config()
4276 crtc_state->master_transcoder = in bdw_get_trans_port_sync_config()
4277 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
4291 crtc_state->cpu_transcoder) in bdw_get_trans_port_sync_config()
4292 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); in bdw_get_trans_port_sync_config()
4297 drm_WARN_ON(&dev_priv->drm, in bdw_get_trans_port_sync_config()
4298 crtc_state->master_transcoder != INVALID_TRANSCODER && in bdw_get_trans_port_sync_config()
4299 crtc_state->sync_mode_slaves_mask); in bdw_get_trans_port_sync_config()
4305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_config()
4306 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_get_config()
4307 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
4312 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
4327 pipe_config->hw.adjusted_mode.flags |= flags; in intel_ddi_get_config()
4331 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
4334 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
4337 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
4340 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
4348 pipe_config->has_hdmi_sink = true; in intel_ddi_get_config()
4350 pipe_config->infoframes.enable |= in intel_ddi_get_config()
4353 if (pipe_config->infoframes.enable) in intel_ddi_get_config()
4354 pipe_config->has_infoframe = true; in intel_ddi_get_config()
4357 pipe_config->hdmi_scrambling = true; in intel_ddi_get_config()
4359 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_ddi_get_config()
4362 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_get_config()
4363 pipe_config->lane_count = 4; in intel_ddi_get_config()
4366 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_get_config()
4369 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_get_config()
4370 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_get_config()
4372 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_get_config()
4373 pipe_config->lane_count = in intel_ddi_get_config()
4381 dp_tp_ctl = DP_TP_CTL(encoder->port); in intel_ddi_get_config()
4383 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); in intel_ddi_get_config()
4385 pipe_config->fec_enable = in intel_ddi_get_config()
4388 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_config()
4390 encoder->base.base.id, encoder->base.name, in intel_ddi_get_config()
4391 pipe_config->fec_enable); in intel_ddi_get_config()
4394 pipe_config->infoframes.enable |= in intel_ddi_get_config()
4399 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_get_config()
4400 pipe_config->lane_count = in intel_ddi_get_config()
4404 pipe_config->mst_master_transcoder = in intel_ddi_get_config()
4409 pipe_config->infoframes.enable |= in intel_ddi_get_config()
4419 pipe_config->mst_master_transcoder : in intel_ddi_get_config()
4420 pipe_config->cpu_transcoder; in intel_ddi_get_config()
4422 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); in intel_ddi_get_config()
4423 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); in intel_ddi_get_config()
4426 pipe_config->has_audio = in intel_ddi_get_config()
4429 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && in intel_ddi_get_config()
4430 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
4444 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_config()
4445 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", in intel_ddi_get_config()
4446 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_ddi_get_config()
4447 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_ddi_get_config()
4453 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
4462 &pipe_config->infoframes.avi); in intel_ddi_get_config()
4465 &pipe_config->infoframes.spd); in intel_ddi_get_config()
4468 &pipe_config->infoframes.hdmi); in intel_ddi_get_config()
4471 &pipe_config->infoframes.drm); in intel_ddi_get_config()
4485 switch (conn_state->connector->connector_type) { in intel_ddi_compute_output_type()
4493 MISSING_CASE(conn_state->connector->connector_type); in intel_ddi_compute_output_type()
4502 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_compute_config()
4503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_compute_config()
4504 enum port port = encoder->port; in intel_ddi_compute_config()
4508 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
4519 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4520 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_ddi_compute_config()
4521 pipe_config->pch_pfit.force_thru = in intel_ddi_compute_config()
4522 pipe_config->pch_pfit.enabled || in intel_ddi_compute_config()
4523 pipe_config->crc_enabled; in intel_ddi_compute_config()
4526 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
4527 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
4541 mode1->clock == mode2->clock; /* we want an exact match */ in mode_equal()
4547 return m_n_1->tu == m_n_2->tu && in m_n_equal()
4548 m_n_1->gmch_m == m_n_2->gmch_m && in m_n_equal()
4549 m_n_1->gmch_n == m_n_2->gmch_n && in m_n_equal()
4550 m_n_1->link_m == m_n_2->link_m && in m_n_equal()
4551 m_n_1->link_n == m_n_2->link_n; in m_n_equal()
4557 return crtc_state1->hw.active && crtc_state2->hw.active && in crtcs_port_sync_compatible()
4558 crtc_state1->output_types == crtc_state2->output_types && in crtcs_port_sync_compatible()
4559 crtc_state1->output_format == crtc_state2->output_format && in crtcs_port_sync_compatible()
4560 crtc_state1->lane_count == crtc_state2->lane_count && in crtcs_port_sync_compatible()
4561 crtc_state1->port_clock == crtc_state2->port_clock && in crtcs_port_sync_compatible()
4562 mode_equal(&crtc_state1->hw.adjusted_mode, in crtcs_port_sync_compatible()
4563 &crtc_state2->hw.adjusted_mode) && in crtcs_port_sync_compatible()
4564 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
4573 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); in intel_ddi_port_sync_transcoders()
4575 to_intel_atomic_state(ref_crtc_state->uapi.state); in intel_ddi_port_sync_transcoders()
4589 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { in intel_ddi_port_sync_transcoders()
4590 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_ddi_port_sync_transcoders()
4596 if (!connector->has_tile || in intel_ddi_port_sync_transcoders()
4597 connector->tile_group->id != in intel_ddi_port_sync_transcoders()
4605 transcoders |= BIT(crtc_state->cpu_transcoder); in intel_ddi_port_sync_transcoders()
4615 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_compute_config_late()
4616 struct drm_connector *connector = conn_state->connector; in intel_ddi_compute_config_late()
4619 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", in intel_ddi_compute_config_late()
4620 encoder->base.base.id, encoder->base.name, in intel_ddi_compute_config_late()
4621 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
4623 if (connector->has_tile) in intel_ddi_compute_config_late()
4625 connector->tile_group->id); in intel_ddi_compute_config_late()
4632 crtc_state->master_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config_late()
4634 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; in intel_ddi_compute_config_late()
4636 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
4637 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_ddi_compute_config_late()
4638 crtc_state->sync_mode_slaves_mask = in intel_ddi_compute_config_late()
4639 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); in intel_ddi_compute_config_late()
4663 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_init_dp_connector()
4665 enum port port = dig_port->base.port; in intel_ddi_init_dp_connector()
4671 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4672 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4673 dig_port->dp.set_link_train = intel_ddi_set_link_train; in intel_ddi_init_dp_connector()
4674 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; in intel_ddi_init_dp_connector()
4677 dig_port->dp.set_signal_levels = tgl_set_signal_levels; in intel_ddi_init_dp_connector()
4679 dig_port->dp.set_signal_levels = icl_set_signal_levels; in intel_ddi_init_dp_connector()
4681 dig_port->dp.set_signal_levels = cnl_set_signal_levels; in intel_ddi_init_dp_connector()
4683 dig_port->dp.set_signal_levels = bxt_set_signal_levels; in intel_ddi_init_dp_connector()
4685 dig_port->dp.set_signal_levels = hsw_set_signal_levels; in intel_ddi_init_dp_connector()
4687 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; in intel_ddi_init_dp_connector()
4688 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; in intel_ddi_init_dp_connector()
4691 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); in intel_ddi_init_dp_connector()
4692 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); in intel_ddi_init_dp_connector()
4710 state = drm_atomic_state_alloc(crtc->dev); in modeset_pipe()
4712 return -ENOMEM; in modeset_pipe()
4714 state->acquire_ctx = ctx; in modeset_pipe()
4722 crtc_state->connectors_changed = true; in modeset_pipe()
4734 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_reset_link()
4736 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_reset_link()
4738 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); in intel_hdmi_reset_link()
4745 if (!connector || connector->base.status != connector_status_connected) in intel_hdmi_reset_link()
4748 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_hdmi_reset_link()
4753 conn_state = connector->base.state; in intel_hdmi_reset_link()
4755 crtc = to_intel_crtc(conn_state->crtc); in intel_hdmi_reset_link()
4759 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_hdmi_reset_link()
4763 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
4765 drm_WARN_ON(&dev_priv->drm, in intel_hdmi_reset_link()
4768 if (!crtc_state->hw.active) in intel_hdmi_reset_link()
4771 if (!crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4772 !crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4775 if (conn_state->commit && in intel_hdmi_reset_link()
4776 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_hdmi_reset_link()
4781 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4787 crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4789 crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4801 return modeset_pipe(&crtc->base, ctx); in intel_hdmi_reset_link()
4808 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_hotplug()
4810 enum phy phy = intel_port_to_phy(i915, encoder->port); in intel_ddi_hotplug()
4821 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) in intel_ddi_hotplug()
4826 if (ret == -EDEADLK) { in intel_ddi_hotplug()
4836 drm_WARN(encoder->base.dev, ret, in intel_ddi_hotplug()
4840 * Unpowered type-c dongles can take some time to boot and be in intel_ddi_hotplug()
4855 * Type-c connectors which get their HPD signal deasserted then in intel_ddi_hotplug()
4858 * becomes functional. Retry the detection for 5 seconds on type-c in intel_ddi_hotplug()
4862 connector->hotplug_retries < (is_tc ? 5 : 1) && in intel_ddi_hotplug()
4863 !dig_port->dp.is_mst) in intel_ddi_hotplug()
4871 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in lpt_digital_port_connected()
4872 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_digital_port_connected()
4880 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bdw_digital_port_connected()
4888 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4897 enum port port = dig_port->base.port; in intel_ddi_init_hdmi_connector()
4903 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4911 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_a_force_4_lanes()
4913 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4916 if (dig_port->saved_port_bits & DDI_A_4_LANES) in intel_ddi_a_force_4_lanes()
4940 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_max_lanes()
4941 enum port port = dig_port->base.port; in intel_ddi_max_lanes()
4961 drm_dbg_kms(&dev_priv->drm, in intel_ddi_max_lanes()
4963 dig_port->saved_port_bits |= DDI_A_4_LANES; in intel_ddi_max_lanes()
4972 return i915->hti_state & HDPORT_ENABLED && in hti_uses_phy()
4973 (i915->hti_state & HDPORT_PHY_USED_DP(phy) || in hti_uses_phy()
4974 i915->hti_state & HDPORT_PHY_USED_HDMI(phy)); in hti_uses_phy()
4981 return HPD_PORT_TC1 + port - PORT_D; in tgl_hpd_pin()
4983 return HPD_PORT_A + port - PORT_A; in tgl_hpd_pin()
4993 return HPD_PORT_C + port - PORT_D; in rkl_hpd_pin()
4995 return HPD_PORT_A + port - PORT_A; in rkl_hpd_pin()
5002 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
5004 return HPD_PORT_A + port - PORT_A; in icl_hpd_pin()
5016 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
5025 return HPD_PORT_A + port - PORT_A; in cnl_hpd_pin()
5042 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
5060 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
5065 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5075 encoder = &dig_port->base; in intel_ddi_init()
5077 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5080 mutex_init(&dig_port->hdcp_mutex); in intel_ddi_init()
5081 dig_port->num_hdcp_streams = 0; in intel_ddi_init()
5083 encoder->hotplug = intel_ddi_hotplug; in intel_ddi_init()
5084 encoder->compute_output_type = intel_ddi_compute_output_type; in intel_ddi_init()
5085 encoder->compute_config = intel_ddi_compute_config; in intel_ddi_init()
5086 encoder->compute_config_late = intel_ddi_compute_config_late; in intel_ddi_init()
5087 encoder->enable = intel_enable_ddi; in intel_ddi_init()
5088 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; in intel_ddi_init()
5089 encoder->pre_enable = intel_ddi_pre_enable; in intel_ddi_init()
5090 encoder->disable = intel_disable_ddi; in intel_ddi_init()
5091 encoder->post_disable = intel_ddi_post_disable; in intel_ddi_init()
5092 encoder->update_pipe = intel_ddi_update_pipe; in intel_ddi_init()
5093 encoder->get_hw_state = intel_ddi_get_hw_state; in intel_ddi_init()
5094 encoder->get_config = intel_ddi_get_config; in intel_ddi_init()
5095 encoder->suspend = intel_dp_encoder_suspend; in intel_ddi_init()
5096 encoder->get_power_domains = intel_ddi_get_power_domains; in intel_ddi_init()
5098 encoder->type = INTEL_OUTPUT_DDI; in intel_ddi_init()
5099 encoder->power_domain = intel_port_to_power_domain(port); in intel_ddi_init()
5100 encoder->port = port; in intel_ddi_init()
5101 encoder->cloneable = 0; in intel_ddi_init()
5102 encoder->pipe_mask = ~0; in intel_ddi_init()
5105 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); in intel_ddi_init()
5107 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); in intel_ddi_init()
5109 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); in intel_ddi_init()
5111 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); in intel_ddi_init()
5113 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); in intel_ddi_init()
5115 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); in intel_ddi_init()
5118 dig_port->saved_port_bits = in intel_ddi_init()
5122 dig_port->saved_port_bits = in intel_ddi_init()
5126 dig_port->dp.output_reg = INVALID_MMIO_REG; in intel_ddi_init()
5127 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
5128 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); in intel_ddi_init()
5137 encoder->update_prepare = intel_ddi_update_prepare; in intel_ddi_init()
5138 encoder->update_complete = intel_ddi_update_complete; in intel_ddi_init()
5141 drm_WARN_ON(&dev_priv->drm, port > PORT_I); in intel_ddi_init()
5142 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + in intel_ddi_init()
5143 port - PORT_A; in intel_ddi_init()
5149 dig_port->hpd_pulse = intel_dp_hpd_pulse; in intel_ddi_init()
5152 /* In theory we don't need the encoder->type check, but leave it just in in intel_ddi_init()
5154 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { in intel_ddi_init()
5162 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5170 drm_err(&dev_priv->drm, in intel_ddi_init()
5177 dig_port->connected = intel_tc_port_connected; in intel_ddi_init()
5179 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5182 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5184 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5187 dig_port->connected = hsw_digital_port_connected; in intel_ddi_init()
5189 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5197 drm_encoder_cleanup(&encoder->base); in intel_ddi_init()