Lines Matching full:phy
41 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in cnl_get_procmon_ref_values() argument
51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
77 enum phy phy) in cnl_set_procmon_ref_values() argument
82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_set_procmon_ref_values()
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); in cnl_set_procmon_ref_values()
89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in cnl_set_procmon_ref_values()
90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in cnl_set_procmon_ref_values()
94 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
101 "Combo PHY %c reg %08x state mismatch: " in check_phy_reg()
103 phy_name(phy), in check_phy_reg()
112 enum phy phy) in cnl_verify_procmon_ref_values() argument
117 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_verify_procmon_ref_values()
119 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in cnl_verify_procmon_ref_values()
121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in cnl_verify_procmon_ref_values()
123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in cnl_verify_procmon_ref_values()
137 enum phy phy = PHY_A; in cnl_combo_phy_verify_state() local
143 ret = cnl_verify_procmon_ref_values(dev_priv, phy); in cnl_combo_phy_verify_state()
145 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, in cnl_combo_phy_verify_state()
177 "Combo PHY HW state changed unexpectedly.\n"); in cnl_combo_phys_uninit()
184 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
187 * Some platforms only expect PHY_MISC to be programmed for PHY-A and in has_phy_misc()
188 * PHY-B and may not even have instances of the register for the in has_phy_misc()
189 * other combo PHY's. in has_phy_misc()
193 return phy < PHY_C; in has_phy_misc()
199 enum phy phy) in icl_combo_phy_enabled() argument
201 /* The PHY C added by EHL has no PHY_MISC register */ in icl_combo_phy_enabled()
202 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
203 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
205 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
207 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
218 * the PHY. So if combo PHY A is wired up to drive an external in ehl_vbt_ddi_d_present()
232 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); in ehl_vbt_ddi_d_present()
237 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
249 * We must set the IREFGEN bit for any PHY acting as a master in phy_is_master()
250 * to another PHY. in phy_is_master()
252 if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C) in phy_is_master()
255 return phy == PHY_A; in phy_is_master()
259 enum phy phy) in icl_combo_phy_verify_state() argument
264 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
268 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy), in icl_combo_phy_verify_state()
274 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy), in icl_combo_phy_verify_state()
279 ret &= cnl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
281 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
282 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
289 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
295 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
302 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
347 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); in intel_combo_phy_power_up_lanes()
350 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); in intel_combo_phy_power_up_lanes()
355 enum phy phy; in icl_combo_phys_init() local
357 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
360 if (icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_init()
362 "Combo PHY %c already enabled, won't reprogram it.\n", in icl_combo_phys_init()
363 phy_name(phy)); in icl_combo_phys_init()
367 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
371 * EHL's combo PHY A can be hooked up to either an external in icl_combo_phys_init()
374 * can't be changed on the fly, so initialize the PHY's mux in icl_combo_phys_init()
378 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
379 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) { in icl_combo_phys_init()
387 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
391 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy)); in icl_combo_phys_init()
395 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
397 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); in icl_combo_phys_init()
400 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
403 cnl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
405 if (phy_is_master(dev_priv, phy)) { in icl_combo_phys_init()
406 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); in icl_combo_phys_init()
408 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); in icl_combo_phys_init()
411 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_init()
413 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_init()
415 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); in icl_combo_phys_init()
417 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); in icl_combo_phys_init()
423 enum phy phy; in icl_combo_phys_uninit() local
425 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
428 if (phy == PHY_A && in icl_combo_phys_uninit()
429 !icl_combo_phy_verify_state(dev_priv, phy)) in icl_combo_phys_uninit()
431 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
432 phy_name(phy)); in icl_combo_phys_uninit()
434 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
437 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_uninit()
439 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_uninit()
442 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); in icl_combo_phys_uninit()
444 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); in icl_combo_phys_uninit()