Lines Matching refs:dev_priv
60 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
66 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
72 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
78 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
84 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
90 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
96 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
99 struct pci_dev *pdev = dev_priv->drm.pdev; in i85x_get_cdclk()
138 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
141 struct pci_dev *pdev = dev_priv->drm.pdev; in i915gm_get_cdclk()
162 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, in i945gm_get_cdclk() argument
165 struct pci_dev *pdev = dev_priv->drm.pdev; in i945gm_get_cdclk()
186 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) in intel_hpll_vco() argument
230 if (IS_GM45(dev_priv)) in intel_hpll_vco()
232 else if (IS_G45(dev_priv)) in intel_hpll_vco()
234 else if (IS_I965GM(dev_priv)) in intel_hpll_vco()
236 else if (IS_PINEVIEW(dev_priv)) in intel_hpll_vco()
238 else if (IS_G33(dev_priv)) in intel_hpll_vco()
243 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
244 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
248 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
251 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
256 static void g33_get_cdclk(struct drm_i915_private *dev_priv, in g33_get_cdclk() argument
259 struct pci_dev *pdev = dev_priv->drm.pdev; in g33_get_cdclk()
268 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
299 drm_err(&dev_priv->drm, in g33_get_cdclk()
305 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, in pnv_get_cdclk() argument
308 struct pci_dev *pdev = dev_priv->drm.pdev; in pnv_get_cdclk()
327 drm_err(&dev_priv->drm, in pnv_get_cdclk()
339 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, in i965gm_get_cdclk() argument
342 struct pci_dev *pdev = dev_priv->drm.pdev; in i965gm_get_cdclk()
350 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
378 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
384 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, in gm45_get_cdclk() argument
387 struct pci_dev *pdev = dev_priv->drm.pdev; in gm45_get_cdclk()
391 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
407 drm_err(&dev_priv->drm, in gm45_get_cdclk()
415 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, in hsw_get_cdclk() argument
418 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
423 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
427 else if (IS_HSW_ULT(dev_priv)) in hsw_get_cdclk()
433 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in vlv_calc_cdclk() argument
435 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
443 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
453 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
455 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
468 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
472 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, in vlv_get_cdclk() argument
477 vlv_iosf_sb_get(dev_priv, in vlv_get_cdclk()
480 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
481 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
485 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
487 vlv_iosf_sb_put(dev_priv, in vlv_get_cdclk()
490 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
498 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
502 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
507 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
509 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
521 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
524 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
531 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
532 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
535 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, in vlv_set_cdclk() argument
561 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
563 vlv_iosf_sb_get(dev_priv, in vlv_set_cdclk()
568 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
571 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
572 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
575 drm_err(&dev_priv->drm, in vlv_set_cdclk()
582 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
586 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
589 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
591 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
594 drm_err(&dev_priv->drm, in vlv_set_cdclk()
599 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in vlv_set_cdclk()
610 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
612 vlv_iosf_sb_put(dev_priv, in vlv_set_cdclk()
617 intel_update_cdclk(dev_priv); in vlv_set_cdclk()
619 vlv_program_pfi_credits(dev_priv); in vlv_set_cdclk()
621 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
624 static void chv_set_cdclk(struct drm_i915_private *dev_priv, in chv_set_cdclk() argument
649 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
651 vlv_punit_get(dev_priv); in chv_set_cdclk()
652 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
655 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
656 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
659 drm_err(&dev_priv->drm, in chv_set_cdclk()
663 vlv_punit_put(dev_priv); in chv_set_cdclk()
665 intel_update_cdclk(dev_priv); in chv_set_cdclk()
667 vlv_program_pfi_credits(dev_priv); in chv_set_cdclk()
669 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
699 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, in bdw_get_cdclk() argument
702 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
707 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
726 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, in bdw_set_cdclk() argument
734 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
735 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
743 ret = sandybridge_pcode_write(dev_priv, in bdw_set_cdclk()
746 drm_err(&dev_priv->drm, in bdw_set_cdclk()
751 val = intel_de_read(dev_priv, LCPLL_CTL); in bdw_set_cdclk()
753 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
759 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
761 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
763 val = intel_de_read(dev_priv, LCPLL_CTL); in bdw_set_cdclk()
784 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
786 val = intel_de_read(dev_priv, LCPLL_CTL); in bdw_set_cdclk()
788 intel_de_write(dev_priv, LCPLL_CTL, val); in bdw_set_cdclk()
790 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
792 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
794 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
797 intel_de_write(dev_priv, CDCLK_FREQ, in bdw_set_cdclk()
800 intel_update_cdclk(dev_priv); in bdw_set_cdclk()
838 static void skl_dpll0_update(struct drm_i915_private *dev_priv, in skl_dpll0_update() argument
846 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
850 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
853 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_update()
855 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
879 static void skl_get_cdclk(struct drm_i915_private *dev_priv, in skl_get_cdclk() argument
884 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
891 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_get_cdclk()
946 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, in skl_set_preferred_cdclk_vco() argument
949 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
951 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
954 intel_update_max_cdclk(dev_priv); in skl_set_preferred_cdclk_vco()
957 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
961 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_enable()
972 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
984 intel_de_write(dev_priv, DPLL_CTRL1, val); in skl_dpll0_enable()
985 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
987 intel_de_write(dev_priv, LCPLL1_CTL, in skl_dpll0_enable()
988 intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE); in skl_dpll0_enable()
990 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
991 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
993 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
996 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
999 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) in skl_dpll0_disable() argument
1001 intel_de_write(dev_priv, LCPLL1_CTL, in skl_dpll0_disable()
1002 intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); in skl_dpll0_disable()
1003 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1004 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1006 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
1009 static void skl_set_cdclk(struct drm_i915_private *dev_priv, in skl_set_cdclk() argument
1026 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1027 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1029 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1034 drm_err(&dev_priv->drm, in skl_set_cdclk()
1042 drm_WARN_ON(&dev_priv->drm, in skl_set_cdclk()
1043 cdclk != dev_priv->cdclk.hw.bypass); in skl_set_cdclk()
1044 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_set_cdclk()
1063 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1064 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1065 skl_dpll0_disable(dev_priv); in skl_set_cdclk()
1067 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1069 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1073 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1078 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1079 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1081 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1082 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1089 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1093 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1094 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1097 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1100 intel_update_cdclk(dev_priv); in skl_set_cdclk()
1103 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) in skl_sanitize_cdclk() argument
1112 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1115 intel_update_cdclk(dev_priv); in skl_sanitize_cdclk()
1116 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1119 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1120 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1129 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_sanitize_cdclk()
1131 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1137 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1140 dev_priv->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1142 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1145 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) in skl_cdclk_init_hw() argument
1149 skl_sanitize_cdclk(dev_priv); in skl_cdclk_init_hw()
1151 if (dev_priv->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1152 dev_priv->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1157 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1158 skl_set_preferred_cdclk_vco(dev_priv, in skl_cdclk_init_hw()
1159 dev_priv->cdclk.hw.vco); in skl_cdclk_init_hw()
1163 cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_init_hw()
1165 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1171 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1174 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in skl_cdclk_uninit_hw() argument
1176 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in skl_cdclk_uninit_hw()
1182 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1236 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in bxt_calc_cdclk() argument
1238 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk()
1242 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk()
1246 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1248 min_cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk()
1252 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1254 const struct intel_cdclk_vals *table = dev_priv->cdclk.table; in bxt_calc_cdclk_pll_vco()
1257 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1261 if (table[i].refclk == dev_priv->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1263 return dev_priv->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1265 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1266 cdclk, dev_priv->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1319 static void cnl_readout_refclk(struct drm_i915_private *dev_priv, in cnl_readout_refclk() argument
1322 if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) in cnl_readout_refclk()
1328 static void icl_readout_refclk(struct drm_i915_private *dev_priv, in icl_readout_refclk() argument
1331 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1349 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, in bxt_de_pll_readout() argument
1354 if (INTEL_GEN(dev_priv) >= 11) in bxt_de_pll_readout()
1355 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1356 else if (IS_CANNONLAKE(dev_priv)) in bxt_de_pll_readout()
1357 cnl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1361 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1376 if (INTEL_GEN(dev_priv) >= 10) in bxt_de_pll_readout()
1379 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1384 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, in bxt_get_cdclk() argument
1390 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1392 if (INTEL_GEN(dev_priv) >= 12) in bxt_get_cdclk()
1394 else if (INTEL_GEN(dev_priv) >= 11) in bxt_get_cdclk()
1404 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1411 drm_WARN(&dev_priv->drm, in bxt_get_cdclk()
1412 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, in bxt_get_cdclk()
1420 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, in bxt_get_cdclk()
1437 dev_priv->display.calc_voltage_level(cdclk_config->cdclk); in bxt_get_cdclk()
1440 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) in bxt_de_pll_disable() argument
1442 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1445 if (intel_de_wait_for_clear(dev_priv, in bxt_de_pll_disable()
1447 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1449 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1452 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1454 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1457 val = intel_de_read(dev_priv, BXT_DE_PLL_CTL); in bxt_de_pll_enable()
1460 intel_de_write(dev_priv, BXT_DE_PLL_CTL, val); in bxt_de_pll_enable()
1462 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1465 if (intel_de_wait_for_set(dev_priv, in bxt_de_pll_enable()
1467 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1469 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1472 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) in cnl_cdclk_pll_disable() argument
1476 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in cnl_cdclk_pll_disable()
1478 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in cnl_cdclk_pll_disable()
1481 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) in cnl_cdclk_pll_disable()
1482 drm_err(&dev_priv->drm, in cnl_cdclk_pll_disable()
1485 dev_priv->cdclk.hw.vco = 0; in cnl_cdclk_pll_disable()
1488 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in cnl_cdclk_pll_enable() argument
1490 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in cnl_cdclk_pll_enable()
1494 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in cnl_cdclk_pll_enable()
1497 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in cnl_cdclk_pll_enable()
1500 if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) in cnl_cdclk_pll_enable()
1501 drm_err(&dev_priv->drm, in cnl_cdclk_pll_enable()
1504 dev_priv->cdclk.hw.vco = vco; in cnl_cdclk_pll_enable()
1507 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1509 if (INTEL_GEN(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1514 } else if (INTEL_GEN(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1527 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, in bxt_set_cdclk() argument
1537 if (INTEL_GEN(dev_priv) >= 10) in bxt_set_cdclk()
1538 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1547 ret = sandybridge_pcode_write_timeout(dev_priv, in bxt_set_cdclk()
1552 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1561 drm_WARN_ON(&dev_priv->drm, in bxt_set_cdclk()
1562 cdclk != dev_priv->cdclk.hw.bypass); in bxt_set_cdclk()
1563 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_set_cdclk()
1569 drm_WARN(&dev_priv->drm, in bxt_set_cdclk()
1570 IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, in bxt_set_cdclk()
1578 drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, in bxt_set_cdclk()
1584 if (INTEL_GEN(dev_priv) >= 10) { in bxt_set_cdclk()
1585 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1586 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1587 cnl_cdclk_pll_disable(dev_priv); in bxt_set_cdclk()
1589 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1590 cnl_cdclk_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1593 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1594 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1595 bxt_de_pll_disable(dev_priv); in bxt_set_cdclk()
1597 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1598 bxt_de_pll_enable(dev_priv, vco); in bxt_set_cdclk()
1602 bxt_cdclk_cd2x_pipe(dev_priv, pipe); in bxt_set_cdclk()
1608 if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) in bxt_set_cdclk()
1610 intel_de_write(dev_priv, CDCLK_CTL, val); in bxt_set_cdclk()
1613 intel_wait_for_vblank(dev_priv, pipe); in bxt_set_cdclk()
1615 if (INTEL_GEN(dev_priv) >= 10) { in bxt_set_cdclk()
1616 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1625 ret = sandybridge_pcode_write_timeout(dev_priv, in bxt_set_cdclk()
1632 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1638 intel_update_cdclk(dev_priv); in bxt_set_cdclk()
1640 if (INTEL_GEN(dev_priv) >= 10) in bxt_set_cdclk()
1645 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1648 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) in bxt_sanitize_cdclk() argument
1653 intel_update_cdclk(dev_priv); in bxt_sanitize_cdclk()
1654 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1656 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1657 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1666 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in bxt_sanitize_cdclk()
1672 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); in bxt_sanitize_cdclk()
1675 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1676 if (cdclk != dev_priv->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
1680 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
1681 if (vco != dev_priv->cdclk.hw.vco) in bxt_sanitize_cdclk()
1687 switch (DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.vco, in bxt_sanitize_cdclk()
1688 dev_priv->cdclk.hw.cdclk)) { in bxt_sanitize_cdclk()
1709 if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1717 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
1720 dev_priv->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1723 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1726 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_init_hw() argument
1730 bxt_sanitize_cdclk(dev_priv); in bxt_cdclk_init_hw()
1732 if (dev_priv->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
1733 dev_priv->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
1736 cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_init_hw()
1743 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
1744 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
1746 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_init_hw()
1748 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
1751 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_uninit_hw() argument
1753 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; in bxt_cdclk_uninit_hw()
1758 dev_priv->display.calc_voltage_level(cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
1760 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
1824 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, in intel_cdclk_can_cd2x_update() argument
1829 if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) in intel_cdclk_can_cd2x_update()
1870 static void intel_set_cdclk(struct drm_i915_private *dev_priv, in intel_set_cdclk() argument
1876 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) in intel_set_cdclk()
1879 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) in intel_set_cdclk()
1889 mutex_lock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1890 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1894 &dev_priv->gmbus_mutex); in intel_set_cdclk()
1897 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
1899 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
1904 mutex_unlock(&dev_priv->gmbus_mutex); in intel_set_cdclk()
1906 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
1907 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), in intel_set_cdclk()
1909 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); in intel_set_cdclk()
1924 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update() local
1937 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
1939 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
1953 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update() local
1966 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
1968 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
1974 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk() local
1977 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in intel_pixel_rate_to_cdclk()
1979 else if (IS_GEN(dev_priv, 9) || in intel_pixel_rate_to_cdclk()
1980 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
1982 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk() local
1997 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2005 struct drm_i915_private *dev_priv = in intel_crtc_compute_min_cdclk() local
2015 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) in intel_crtc_compute_min_cdclk()
2027 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { in intel_crtc_compute_min_cdclk()
2030 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { in intel_crtc_compute_min_cdclk()
2040 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2050 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2059 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2068 IS_GEMINILAKE(dev_priv)) in intel_crtc_compute_min_cdclk()
2083 if (IS_TIGERLAKE(dev_priv)) { in intel_crtc_compute_min_cdclk()
2090 dev_priv->max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2093 if (min_cdclk > dev_priv->max_cdclk_freq) { in intel_crtc_compute_min_cdclk()
2094 drm_dbg_kms(&dev_priv->drm, in intel_crtc_compute_min_cdclk()
2096 min_cdclk, dev_priv->max_cdclk_freq); in intel_crtc_compute_min_cdclk()
2106 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk() local
2135 for_each_pipe(dev_priv, pipe) { in intel_compute_min_cdclk()
2163 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level() local
2189 for_each_pipe(dev_priv, pipe) in bxt_compute_min_voltage_level()
2199 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk() local
2206 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2210 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2213 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2217 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2259 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco() local
2266 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2331 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk() local
2342 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
2343 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2349 dev_priv->display.calc_voltage_level(cdclk)); in bxt_modeset_calc_cdclk()
2352 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2353 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2358 dev_priv->display.calc_voltage_level(cdclk); in bxt_modeset_calc_cdclk()
2368 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_all_pipes() local
2375 for_each_intel_crtc(&dev_priv->drm, crtc) { in intel_modeset_all_pipes()
2448 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state() local
2451 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); in intel_atomic_get_cdclk_state()
2458 int intel_cdclk_init(struct drm_i915_private *dev_priv) in intel_cdclk_init() argument
2466 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, in intel_cdclk_init()
2474 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk() local
2489 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); in intel_modeset_calc_cdclk()
2514 intel_cdclk_can_cd2x_update(dev_priv, in intel_modeset_calc_cdclk()
2521 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in intel_modeset_calc_cdclk()
2536 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2548 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2552 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2556 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
2564 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
2566 int max_cdclk_freq = dev_priv->max_cdclk_freq; in intel_compute_max_dotclk()
2568 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) in intel_compute_max_dotclk()
2570 else if (IS_GEN(dev_priv, 9) || in intel_compute_max_dotclk()
2571 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
2573 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
2575 else if (INTEL_GEN(dev_priv) < 4) in intel_compute_max_dotclk()
2589 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) in intel_update_max_cdclk() argument
2591 if (IS_ELKHARTLAKE(dev_priv)) { in intel_update_max_cdclk()
2592 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2593 dev_priv->max_cdclk_freq = 552000; in intel_update_max_cdclk()
2595 dev_priv->max_cdclk_freq = 556800; in intel_update_max_cdclk()
2596 } else if (INTEL_GEN(dev_priv) >= 11) { in intel_update_max_cdclk()
2597 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2598 dev_priv->max_cdclk_freq = 648000; in intel_update_max_cdclk()
2600 dev_priv->max_cdclk_freq = 652800; in intel_update_max_cdclk()
2601 } else if (IS_CANNONLAKE(dev_priv)) { in intel_update_max_cdclk()
2602 dev_priv->max_cdclk_freq = 528000; in intel_update_max_cdclk()
2603 } else if (IS_GEN9_BC(dev_priv)) { in intel_update_max_cdclk()
2604 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
2607 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
2608 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
2624 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
2625 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
2626 dev_priv->max_cdclk_freq = 316800; in intel_update_max_cdclk()
2627 } else if (IS_BROXTON(dev_priv)) { in intel_update_max_cdclk()
2628 dev_priv->max_cdclk_freq = 624000; in intel_update_max_cdclk()
2629 } else if (IS_BROADWELL(dev_priv)) { in intel_update_max_cdclk()
2636 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
2637 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2638 else if (IS_BDW_ULX(dev_priv)) in intel_update_max_cdclk()
2639 dev_priv->max_cdclk_freq = 450000; in intel_update_max_cdclk()
2640 else if (IS_BDW_ULT(dev_priv)) in intel_update_max_cdclk()
2641 dev_priv->max_cdclk_freq = 540000; in intel_update_max_cdclk()
2643 dev_priv->max_cdclk_freq = 675000; in intel_update_max_cdclk()
2644 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
2645 dev_priv->max_cdclk_freq = 320000; in intel_update_max_cdclk()
2646 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
2647 dev_priv->max_cdclk_freq = 400000; in intel_update_max_cdclk()
2650 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2653 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
2655 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
2656 dev_priv->max_cdclk_freq); in intel_update_max_cdclk()
2658 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
2659 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
2668 void intel_update_cdclk(struct drm_i915_private *dev_priv) in intel_update_cdclk() argument
2670 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2678 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
2679 intel_de_write(dev_priv, GMBUSFREQ_VLV, in intel_update_cdclk()
2680 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
2683 static int cnp_rawclk(struct drm_i915_private *dev_priv) in cnp_rawclk() argument
2688 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
2704 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in cnp_rawclk()
2708 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
2712 static int pch_rawclk(struct drm_i915_private *dev_priv) in pch_rawclk() argument
2714 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
2717 static int vlv_hrawclk(struct drm_i915_private *dev_priv) in vlv_hrawclk() argument
2720 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", in vlv_hrawclk()
2724 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) in i9xx_hrawclk() argument
2738 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_hrawclk()
2740 if (IS_MOBILE(dev_priv)) { in i9xx_hrawclk()
2787 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) in intel_read_rawclk() argument
2791 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in intel_read_rawclk()
2792 freq = cnp_rawclk(dev_priv); in intel_read_rawclk()
2793 else if (HAS_PCH_SPLIT(dev_priv)) in intel_read_rawclk()
2794 freq = pch_rawclk(dev_priv); in intel_read_rawclk()
2795 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
2796 freq = vlv_hrawclk(dev_priv); in intel_read_rawclk()
2797 else if (INTEL_GEN(dev_priv) >= 3) in intel_read_rawclk()
2798 freq = i9xx_hrawclk(dev_priv); in intel_read_rawclk()
2810 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) in intel_init_cdclk_hooks() argument
2812 if (INTEL_GEN(dev_priv) >= 12) { in intel_init_cdclk_hooks()
2813 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2814 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2815 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2816 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; in intel_init_cdclk_hooks()
2817 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2818 } else if (IS_ELKHARTLAKE(dev_priv)) { in intel_init_cdclk_hooks()
2819 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2820 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2821 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2822 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; in intel_init_cdclk_hooks()
2823 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2824 } else if (INTEL_GEN(dev_priv) >= 11) { in intel_init_cdclk_hooks()
2825 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2826 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2827 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2828 dev_priv->display.calc_voltage_level = icl_calc_voltage_level; in intel_init_cdclk_hooks()
2829 dev_priv->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
2830 } else if (IS_CANNONLAKE(dev_priv)) { in intel_init_cdclk_hooks()
2831 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2832 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2833 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2834 dev_priv->display.calc_voltage_level = cnl_calc_voltage_level; in intel_init_cdclk_hooks()
2835 dev_priv->cdclk.table = cnl_cdclk_table; in intel_init_cdclk_hooks()
2836 } else if (IS_GEN9_LP(dev_priv)) { in intel_init_cdclk_hooks()
2837 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2838 dev_priv->display.set_cdclk = bxt_set_cdclk; in intel_init_cdclk_hooks()
2839 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2840 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level; in intel_init_cdclk_hooks()
2841 if (IS_GEMINILAKE(dev_priv)) in intel_init_cdclk_hooks()
2842 dev_priv->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
2844 dev_priv->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
2845 } else if (IS_GEN9_BC(dev_priv)) { in intel_init_cdclk_hooks()
2846 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2847 dev_priv->display.set_cdclk = skl_set_cdclk; in intel_init_cdclk_hooks()
2848 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2849 } else if (IS_BROADWELL(dev_priv)) { in intel_init_cdclk_hooks()
2850 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2851 dev_priv->display.set_cdclk = bdw_set_cdclk; in intel_init_cdclk_hooks()
2852 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2853 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
2854 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2855 dev_priv->display.set_cdclk = chv_set_cdclk; in intel_init_cdclk_hooks()
2856 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2857 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
2858 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2859 dev_priv->display.set_cdclk = vlv_set_cdclk; in intel_init_cdclk_hooks()
2860 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2862 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk; in intel_init_cdclk_hooks()
2863 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk; in intel_init_cdclk_hooks()
2866 if (INTEL_GEN(dev_priv) >= 10 || IS_GEN9_LP(dev_priv)) in intel_init_cdclk_hooks()
2867 dev_priv->display.get_cdclk = bxt_get_cdclk; in intel_init_cdclk_hooks()
2868 else if (IS_GEN9_BC(dev_priv)) in intel_init_cdclk_hooks()
2869 dev_priv->display.get_cdclk = skl_get_cdclk; in intel_init_cdclk_hooks()
2870 else if (IS_BROADWELL(dev_priv)) in intel_init_cdclk_hooks()
2871 dev_priv->display.get_cdclk = bdw_get_cdclk; in intel_init_cdclk_hooks()
2872 else if (IS_HASWELL(dev_priv)) in intel_init_cdclk_hooks()
2873 dev_priv->display.get_cdclk = hsw_get_cdclk; in intel_init_cdclk_hooks()
2874 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_init_cdclk_hooks()
2875 dev_priv->display.get_cdclk = vlv_get_cdclk; in intel_init_cdclk_hooks()
2876 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) in intel_init_cdclk_hooks()
2877 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2878 else if (IS_GEN(dev_priv, 5)) in intel_init_cdclk_hooks()
2879 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; in intel_init_cdclk_hooks()
2880 else if (IS_GM45(dev_priv)) in intel_init_cdclk_hooks()
2881 dev_priv->display.get_cdclk = gm45_get_cdclk; in intel_init_cdclk_hooks()
2882 else if (IS_G45(dev_priv)) in intel_init_cdclk_hooks()
2883 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2884 else if (IS_I965GM(dev_priv)) in intel_init_cdclk_hooks()
2885 dev_priv->display.get_cdclk = i965gm_get_cdclk; in intel_init_cdclk_hooks()
2886 else if (IS_I965G(dev_priv)) in intel_init_cdclk_hooks()
2887 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2888 else if (IS_PINEVIEW(dev_priv)) in intel_init_cdclk_hooks()
2889 dev_priv->display.get_cdclk = pnv_get_cdclk; in intel_init_cdclk_hooks()
2890 else if (IS_G33(dev_priv)) in intel_init_cdclk_hooks()
2891 dev_priv->display.get_cdclk = g33_get_cdclk; in intel_init_cdclk_hooks()
2892 else if (IS_I945GM(dev_priv)) in intel_init_cdclk_hooks()
2893 dev_priv->display.get_cdclk = i945gm_get_cdclk; in intel_init_cdclk_hooks()
2894 else if (IS_I945G(dev_priv)) in intel_init_cdclk_hooks()
2895 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; in intel_init_cdclk_hooks()
2896 else if (IS_I915GM(dev_priv)) in intel_init_cdclk_hooks()
2897 dev_priv->display.get_cdclk = i915gm_get_cdclk; in intel_init_cdclk_hooks()
2898 else if (IS_I915G(dev_priv)) in intel_init_cdclk_hooks()
2899 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk; in intel_init_cdclk_hooks()
2900 else if (IS_I865G(dev_priv)) in intel_init_cdclk_hooks()
2901 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk; in intel_init_cdclk_hooks()
2902 else if (IS_I85X(dev_priv)) in intel_init_cdclk_hooks()
2903 dev_priv->display.get_cdclk = i85x_get_cdclk; in intel_init_cdclk_hooks()
2904 else if (IS_I845G(dev_priv)) in intel_init_cdclk_hooks()
2905 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; in intel_init_cdclk_hooks()
2906 else if (IS_I830(dev_priv)) in intel_init_cdclk_hooks()
2907 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()
2909 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk, in intel_init_cdclk_hooks()
2911 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; in intel_init_cdclk_hooks()