120 	writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);  in hibmc_plane_atomic_update()
127 	       priv->mmio + HIBMC_CRT_FB_WIDTH);  in hibmc_plane_atomic_update()
130 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_plane_atomic_update()
134 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_plane_atomic_update()
165 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_dpms()
171 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_dpms()
183 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_enable()
205 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_disable()
259 	val = readl(priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
261 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
264 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
266 	writel(pll, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
271 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
276 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
281 	writel(val, priv->mmio + CRT_PLL1_HS);  in set_vclock_hisilicon()
324 	writel(pll2, priv->mmio + CRT_PLL2_HS);  in display_ctrl_adjust()
335 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL);  in display_ctrl_adjust()
339 	       priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR);  in display_ctrl_adjust()
356 	writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL);  in display_ctrl_adjust()
370 	writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL);  in hibmc_crtc_mode_set_nofb()
373 	       priv->mmio + HIBMC_CRT_HORZ_TOTAL);  in hibmc_crtc_mode_set_nofb()
377 	       priv->mmio + HIBMC_CRT_HORZ_SYNC);  in hibmc_crtc_mode_set_nofb()
381 	       priv->mmio + HIBMC_CRT_VERT_TOTAL);  in hibmc_crtc_mode_set_nofb()
385 	       priv->mmio + HIBMC_CRT_VERT_SYNC);  in hibmc_crtc_mode_set_nofb()
405 	reg = readl(priv->mmio + HIBMC_CURRENT_GATE);  in hibmc_crtc_atomic_begin()
433 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);  in hibmc_crtc_enable_vblank()
443 	       priv->mmio + HIBMC_RAW_INTERRUPT_EN);  in hibmc_crtc_disable_vblank()
449 	void __iomem   *mmio = priv->mmio;  in hibmc_crtc_load_lut()  local
465 		writel(rgb, mmio + HIBMC_CRT_PALETTE + offset);  in hibmc_crtc_load_lut()
468 	reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_load_lut()
470 	writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL);  in hibmc_crtc_load_lut()