260 	uint32_t DP;  member
1049 	intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;  in cdv_intel_dp_mode_set()
1050 	intel_dp->DP |= intel_dp->color_range;  in cdv_intel_dp_mode_set()
1053 		intel_dp->DP |= DP_SYNC_HS_HIGH;  in cdv_intel_dp_mode_set()
1055 		intel_dp->DP |= DP_SYNC_VS_HIGH;  in cdv_intel_dp_mode_set()
1057 	intel_dp->DP |= DP_LINK_TRAIN_OFF;  in cdv_intel_dp_mode_set()
1061 		intel_dp->DP |= DP_PORT_WIDTH_1;  in cdv_intel_dp_mode_set()
1064 		intel_dp->DP |= DP_PORT_WIDTH_2;  in cdv_intel_dp_mode_set()
1067 		intel_dp->DP |= DP_PORT_WIDTH_4;  in cdv_intel_dp_mode_set()
1071 		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;  in cdv_intel_dp_mode_set()
1083 		intel_dp->DP |= DP_ENHANCED_FRAMING;  in cdv_intel_dp_mode_set()
1088 		intel_dp->DP |= DP_PIPEB_SELECT;  in cdv_intel_dp_mode_set()
1090 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1091 	DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);  in cdv_intel_dp_mode_set()
1480 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_start_link_train()  local
1482 	DP |= DP_PORT_EN;  in cdv_intel_dp_start_link_train()
1483 	DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_start_link_train()
1485 	reg = DP;	  in cdv_intel_dp_start_link_train()
1504 		reg = DP | DP_LINK_TRAIN_PAT_1;  in cdv_intel_dp_start_link_train()
1561 	intel_dp->DP = DP;  in cdv_intel_dp_start_link_train()
1571 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_complete_link_train()  local
1578 		reg = DP | DP_LINK_TRAIN_PAT_2;  in cdv_intel_dp_complete_link_train()
1639 	reg = DP | DP_LINK_TRAIN_OFF;  in cdv_intel_dp_complete_link_train()
1652 	uint32_t DP = intel_dp->DP;  in cdv_intel_dp_link_down()  local
1661 		DP &= ~DP_LINK_TRAIN_MASK;  in cdv_intel_dp_link_down()
1662 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1668 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()