Lines Matching +full:4 +full:th
30 /* Y 4th frame start address for output DMA */
38 /* Cb 4th frame start address for output DMA */
46 /* Cr 4th frame start address for output DMA */
120 /* Y 5th frame start address for output DMA */
122 /* Y 6th frame start address for output DMA */
124 /* Y 7th frame start address for output DMA */
126 /* Y 8th frame start address for output DMA */
128 /* Y 9th frame start address for output DMA */
130 /* Y 10th frame start address for output DMA */
132 /* Y 11th frame start address for output DMA */
134 /* Y 12th frame start address for output DMA */
136 /* Y 13th frame start address for output DMA */
138 /* Y 14th frame start address for output DMA */
140 /* Y 15th frame start address for output DMA */
142 /* Y 16th frame start address for output DMA */
144 /* Y 17th frame start address for output DMA */
146 /* Y 18th frame start address for output DMA */
148 /* Y 19th frame start address for output DMA */
150 /* Y 20th frame start address for output DMA */
152 /* Y 21th frame start address for output DMA */
154 /* Y 22th frame start address for output DMA */
156 /* Y 23th frame start address for output DMA */
158 /* Y 24th frame start address for output DMA */
160 /* Y 25th frame start address for output DMA */
162 /* Y 26th frame start address for output DMA */
164 /* Y 27th frame start address for output DMA */
166 /* Y 28th frame start address for output DMA */
168 /* Y 29th frame start address for output DMA */
170 /* Y 30th frame start address for output DMA */
172 /* Y 31th frame start address for output DMA */
174 /* Y 32th frame start address for output DMA */
177 /* CB 5th frame start address for output DMA */
179 /* CB 6th frame start address for output DMA */
181 /* CB 7th frame start address for output DMA */
183 /* CB 8th frame start address for output DMA */
185 /* CB 9th frame start address for output DMA */
187 /* CB 10th frame start address for output DMA */
189 /* CB 11th frame start address for output DMA */
191 /* CB 12th frame start address for output DMA */
193 /* CB 13th frame start address for output DMA */
195 /* CB 14th frame start address for output DMA */
197 /* CB 15th frame start address for output DMA */
199 /* CB 16th frame start address for output DMA */
201 /* CB 17th frame start address for output DMA */
203 /* CB 18th frame start address for output DMA */
205 /* CB 19th frame start address for output DMA */
207 /* CB 20th frame start address for output DMA */
209 /* CB 21th frame start address for output DMA */
211 /* CB 22th frame start address for output DMA */
213 /* CB 23th frame start address for output DMA */
215 /* CB 24th frame start address for output DMA */
217 /* CB 25th frame start address for output DMA */
219 /* CB 26th frame start address for output DMA */
221 /* CB 27th frame start address for output DMA */
223 /* CB 28th frame start address for output DMA */
225 /* CB 29th frame start address for output DMA */
227 /* CB 30th frame start address for output DMA */
229 /* CB 31th frame start address for output DMA */
231 /* CB 32th frame start address for output DMA */
234 /* CR 5th frame start address for output DMA */
236 /* CR 6th frame start address for output DMA */
238 /* CR 7th frame start address for output DMA */
240 /* CR 8th frame start address for output DMA */
242 /* CR 9th frame start address for output DMA */
244 /* CR 10th frame start address for output DMA */
246 /* CR 11th frame start address for output DMA */
248 /* CR 12th frame start address for output DMA */
250 /* CR 13th frame start address for output DMA */
252 /* CR 14th frame start address for output DMA */
254 /* CR 15th frame start address for output DMA */
256 /* CR 16th frame start address for output DMA */
258 /* CR 17th frame start address for output DMA */
260 /* CR 18th frame start address for output DMA */
262 /* CR 19th frame start address for output DMA */
264 /* CR 20th frame start address for output DMA */
266 /* CR 21th frame start address for output DMA */
268 /* CR 22th frame start address for output DMA */
270 /* CR 23th frame start address for output DMA */
272 /* CR 24th frame start address for output DMA */
274 /* CR 25th frame start address for output DMA */
276 /* CR 26th frame start address for output DMA */
278 /* CR 27th frame start address for output DMA */
280 /* CR 28th frame start address for output DMA */
282 /* CR 29th frame start address for output DMA */
284 /* CR 30th frame start address for output DMA */
286 /* CR 31th frame start address for output DMA */
288 /* CR 32th frame start address for output DMA */
294 /* frame start address 1 ~ 4, 5 ~ 32 */
296 #define DEF_PP 4
299 (EXYNOS_CIOYSA1 + (__x) * 4) : \
300 (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4))
303 (EXYNOS_CIOCBSA1 + (__x) * 4) : \
304 (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4))
307 (EXYNOS_CIOCRSA1 + (__x) * 4) : \
308 (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4))
457 #define EXYNOS_CIGCTRL_INVPOLHSYNC (1 << 4)
499 #define EXYNOS_CIOCTRL_ALPHA_OUT (0xff << 4)
566 #define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26)
597 #define EXYNOS_MSCTRL_ORDER422_CRYCBY (0 << 4)
598 #define EXYNOS_MSCTRL_ORDER422_YCRYCB (1 << 4)
599 #define EXYNOS_MSCTRL_ORDER422_CBYCRY (2 << 4)
600 #define EXYNOS_MSCTRL_ORDER422_YCBYCR (3 << 4)
620 #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24)
627 #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20)
638 #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8)
641 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4)
642 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4)
643 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4)
644 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4)
645 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4)
646 #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4)