Lines Matching refs:reg_values
251 const unsigned int *reg_values; member
399 static const unsigned int reg_values[] = { variable
462 .reg_values = reg_values,
474 .reg_values = reg_values,
484 .reg_values = reg_values,
495 .reg_values = exynos5433_reg_values,
506 .reg_values = exynos5422_reg_values,
533 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; in exynos_dsi_reset()
616 writel(driver_data->reg_values[PLL_TIMER], in exynos_dsi_set_pll()
695 const unsigned int *reg_values = driver_data->reg_values; in exynos_dsi_set_phy_ctrl() local
702 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | in exynos_dsi_set_phy_ctrl()
703 reg_values[PHYCTRL_SLEW_UP]; in exynos_dsi_set_phy_ctrl()
711 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; in exynos_dsi_set_phy_ctrl()
727 reg = reg_values[PHYTIMING_CLK_PREPARE] | in exynos_dsi_set_phy_ctrl()
728 reg_values[PHYTIMING_CLK_ZERO] | in exynos_dsi_set_phy_ctrl()
729 reg_values[PHYTIMING_CLK_POST] | in exynos_dsi_set_phy_ctrl()
730 reg_values[PHYTIMING_CLK_TRAIL]; in exynos_dsi_set_phy_ctrl()
743 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | in exynos_dsi_set_phy_ctrl()
744 reg_values[PHYTIMING_HS_TRAIL]; in exynos_dsi_set_phy_ctrl()
875 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); in exynos_dsi_init_link()
1321 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) in exynos_dsi_init()