Lines Matching +full:vdd +full:- +full:rx +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
35 /* DSI D-PHY Layer Registers */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
90 #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
91 #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
97 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
171 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
172 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
175 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
268 struct regulator *vdd; member
272 u8 lvds_link; /* single-link or dual-link */
284 struct device *dev = &tc->dsi->dev; in tc_bridge_pre_enable()
287 ret = regulator_enable(tc->vddio); in tc_bridge_pre_enable()
292 ret = regulator_enable(tc->vdd); in tc_bridge_pre_enable()
294 dev_err(dev, "regulator vdd enable failed, %d\n", ret); in tc_bridge_pre_enable()
297 gpiod_set_value(tc->stby_gpio, 0); in tc_bridge_pre_enable()
300 gpiod_set_value(tc->reset_gpio, 0); in tc_bridge_pre_enable()
307 struct device *dev = &tc->dsi->dev; in tc_bridge_post_disable()
310 gpiod_set_value(tc->reset_gpio, 1); in tc_bridge_post_disable()
313 gpiod_set_value(tc->stby_gpio, 1); in tc_bridge_post_disable()
316 ret = regulator_disable(tc->vdd); in tc_bridge_post_disable()
318 dev_err(dev, "regulator vdd disable failed, %d\n", ret); in tc_bridge_post_disable()
321 ret = regulator_disable(tc->vddio); in tc_bridge_post_disable()
344 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", in d2l_read()
358 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", in d2l_write()
365 struct drm_device *dev = encoder->dev; in get_connector()
368 list_for_each_entry(connector, &dev->mode_config.connector_list, head) in get_connector()
369 if (connector->encoder == encoder) in get_connector()
383 struct drm_connector *connector = get_connector(bridge->encoder); in tc_bridge_enable()
385 mode = &bridge->encoder->crtc->state->adjusted_mode; in tc_bridge_enable()
387 hback_porch = mode->htotal - mode->hsync_end; in tc_bridge_enable()
388 hsync_len = mode->hsync_end - mode->hsync_start; in tc_bridge_enable()
389 vback_porch = mode->vtotal - mode->vsync_end; in tc_bridge_enable()
390 vsync_len = mode->vsync_end - mode->vsync_start; in tc_bridge_enable()
395 hfront_porch = mode->hsync_start - mode->hdisplay; in tc_bridge_enable()
396 hactive = mode->hdisplay; in tc_bridge_enable()
397 vfront_porch = mode->vsync_start - mode->vdisplay; in tc_bridge_enable()
398 vactive = mode->vdisplay; in tc_bridge_enable()
403 d2l_read(tc->i2c, IDREG, &val); in tc_bridge_enable()
405 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", in tc_bridge_enable()
408 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | in tc_bridge_enable()
412 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_bridge_enable()
413 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_bridge_enable()
414 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
415 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
416 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
417 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
419 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; in tc_bridge_enable()
420 d2l_write(tc->i2c, PPI_LANEENABLE, val); in tc_bridge_enable()
421 d2l_write(tc->i2c, DSI_LANEENABLE, val); in tc_bridge_enable()
423 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); in tc_bridge_enable()
424 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); in tc_bridge_enable()
426 if (tc->bpc == 8) in tc_bridge_enable()
431 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
432 clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link; in tc_bridge_enable()
434 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; in tc_bridge_enable()
436 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / in tc_bridge_enable()
437 tc->num_dsi_lanes); in tc_bridge_enable()
439 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; in tc_bridge_enable()
442 d2l_write(tc->i2c, VPCTRL, val); in tc_bridge_enable()
444 d2l_write(tc->i2c, HTIM1, htime1); in tc_bridge_enable()
445 d2l_write(tc->i2c, VTIM1, vtime1); in tc_bridge_enable()
446 d2l_write(tc->i2c, HTIM2, htime2); in tc_bridge_enable()
447 d2l_write(tc->i2c, VTIM2, vtime2); in tc_bridge_enable()
449 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
450 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); in tc_bridge_enable()
451 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); in tc_bridge_enable()
453 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", in tc_bridge_enable()
454 connector->display_info.bus_formats[0], in tc_bridge_enable()
455 tc->bpc); in tc_bridge_enable()
458 * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format in tc_bridge_enable()
460 if (connector->display_info.bus_formats[0] == in tc_bridge_enable()
462 /* VESA-24 */ in tc_bridge_enable()
463 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
464 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); in tc_bridge_enable()
465 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); in tc_bridge_enable()
466 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
467 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); in tc_bridge_enable()
468 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
469 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); in tc_bridge_enable()
470 } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */ in tc_bridge_enable()
471 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
472 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0)); in tc_bridge_enable()
473 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0)); in tc_bridge_enable()
474 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
475 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2)); in tc_bridge_enable()
476 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
477 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0)); in tc_bridge_enable()
480 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
483 if (tc->lvds_link == DUAL_LINK) { in tc_bridge_enable()
489 d2l_write(tc->i2c, LVCFG, val); in tc_bridge_enable()
500 * Maximum pixel clock speed 135MHz for single-link in tc_mode_valid()
501 * 270MHz for dual-link in tc_mode_valid()
503 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || in tc_mode_valid()
504 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) in tc_mode_valid()
507 switch (info->bus_formats[0]) { in tc_mode_valid()
511 tc->bpc = 8; in tc_mode_valid()
515 tc->bpc = 6; in tc_mode_valid()
518 dev_warn(tc->dev, in tc_mode_valid()
520 info->bus_formats[0]); in tc_mode_valid()
536 * To get the data-lanes of dsi, we need to access the dsi0_out of port1 in tc358775_parse_dt()
539 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
540 TC358775_DSI_IN, -1); in tc358775_parse_dt()
547 endpoint = of_graph_get_endpoint_by_regs(parent, 1, -1); in tc358775_parse_dt()
550 prop = of_find_property(endpoint, "data-lanes", in tc358775_parse_dt()
554 dev_err(tc->dev, in tc358775_parse_dt()
556 return -EPROBE_DEFER; in tc358775_parse_dt()
562 tc->num_dsi_lanes = len / sizeof(u32); in tc358775_parse_dt()
564 if (tc->num_dsi_lanes < 1 || tc->num_dsi_lanes > 4) in tc358775_parse_dt()
565 return -EINVAL; in tc358775_parse_dt()
567 tc->host_node = of_graph_get_remote_node(np, 0, 0); in tc358775_parse_dt()
568 if (!tc->host_node) in tc358775_parse_dt()
569 return -ENODEV; in tc358775_parse_dt()
571 of_node_put(tc->host_node); in tc358775_parse_dt()
573 tc->lvds_link = SINGLE_LINK; in tc358775_parse_dt()
574 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
575 TC358775_LVDS_OUT1, -1); in tc358775_parse_dt()
582 tc->lvds_link = DUAL_LINK; in tc358775_parse_dt()
587 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); in tc358775_parse_dt()
588 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); in tc358775_parse_dt()
597 struct device *dev = &tc->i2c->dev; in tc_bridge_attach()
607 host = of_find_mipi_dsi_host_by_node(tc->host_node); in tc_bridge_attach()
610 return -EPROBE_DEFER; in tc_bridge_attach()
620 tc->dsi = dsi; in tc_bridge_attach()
622 dsi->lanes = tc->num_dsi_lanes; in tc_bridge_attach()
623 dsi->format = MIPI_DSI_FMT_RGB888; in tc_bridge_attach()
624 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; in tc_bridge_attach()
632 /* Attach the panel-bridge to the dsi bridge */ in tc_bridge_attach()
633 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, in tc_bridge_attach()
634 &tc->bridge, flags); in tc_bridge_attach()
651 struct device *dev = &client->dev; in tc_probe()
658 return -ENOMEM; in tc_probe()
660 tc->dev = dev; in tc_probe()
661 tc->i2c = client; in tc_probe()
663 ret = drm_of_find_panel_or_bridge(dev->of_node, TC358775_LVDS_OUT0, in tc_probe()
668 return -ENODEV; in tc_probe()
670 tc->panel_bridge = devm_drm_panel_bridge_add(dev, panel); in tc_probe()
671 if (IS_ERR(tc->panel_bridge)) in tc_probe()
672 return PTR_ERR(tc->panel_bridge); in tc_probe()
674 ret = tc358775_parse_dt(dev->of_node, tc); in tc_probe()
678 tc->vddio = devm_regulator_get(dev, "vddio-supply"); in tc_probe()
679 if (IS_ERR(tc->vddio)) { in tc_probe()
680 ret = PTR_ERR(tc->vddio); in tc_probe()
681 dev_err(dev, "vddio-supply not found\n"); in tc_probe()
685 tc->vdd = devm_regulator_get(dev, "vdd-supply"); in tc_probe()
686 if (IS_ERR(tc->vdd)) { in tc_probe()
687 ret = PTR_ERR(tc->vdd); in tc_probe()
688 dev_err(dev, "vdd-supply not found\n"); in tc_probe()
692 tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH); in tc_probe()
693 if (IS_ERR(tc->stby_gpio)) { in tc_probe()
694 ret = PTR_ERR(tc->stby_gpio); in tc_probe()
695 dev_err(dev, "cannot get stby-gpio %d\n", ret); in tc_probe()
699 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); in tc_probe()
700 if (IS_ERR(tc->reset_gpio)) { in tc_probe()
701 ret = PTR_ERR(tc->reset_gpio); in tc_probe()
702 dev_err(dev, "cannot get reset-gpios %d\n", ret); in tc_probe()
706 tc->bridge.funcs = &tc_bridge_funcs; in tc_probe()
707 tc->bridge.of_node = dev->of_node; in tc_probe()
708 drm_bridge_add(&tc->bridge); in tc_probe()
719 drm_bridge_remove(&tc->bridge); in tc_remove()