Lines Matching +full:4 +full:th
38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
49 #define BIT_DPD_OSC_EN BIT(4)
59 #define BIT_DCTL_EXT_DDC_SEL BIT(4)
70 #define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
91 #define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
125 #define BIT_CTRL1_GPIO_OEN_8 BIT(4)
172 #define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
183 #define BIT_CTRL_GPIO_OEN_4 BIT(4)
205 #define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
207 /* TMDS Control #4, default value: 0x02 */
217 #define BIT_BIST_START_BIT BIT(4)
257 #define BIT_DDC_MANUAL_DSCL BIT(4)
284 #define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
294 #define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
332 #define BIT_UTSRST_KEEPER_SRST BIT(4)
369 #define BIT_TTXINTL_TTX_INTR4 BIT(4)
380 #define BIT_TTXINTH_TTX_INTR12 BIT(4)
388 #define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
419 #define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
483 #define BIT_TMDS_CH_EN_CH0_EN BIT(4)
506 /* MHL Tx Control 6th, default value: 0xa0 */
516 #define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
544 #define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
553 #define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
565 #define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
584 #define BIT_INTR9_DEVCAP_DONE BIT(4)
594 #define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
605 #define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
630 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
653 #define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
683 #define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
730 /* MHL DataPath 4th Ctl, default value: 0x48 */
735 /* MHL DataPath 5th Ctl, default value: 0x48 */
740 /* MHL DataPath 6th Ctl, default value: 0x3f */
814 /* MHL CoC 4th Ctl, default value: 0x00 */
818 /* MHL CoC 5th Ctl, default value: 0x28 */
823 /* MHL CoC 6th Ctl, default value: 0x0d */
833 /* MHL DataPath 7th Ctl, default value: 0x2a */
836 #define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
842 /* MHL DataPath 8th Ctl, default value: 0x06 */
868 #define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
884 #define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
900 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
934 #define BIT_M3_CTRL_H2M_SWRST BIT(4)
949 #define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
1008 #define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
1020 #define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
1043 #define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
1073 #define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
1125 /* CoC 4th Ctl, default value: 0x40 */
1130 /* CoC 7th Ctl, default value: 0x00 */
1136 /* CoC 8th Ctl, default value: 0x06 */
1144 /* CoC 10th Ctl, default value: 0x00 */
1147 /* CoC 11th Ctl, default value: 0x00 */
1150 /* CoC 12th Ctl, default value: 0x00 */
1153 /* CoC 13th Ctl, default value: 0x0f */
1156 /* CoC 14th Ctl, default value: 0x0a */
1161 /* CoC 15th Ctl, default value: 0x0a */
1166 /* CoC 16th Ctl, default value: 0x00 */
1171 /* CoC 18th Ctl, default value: 0x32 */
1199 /* CoC 24th Ctl, default value: 0x00 */
1204 /* CoC 25th Ctl, default value: 0x00 */
1209 /* CoC 26th Ctl, default value: 0x00 */
1214 /* CoC 27th Ctl, default value: 0x00 */
1219 /* DoC 9th Status, default value: 0x00 */
1222 /* DoC 10th Status, default value: 0x00 */
1225 /* DoC 5th CFG, default value: 0x00 */
1232 /* DoC 7th Ctl, default value: 0x00 */
1239 /* DoC 8th Ctl, default value: 0x00 */
1247 /* DoC 9th Ctl, default value: 0x00 */
1254 /* DoC 10th Ctl, default value: 0x00 */
1257 /* DoC 11th Ctl, default value: 0x00 */
1260 /* DoC 15th Ctl, default value: 0x00 */
1276 /* Interrupt Mask 4th, default value: 0x00 */
1289 #define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
1303 #define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4)
1320 #define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
1349 #define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
1360 #define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
1414 #define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
1472 #define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
1488 #define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
1503 #define BIT_DISC_STAT2_RSEN BIT(4)
1521 #define BIT_CBUS_MHL3_DISCON_INT BIT(4)