1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/reset.h>
32 #include "nwl-dsi.h"
34 #define DRV_NAME "nwl-dsi"
82 	 * The DSI host controller needs this reset sequence according to NWL:
83 	 * 1. Deassert pclk reset to get access to DSI regs
85 	 * 3. Deassert ESC and BYTE resets to allow host TX operations)
87 	 * 5. Deassert DPI reset so DPI receives pixels and starts sending
105 	 * hardware bug: the i.MX8MQ needs this clock on during reset
135 	int ret = dsi->error;  in nwl_dsi_clear_error()
137 	dsi->error = 0;  in nwl_dsi_clear_error()
145 	if (dsi->error)  in nwl_dsi_write()
148 	ret = regmap_write(dsi->regmap, reg, val);  in nwl_dsi_write()
150 		DRM_DEV_ERROR(dsi->dev,  in nwl_dsi_write()
153 		dsi->error = ret;  in nwl_dsi_write()
162 	if (dsi->error)  in nwl_dsi_read()
165 	ret = regmap_read(dsi->regmap, reg, &val);  in nwl_dsi_read()
167 		DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",  in nwl_dsi_read()
169 		dsi->error = ret;  in nwl_dsi_read()
186 		return -EINVAL;  in nwl_dsi_get_dpi_pixel_format()
191  * ps2bc - Picoseconds to byte clock cycles
195 	u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in ps2bc()
197 	return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,  in ps2bc()
198 				  dsi->lanes * 8 * NSEC_PER_SEC);  in ps2bc()
202  * ui2bc - UI time periods to byte clock cycles
206 	u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in ui2bc()
208 	return DIV64_U64_ROUND_UP(ui * dsi->lanes,  in ui2bc()
209 				  dsi->mode.clock * 1000 * bpp);  in ui2bc()
213  * us2bc - micro seconds to lp clock cycles
215 static u32 us2lp(u32 lp_clk_rate, unsigned long us)  in us2lp()  argument
217 	return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);  in us2lp()
223 	struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;  in nwl_dsi_config_host()
225 	if (dsi->lanes < 1 || dsi->lanes > 4)  in nwl_dsi_config_host()
226 		return -EINVAL;  in nwl_dsi_config_host()
228 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);  in nwl_dsi_config_host()
229 	nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);  in nwl_dsi_config_host()
231 	if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {  in nwl_dsi_config_host()
240 	cycles = ui2bc(dsi, cfg->clk_pre);  in nwl_dsi_config_host()
241 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);  in nwl_dsi_config_host()
243 	cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);  in nwl_dsi_config_host()
244 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);  in nwl_dsi_config_host()
245 	cycles += ui2bc(dsi, cfg->clk_pre);  in nwl_dsi_config_host()
246 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);  in nwl_dsi_config_host()
248 	cycles = ps2bc(dsi, cfg->hs_exit);  in nwl_dsi_config_host()
249 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);  in nwl_dsi_config_host()
257 	cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);  in nwl_dsi_config_host()
258 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);  in nwl_dsi_config_host()
272 	hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;  in nwl_dsi_config_dpi()
273 	hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;  in nwl_dsi_config_dpi()
274 	hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;  in nwl_dsi_config_dpi()
276 	vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;  in nwl_dsi_config_dpi()
277 	vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;  in nwl_dsi_config_dpi()
278 	vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;  in nwl_dsi_config_dpi()
280 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);  in nwl_dsi_config_dpi()
281 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);  in nwl_dsi_config_dpi()
282 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);  in nwl_dsi_config_dpi()
283 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);  in nwl_dsi_config_dpi()
284 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);  in nwl_dsi_config_dpi()
285 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);  in nwl_dsi_config_dpi()
286 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);  in nwl_dsi_config_dpi()
287 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);  in nwl_dsi_config_dpi()
288 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);  in nwl_dsi_config_dpi()
290 	color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);  in nwl_dsi_config_dpi()
292 		DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",  in nwl_dsi_config_dpi()
293 			      dsi->format);  in nwl_dsi_config_dpi()
296 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);  in nwl_dsi_config_dpi()
309 	burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&  in nwl_dsi_config_dpi()
310 		     !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);  in nwl_dsi_config_dpi()
316 		mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?  in nwl_dsi_config_dpi()
321 			      dsi->mode.hdisplay);  in nwl_dsi_config_dpi()
333 	nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);  in nwl_dsi_config_dpi()
334 	nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);  in nwl_dsi_config_dpi()
362 	struct device *dev = dsi->dev;  in nwl_dsi_host_attach()
364 	DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,  in nwl_dsi_host_attach()
365 		     device->format, device->mode_flags);  in nwl_dsi_host_attach()
367 	if (device->lanes < 1 || device->lanes > 4)  in nwl_dsi_host_attach()
368 		return -EINVAL;  in nwl_dsi_host_attach()
370 	dsi->lanes = device->lanes;  in nwl_dsi_host_attach()
371 	dsi->format = device->format;  in nwl_dsi_host_attach()
372 	dsi->dsi_mode_flags = device->mode_flags;  in nwl_dsi_host_attach()
379 	struct device *dev = dsi->dev;  in nwl_dsi_read_packet()
380 	struct nwl_dsi_transfer *xfer = dsi->xfer;  in nwl_dsi_read_packet()
382 	u8 *payload = xfer->msg->rx_buf;  in nwl_dsi_read_packet()
388 	xfer->status = 0;  in nwl_dsi_read_packet()
390 	if (xfer->rx_word_count == 0) {  in nwl_dsi_read_packet()
397 			xfer->status = err;  in nwl_dsi_read_packet()
402 		if (channel != xfer->msg->channel) {  in nwl_dsi_read_packet()
405 				      xfer->cmd, channel, xfer->msg->channel);  in nwl_dsi_read_packet()
406 			xfer->status = -EINVAL;  in nwl_dsi_read_packet()
413 			if (xfer->msg->rx_len > 1) {  in nwl_dsi_read_packet()
416 				++xfer->rx_len;  in nwl_dsi_read_packet()
421 			if (xfer->msg->rx_len > 0) {  in nwl_dsi_read_packet()
424 				++xfer->rx_len;  in nwl_dsi_read_packet()
426 			xfer->status = xfer->rx_len;  in nwl_dsi_read_packet()
431 				      xfer->cmd, word_count);  in nwl_dsi_read_packet()
432 			xfer->status = -EPROTO;  in nwl_dsi_read_packet()
436 		if (word_count > xfer->msg->rx_len) {  in nwl_dsi_read_packet()
439 				xfer->cmd, xfer->msg->rx_len, word_count);  in nwl_dsi_read_packet()
440 			xfer->status = -EINVAL;  in nwl_dsi_read_packet()
444 		xfer->rx_word_count = word_count;  in nwl_dsi_read_packet()
447 		word_count = xfer->rx_word_count;  in nwl_dsi_read_packet()
462 		xfer->rx_len += 4;  in nwl_dsi_read_packet()
463 		word_count -= 4;  in nwl_dsi_read_packet()
471 			++xfer->rx_len;  in nwl_dsi_read_packet()
475 			++xfer->rx_len;  in nwl_dsi_read_packet()
479 			++xfer->rx_len;  in nwl_dsi_read_packet()
484 	xfer->status = xfer->rx_len;  in nwl_dsi_read_packet()
487 		xfer->status = err;  in nwl_dsi_read_packet()
494 	struct nwl_dsi_transfer *xfer = dsi->xfer;  in nwl_dsi_finish_transmission()
500 	if (xfer->direction == DSI_PACKET_SEND &&  in nwl_dsi_finish_transmission()
502 		xfer->status = xfer->tx_len;  in nwl_dsi_finish_transmission()
511 		complete(&xfer->completed);  in nwl_dsi_finish_transmission()
516 	struct nwl_dsi_transfer *xfer = dsi->xfer;  in nwl_dsi_begin_transmission()
517 	struct mipi_dsi_packet *pkt = &xfer->packet;  in nwl_dsi_begin_transmission()
526 	length = pkt->payload_length;  in nwl_dsi_begin_transmission()
527 	payload = pkt->payload;  in nwl_dsi_begin_transmission()
534 		length -= 4;  in nwl_dsi_begin_transmission()
551 	xfer->tx_len = pkt->payload_length;  in nwl_dsi_begin_transmission()
559 	word_count = pkt->header[1] | (pkt->header[2] << 8);  in nwl_dsi_begin_transmission()
560 	if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {  in nwl_dsi_begin_transmission()
561 		DRM_DEV_DEBUG_DRIVER(dsi->dev,  in nwl_dsi_begin_transmission()
563 				     xfer->cmd);  in nwl_dsi_begin_transmission()
566 		hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;  in nwl_dsi_begin_transmission()
568 	val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |  in nwl_dsi_begin_transmission()
569 	      NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |  in nwl_dsi_begin_transmission()
570 	      NWL_DSI_BTA_TX(xfer->need_bta);  in nwl_dsi_begin_transmission()
585 	dsi->xfer = &xfer;  in nwl_dsi_host_transfer()
588 		dsi->xfer = NULL;  in nwl_dsi_host_transfer()
592 	if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||  in nwl_dsi_host_transfer()
593 	     msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||  in nwl_dsi_host_transfer()
594 	     msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||  in nwl_dsi_host_transfer()
595 	     msg->type & MIPI_DSI_DCS_READ) &&  in nwl_dsi_host_transfer()
596 	    msg->rx_len > 0 && msg->rx_buf)  in nwl_dsi_host_transfer()
602 	xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;  in nwl_dsi_host_transfer()
604 	xfer.status = -ETIMEDOUT;  in nwl_dsi_host_transfer()
608 	if (msg->tx_len > 0)  in nwl_dsi_host_transfer()
609 		xfer.cmd = ((u8 *)(msg->tx_buf))[0];  in nwl_dsi_host_transfer()
612 	ret = clk_prepare_enable(dsi->rx_esc_clk);  in nwl_dsi_host_transfer()
614 		DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",  in nwl_dsi_host_transfer()
618 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",  in nwl_dsi_host_transfer()
619 			     clk_get_rate(dsi->rx_esc_clk));  in nwl_dsi_host_transfer()
626 		DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",  in nwl_dsi_host_transfer()
628 		ret = -ETIMEDOUT;  in nwl_dsi_host_transfer()
633 	clk_disable_unprepare(dsi->rx_esc_clk);  in nwl_dsi_host_transfer()
651 		DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");  in nwl_dsi_irq_handler()
654 		DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");  in nwl_dsi_irq_handler()
666 	struct device *dev = dsi->dev;  in nwl_dsi_enable()
667 	union phy_configure_opts *phy_cfg = &dsi->phy_cfg;  in nwl_dsi_enable()
670 	if (!dsi->lanes) {  in nwl_dsi_enable()
671 		DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);  in nwl_dsi_enable()
672 		return -EINVAL;  in nwl_dsi_enable()
675 	ret = phy_init(dsi->phy);  in nwl_dsi_enable()
681 	ret = phy_configure(dsi->phy, phy_cfg);  in nwl_dsi_enable()
687 	ret = clk_prepare_enable(dsi->tx_esc_clk);  in nwl_dsi_enable()
689 		DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",  in nwl_dsi_enable()
693 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",  in nwl_dsi_enable()
694 			     clk_get_rate(dsi->tx_esc_clk));  in nwl_dsi_enable()
708 	ret = phy_power_on(dsi->phy);  in nwl_dsi_enable()
721 	phy_power_off(dsi->phy);  in nwl_dsi_enable()
723 	clk_disable_unprepare(dsi->tx_esc_clk);  in nwl_dsi_enable()
725 	phy_exit(dsi->phy);  in nwl_dsi_enable()
732 	struct device *dev = dsi->dev;  in nwl_dsi_disable()
736 	phy_power_off(dsi->phy);  in nwl_dsi_disable()
737 	phy_exit(dsi->phy);  in nwl_dsi_disable()
740 	clk_disable_unprepare(dsi->tx_esc_clk);  in nwl_dsi_disable()
752 	ret = reset_control_assert(dsi->rst_dpi);  in nwl_dsi_bridge_disable()
754 		DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);  in nwl_dsi_bridge_disable()
757 	ret = reset_control_assert(dsi->rst_byte);  in nwl_dsi_bridge_disable()
759 		DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);  in nwl_dsi_bridge_disable()
762 	ret = reset_control_assert(dsi->rst_esc);  in nwl_dsi_bridge_disable()
764 		DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);  in nwl_dsi_bridge_disable()
767 	ret = reset_control_assert(dsi->rst_pclk);  in nwl_dsi_bridge_disable()
769 		DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);  in nwl_dsi_bridge_disable()
773 	clk_disable_unprepare(dsi->core_clk);  in nwl_dsi_bridge_disable()
774 	clk_disable_unprepare(dsi->lcdif_clk);  in nwl_dsi_bridge_disable()
776 	pm_runtime_put(dsi->dev);  in nwl_dsi_bridge_disable()
786 	if (dsi->lanes < 1 || dsi->lanes > 4)  in nwl_dsi_get_dphy_params()
787 		return -EINVAL;  in nwl_dsi_get_dphy_params()
793 	ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,  in nwl_dsi_get_dphy_params()
794 		mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,  in nwl_dsi_get_dphy_params()
795 		&phy_opts->mipi_dphy);  in nwl_dsi_get_dphy_params()
799 	rate = clk_get_rate(dsi->tx_esc_clk);  in nwl_dsi_get_dphy_params()
800 	DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);  in nwl_dsi_get_dphy_params()
801 	phy_opts->mipi_dphy.lp_clk_rate = rate;  in nwl_dsi_get_dphy_params()
811 	adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);  in nwl_dsi_bridge_mode_fixup()
812 	adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);  in nwl_dsi_bridge_mode_fixup()
823 	int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);  in nwl_dsi_bridge_mode_valid()
825 	if (mode->clock * bpp > 15000000 * dsi->lanes)  in nwl_dsi_bridge_mode_valid()
828 	if (mode->clock * bpp < 80000 * dsi->lanes)  in nwl_dsi_bridge_mode_valid()
840 	struct device *dev = dsi->dev;  in nwl_dsi_bridge_mode_set()
850 	 * If hs clock is unchanged, we're all good - all parameters are  in nwl_dsi_bridge_mode_set()
853 	if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)  in nwl_dsi_bridge_mode_set()
856 	phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);  in nwl_dsi_bridge_mode_set()
859 	memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));  in nwl_dsi_bridge_mode_set()
861 	memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));  in nwl_dsi_bridge_mode_set()
870 	pm_runtime_get_sync(dsi->dev);  in nwl_dsi_bridge_pre_enable()
872 	if (clk_prepare_enable(dsi->lcdif_clk) < 0)  in nwl_dsi_bridge_pre_enable()
874 	if (clk_prepare_enable(dsi->core_clk) < 0)  in nwl_dsi_bridge_pre_enable()
877 	/* Step 1 from DSI reset-out instructions */  in nwl_dsi_bridge_pre_enable()
878 	ret = reset_control_deassert(dsi->rst_pclk);  in nwl_dsi_bridge_pre_enable()
880 		DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);  in nwl_dsi_bridge_pre_enable()
884 	/* Step 2 from DSI reset-out instructions */  in nwl_dsi_bridge_pre_enable()
887 	/* Step 3 from DSI reset-out instructions */  in nwl_dsi_bridge_pre_enable()
888 	ret = reset_control_deassert(dsi->rst_esc);  in nwl_dsi_bridge_pre_enable()
890 		DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);  in nwl_dsi_bridge_pre_enable()
893 	ret = reset_control_deassert(dsi->rst_byte);  in nwl_dsi_bridge_pre_enable()
895 		DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);  in nwl_dsi_bridge_pre_enable()
905 	/* Step 5 from DSI reset-out instructions */  in nwl_dsi_bridge_enable()
906 	ret = reset_control_deassert(dsi->rst_dpi);  in nwl_dsi_bridge_enable()
908 		DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);  in nwl_dsi_bridge_enable()
919 	ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,  in nwl_dsi_bridge_attach()
929 	dsi->panel_bridge = panel_bridge;  in nwl_dsi_bridge_attach()
931 	if (!dsi->panel_bridge)  in nwl_dsi_bridge_attach()
932 		return -EPROBE_DEFER;  in nwl_dsi_bridge_attach()
934 	return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,  in nwl_dsi_bridge_attach()
941 	drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);  in nwl_dsi_bridge_detach()
957 	struct platform_device *pdev = to_platform_device(dsi->dev);  in nwl_dsi_parse_dt()
962 	dsi->phy = devm_phy_get(dsi->dev, "dphy");  in nwl_dsi_parse_dt()
963 	if (IS_ERR(dsi->phy)) {  in nwl_dsi_parse_dt()
964 		ret = PTR_ERR(dsi->phy);  in nwl_dsi_parse_dt()
965 		if (ret != -EPROBE_DEFER)  in nwl_dsi_parse_dt()
966 			DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);  in nwl_dsi_parse_dt()
970 	clk = devm_clk_get(dsi->dev, "lcdif");  in nwl_dsi_parse_dt()
973 		DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",  in nwl_dsi_parse_dt()
977 	dsi->lcdif_clk = clk;  in nwl_dsi_parse_dt()
979 	clk = devm_clk_get(dsi->dev, "core");  in nwl_dsi_parse_dt()
982 		DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",  in nwl_dsi_parse_dt()
986 	dsi->core_clk = clk;  in nwl_dsi_parse_dt()
988 	clk = devm_clk_get(dsi->dev, "phy_ref");  in nwl_dsi_parse_dt()
991 		DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",  in nwl_dsi_parse_dt()
995 	dsi->phy_ref_clk = clk;  in nwl_dsi_parse_dt()
997 	clk = devm_clk_get(dsi->dev, "rx_esc");  in nwl_dsi_parse_dt()
1000 		DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",  in nwl_dsi_parse_dt()
1004 	dsi->rx_esc_clk = clk;  in nwl_dsi_parse_dt()
1006 	clk = devm_clk_get(dsi->dev, "tx_esc");  in nwl_dsi_parse_dt()
1009 		DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",  in nwl_dsi_parse_dt()
1013 	dsi->tx_esc_clk = clk;  in nwl_dsi_parse_dt()
1015 	dsi->mux = devm_mux_control_get(dsi->dev, NULL);  in nwl_dsi_parse_dt()
1016 	if (IS_ERR(dsi->mux)) {  in nwl_dsi_parse_dt()
1017 		ret = PTR_ERR(dsi->mux);  in nwl_dsi_parse_dt()
1018 		if (ret != -EPROBE_DEFER)  in nwl_dsi_parse_dt()
1019 			DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);  in nwl_dsi_parse_dt()
1027 	dsi->regmap =  in nwl_dsi_parse_dt()
1028 		devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);  in nwl_dsi_parse_dt()
1029 	if (IS_ERR(dsi->regmap)) {  in nwl_dsi_parse_dt()
1030 		ret = PTR_ERR(dsi->regmap);  in nwl_dsi_parse_dt()
1031 		DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",  in nwl_dsi_parse_dt()
1036 	dsi->irq = platform_get_irq(pdev, 0);  in nwl_dsi_parse_dt()
1037 	if (dsi->irq < 0) {  in nwl_dsi_parse_dt()
1038 		DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",  in nwl_dsi_parse_dt()
1039 			      dsi->irq);  in nwl_dsi_parse_dt()
1040 		return dsi->irq;  in nwl_dsi_parse_dt()
1043 	dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");  in nwl_dsi_parse_dt()
1044 	if (IS_ERR(dsi->rst_pclk)) {  in nwl_dsi_parse_dt()
1045 		DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",  in nwl_dsi_parse_dt()
1046 			      PTR_ERR(dsi->rst_pclk));  in nwl_dsi_parse_dt()
1047 		return PTR_ERR(dsi->rst_pclk);  in nwl_dsi_parse_dt()
1049 	dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");  in nwl_dsi_parse_dt()
1050 	if (IS_ERR(dsi->rst_byte)) {  in nwl_dsi_parse_dt()
1051 		DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",  in nwl_dsi_parse_dt()
1052 			      PTR_ERR(dsi->rst_byte));  in nwl_dsi_parse_dt()
1053 		return PTR_ERR(dsi->rst_byte);  in nwl_dsi_parse_dt()
1055 	dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");  in nwl_dsi_parse_dt()
1056 	if (IS_ERR(dsi->rst_esc)) {  in nwl_dsi_parse_dt()
1057 		DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",  in nwl_dsi_parse_dt()
1058 			      PTR_ERR(dsi->rst_esc));  in nwl_dsi_parse_dt()
1059 		return PTR_ERR(dsi->rst_esc);  in nwl_dsi_parse_dt()
1061 	dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");  in nwl_dsi_parse_dt()
1062 	if (IS_ERR(dsi->rst_dpi)) {  in nwl_dsi_parse_dt()
1063 		DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",  in nwl_dsi_parse_dt()
1064 			      PTR_ERR(dsi->rst_dpi));  in nwl_dsi_parse_dt()
1065 		return PTR_ERR(dsi->rst_dpi);  in nwl_dsi_parse_dt()
1076 	remote = of_graph_get_remote_node(dsi->dev->of_node, 0,  in nwl_dsi_select_input()
1081 		remote = of_graph_get_remote_node(dsi->dev->of_node, 0,  in nwl_dsi_select_input()
1084 			DRM_DEV_ERROR(dsi->dev,  in nwl_dsi_select_input()
1086 			return -EINVAL;  in nwl_dsi_select_input()
1090 	DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",  in nwl_dsi_select_input()
1092 	ret = mux_control_try_select(dsi->mux, use_dcss);  in nwl_dsi_select_input()
1094 		DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);  in nwl_dsi_select_input()
1104 	ret = mux_control_deselect(dsi->mux);  in nwl_dsi_deselect_input()
1106 		DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);  in nwl_dsi_deselect_input()
1116 	{ .compatible = "fsl,imx8mq-nwl-dsi", },
1129 	struct device *dev = &pdev->dev;  in nwl_dsi_probe()
1136 		return -ENOMEM;  in nwl_dsi_probe()
1138 	dsi->dev = dev;  in nwl_dsi_probe()
1144 	ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,  in nwl_dsi_probe()
1147 		DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,  in nwl_dsi_probe()
1152 	dsi->dsi_host.ops = &nwl_dsi_host_ops;  in nwl_dsi_probe()
1153 	dsi->dsi_host.dev = dev;  in nwl_dsi_probe()
1154 	ret = mipi_dsi_host_register(&dsi->dsi_host);  in nwl_dsi_probe()
1162 		dsi->quirks = (uintptr_t)attr->data;  in nwl_dsi_probe()
1164 	dsi->bridge.driver_private = dsi;  in nwl_dsi_probe()
1165 	dsi->bridge.funcs = &nwl_dsi_bridge_funcs;  in nwl_dsi_probe()
1166 	dsi->bridge.of_node = dev->of_node;  in nwl_dsi_probe()
1167 	dsi->bridge.timings = &nwl_dsi_timings;  in nwl_dsi_probe()
1174 		mipi_dsi_host_unregister(&dsi->dsi_host);  in nwl_dsi_probe()
1178 	drm_bridge_add(&dsi->bridge);  in nwl_dsi_probe()
1187 	mipi_dsi_host_unregister(&dsi->dsi_host);  in nwl_dsi_remove()
1188 	drm_bridge_remove(&dsi->bridge);  in nwl_dsi_remove()
1189 	pm_runtime_disable(&pdev->dev);  in nwl_dsi_remove()
1206 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");