Lines Matching +full:0 +full:x1e6e2000
44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
63 return !!(ch & 0x01); in ast_is_vga_enabled()
66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
78 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
83 if (dev->pdev->revision >= 0x20) in ast_set_def_ext_reg()
90 index = 0xa0; in ast_set_def_ext_reg()
91 while (*ext_reg_info != 0xff) { in ast_set_def_ext_reg()
92 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
98 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
105 reg = 0x04; in ast_set_def_ext_reg()
108 reg |= 0x20; in ast_set_def_ext_reg()
109 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
116 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_mindwm()
117 ast_write32(ast, 0xf000, 0x1); in ast_mindwm()
120 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_mindwm()
121 } while (data != (r & 0xffff0000)); in ast_mindwm()
122 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); in ast_mindwm()
128 ast_write32(ast, 0xf004, r & 0xffff0000); in ast_moutdwm()
129 ast_write32(ast, 0xf000, 0x1); in ast_moutdwm()
131 data = ast_read32(ast, 0xf004) & 0xffff0000; in ast_moutdwm()
132 } while (data != (r & 0xffff0000)); in ast_moutdwm()
133 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v); in ast_moutdwm()
148 0xFF00FF00,
149 0xCC33CC33,
150 0xAA55AA55,
151 0xFFFE0001,
152 0x683501FE,
153 0x0F1929B0,
154 0x2D0B4346,
155 0x60767F02,
156 0x6FBE36A6,
157 0x3A253035,
158 0x3019686D,
159 0x41C6167E,
160 0x620152BF,
161 0x20F050E0
168 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); in mmctestburst2_ast2150()
170 timeout = 0; in mmctestburst2_ast2150()
172 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
174 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
175 return 0xffffffff; in mmctestburst2_ast2150()
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); in mmctestburst2_ast2150()
180 timeout = 0; in mmctestburst2_ast2150()
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40; in mmctestburst2_ast2150()
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
185 return 0xffffffff; in mmctestburst2_ast2150()
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7; in mmctestburst2_ast2150()
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmctestburst2_ast2150()
193 #if 0 /* unused in DDX driver - here for completeness */
198 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
199 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
200 timeout = 0;
202 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
204 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
205 return 0xffffffff;
208 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
209 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
218 for (i = 0; i < 8; i++) in cbrtest_ast2150()
220 return 0; in cbrtest_ast2150()
228 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { in cbrscan_ast2150()
229 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); in cbrscan_ast2150()
230 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { in cbrscan_ast2150()
235 return 0; in cbrscan_ast2150()
246 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff; in cbrdlli_ast2150()
247 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0; in cbrdlli_ast2150()
248 passcnt = 0; in cbrdlli_ast2150()
250 for (dlli = 0; dlli < 100; dlli++) { in cbrdlli_ast2150()
251 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
253 if (data != 0) { in cbrdlli_ast2150()
254 if (data & 0x1) { in cbrdlli_ast2150()
255 if (dll_min[0] > dlli) in cbrdlli_ast2150()
256 dll_min[0] = dlli; in cbrdlli_ast2150()
257 if (dll_max[0] < dlli) in cbrdlli_ast2150()
258 dll_max[0] = dlli; in cbrdlli_ast2150()
264 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150) in cbrdlli_ast2150()
267 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); in cbrdlli_ast2150()
268 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); in cbrdlli_ast2150()
280 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
282 if ((j & 0x80) == 0) { /* VGA only */ in ast_init_dram_reg()
285 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
286 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
287 ast_write32(ast, 0x10100, 0xa8); in ast_init_dram_reg()
291 } while (ast_read32(ast, 0x10100) != 0xa8); in ast_init_dram_reg()
298 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_init_dram_reg()
299 ast_write32(ast, 0xf000, 0x1); in ast_init_dram_reg()
300 ast_write32(ast, 0x12000, 0x1688A8A8); in ast_init_dram_reg()
303 } while (ast_read32(ast, 0x12000) != 0x01); in ast_init_dram_reg()
305 ast_write32(ast, 0x10000, 0xfc600309); in ast_init_dram_reg()
308 } while (ast_read32(ast, 0x10000) != 0x01); in ast_init_dram_reg()
311 while (dram_reg_info->index != 0xffff) { in ast_init_dram_reg()
312 if (dram_reg_info->index == 0xff00) {/* delay fn */ in ast_init_dram_reg()
313 for (i = 0; i < 15; i++) in ast_init_dram_reg()
315 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) { in ast_init_dram_reg()
318 data = 0x00000d89; in ast_init_dram_reg()
320 data = 0x00000c8d; in ast_init_dram_reg()
322 temp = ast_read32(ast, 0x12070); in ast_init_dram_reg()
323 temp &= 0xc; in ast_init_dram_reg()
325 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp); in ast_init_dram_reg()
327 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data); in ast_init_dram_reg()
332 data = ast_read32(ast, 0x10120); in ast_init_dram_reg()
333 if (data == 0x5061) { /* 266Mhz */ in ast_init_dram_reg()
334 data = ast_read32(ast, 0x10004); in ast_init_dram_reg()
335 if (data & 0x40) in ast_init_dram_reg()
343 temp = ast_read32(ast, 0x10140); in ast_init_dram_reg()
344 ast_write32(ast, 0x10140, temp | 0x40); in ast_init_dram_reg()
350 temp = ast_read32(ast, 0x1200c); in ast_init_dram_reg()
351 ast_write32(ast, 0x1200c, temp & 0xfffffffd); in ast_init_dram_reg()
352 temp = ast_read32(ast, 0x12040); in ast_init_dram_reg()
353 ast_write32(ast, 0x12040, temp | 0x40); in ast_init_dram_reg()
362 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
363 } while ((j & 0x40) == 0); in ast_init_dram_reg()
371 pci_read_config_dword(dev->pdev, 0x04, ®); in ast_post_gpu()
372 reg |= 0x3; in ast_post_gpu()
373 pci_write_config_dword(dev->pdev, 0x04, reg); in ast_post_gpu()
391 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
396 #define AST_DDR3 0
438 0xFF00FF00,
439 0xCC33CC33,
440 0xAA55AA55,
441 0x88778877,
442 0x92CC4D6E,
443 0x543D3CDE,
444 0xF1E843C7,
445 0x7C61D253
452 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
453 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test()
454 timeout = 0; in mmc_test()
456 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000; in mmc_test()
457 if (data & 0x2000) in mmc_test()
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test()
464 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test()
472 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
473 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl); in mmc_test2()
474 timeout = 0; in mmc_test2()
476 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000; in mmc_test2()
478 ast_moutdwm(ast, 0x1e6e0070, 0x0); in mmc_test2()
479 return 0xffffffff; in mmc_test2()
482 data = ast_mindwm(ast, 0x1e6e0078); in mmc_test2()
483 data = (data | (data >> 16)) & 0xffff; in mmc_test2()
484 ast_moutdwm(ast, 0x1e6e0070, 0x00000000); in mmc_test2()
491 return mmc_test(ast, datagen, 0xc1); in mmc_test_burst()
496 return mmc_test2(ast, datagen, 0x41); in mmc_test_burst2()
501 return mmc_test(ast, datagen, 0xc5); in mmc_test_single()
506 return mmc_test2(ast, datagen, 0x05); in mmc_test_single2()
511 return mmc_test(ast, datagen, 0x85); in mmc_test_single_2500()
518 data = mmc_test_single2(ast, 0); in cbr_test()
519 if ((data & 0xff) && (data & 0xff00)) in cbr_test()
520 return 0; in cbr_test()
521 for (i = 0; i < 8; i++) { in cbr_test()
523 if ((data & 0xff) && (data & 0xff00)) in cbr_test()
524 return 0; in cbr_test()
528 else if (data & 0xff) in cbr_test()
538 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { in cbr_scan()
539 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan()
540 for (loop = 0; loop < CBR_PASSNUM2; loop++) { in cbr_scan()
541 if ((data = cbr_test(ast)) != 0) { in cbr_scan()
544 return 0; in cbr_scan()
549 return 0; in cbr_scan()
558 data = mmc_test_burst2(ast, 0); in cbr_test2()
559 if (data == 0xffff) in cbr_test2()
560 return 0; in cbr_test2()
561 data |= mmc_test_single2(ast, 0); in cbr_test2()
562 if (data == 0xffff) in cbr_test2()
563 return 0; in cbr_test2()
565 return ~data & 0xffff; in cbr_test2()
572 data2 = 0xffff; in cbr_scan2()
573 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { in cbr_scan2()
574 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan2()
575 for (loop = 0; loop < CBR_PASSNUM2; loop++) { in cbr_scan2()
576 if ((data = cbr_test2(ast)) != 0) { in cbr_scan2()
579 return 0; in cbr_scan2()
584 return 0; in cbr_scan2()
591 if (!mmc_test_burst(ast, 0)) in cbr_test3()
593 if (!mmc_test_single(ast, 0)) in cbr_test3()
602 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { in cbr_scan3()
603 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]); in cbr_scan3()
604 for (loop = 0; loop < 2; loop++) { in cbr_scan3()
616 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0; in finetuneDQI_L()
619 for (cnt = 0; cnt < 16; cnt++) { in finetuneDQI_L()
620 dllmin[cnt] = 0xff; in finetuneDQI_L()
621 dllmax[cnt] = 0x0; in finetuneDQI_L()
623 passcnt = 0; in finetuneDQI_L()
624 for (dlli = 0; dlli < 76; dlli++) { in finetuneDQI_L()
625 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); in finetuneDQI_L()
626 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1); in finetuneDQI_L()
628 if (data != 0) { in finetuneDQI_L()
629 mask = 0x00010001; in finetuneDQI_L()
630 for (cnt = 0; cnt < 16; cnt++) { in finetuneDQI_L()
646 gold_sadj[0] = 0x0; in finetuneDQI_L()
647 passcnt = 0; in finetuneDQI_L()
648 for (cnt = 0; cnt < 16; cnt++) { in finetuneDQI_L()
650 gold_sadj[0] += dllmin[cnt]; in finetuneDQI_L()
661 gold_sadj[0] = gold_sadj[0] >> 4; in finetuneDQI_L()
662 gold_sadj[1] = gold_sadj[0]; in finetuneDQI_L()
664 data = 0; in finetuneDQI_L()
665 for (cnt = 0; cnt < 8; cnt++) { in finetuneDQI_L()
669 if (gold_sadj[0] >= dlli) { in finetuneDQI_L()
670 dlli = ((gold_sadj[0] - dlli) * 19) >> 5; in finetuneDQI_L()
675 dlli = ((dlli - gold_sadj[0]) * 19) >> 5; in finetuneDQI_L()
679 dlli = (8 - dlli) & 0x7; in finetuneDQI_L()
684 ast_moutdwm(ast, 0x1E6E0080, data); in finetuneDQI_L()
686 data = 0; in finetuneDQI_L()
696 dlli = (dlli - 1) & 0x7; in finetuneDQI_L()
704 dlli = (8 - dlli) & 0x7; in finetuneDQI_L()
709 ast_moutdwm(ast, 0x1E6E0084, data); in finetuneDQI_L()
722 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C); in finetuneDQSI()
723 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018); in finetuneDQSI()
724 reg_mcr18 &= 0x0000ffff; in finetuneDQSI()
725 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
727 for (dlli = 0; dlli < 76; dlli++) { in finetuneDQSI()
728 tag[0][dlli] = 0x0; in finetuneDQSI()
729 tag[1][dlli] = 0x0; in finetuneDQSI()
731 for (dqidly = 0; dqidly < 32; dqidly++) { in finetuneDQSI()
732 pass[dqidly][0][0] = 0xff; in finetuneDQSI()
733 pass[dqidly][0][1] = 0x0; in finetuneDQSI()
734 pass[dqidly][1][0] = 0xff; in finetuneDQSI()
735 pass[dqidly][1][1] = 0x0; in finetuneDQSI()
737 for (dqidly = 0; dqidly < 32; dqidly++) { in finetuneDQSI()
738 passcnt[0] = passcnt[1] = 0; in finetuneDQSI()
739 for (dqsip = 0; dqsip < 2; dqsip++) { in finetuneDQSI()
740 ast_moutdwm(ast, 0x1E6E000C, 0); in finetuneDQSI()
741 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); in finetuneDQSI()
742 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c); in finetuneDQSI()
743 for (dlli = 0; dlli < 76; dlli++) { in finetuneDQSI()
744 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in finetuneDQSI()
745 ast_moutdwm(ast, 0x1E6E0070, 0); in finetuneDQSI()
746 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0); in finetuneDQSI()
748 if (dlli == 0) in finetuneDQSI()
752 if (dlli < pass[dqidly][dqsip][0]) in finetuneDQSI()
753 pass[dqidly][dqsip][0] = (u16) dlli; in finetuneDQSI()
759 pass[dqidly][dqsip][0] = 0xff; in finetuneDQSI()
760 pass[dqidly][dqsip][1] = 0x0; in finetuneDQSI()
764 if (passcnt[0] == 0 && passcnt[1] == 0) in finetuneDQSI()
768 g_dqidly = g_dqsip = g_margin = g_side = 0; in finetuneDQSI()
770 for (dqidly = 0; dqidly < 32; dqidly++) { in finetuneDQSI()
771 for (dqsip = 0; dqsip < 2; dqsip++) { in finetuneDQSI()
772 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1]) in finetuneDQSI()
774 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0]; in finetuneDQSI()
777 passcnt[0] = passcnt[1] = 0; in finetuneDQSI()
778 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++); in finetuneDQSI()
779 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++); in finetuneDQSI()
780 if (passcnt[0] > passcnt[1]) in finetuneDQSI()
781 passcnt[0] = passcnt[1]; in finetuneDQSI()
782 passcnt[1] = 0; in finetuneDQSI()
783 if (passcnt[0] > g_side) in finetuneDQSI()
784 passcnt[1] = passcnt[0] - g_side; in finetuneDQSI()
785 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) { in finetuneDQSI()
789 g_side = passcnt[0]; in finetuneDQSI()
795 g_side = passcnt[0]; in finetuneDQSI()
800 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18); in finetuneDQSI()
805 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0; in cbr_dll2()
813 dllmin[0] = dllmin[1] = 0xff; in cbr_dll2()
814 dllmax[0] = dllmax[1] = 0x0; in cbr_dll2()
815 passcnt = 0; in cbr_dll2()
816 for (dlli = 0; dlli < 76; dlli++) { in cbr_dll2()
817 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); in cbr_dll2()
818 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2); in cbr_dll2()
820 if (data != 0) { in cbr_dll2()
821 if (data & 0x1) { in cbr_dll2()
822 if (dllmin[0] > dlli) { in cbr_dll2()
823 dllmin[0] = dlli; in cbr_dll2()
825 if (dllmax[0] < dlli) { in cbr_dll2()
826 dllmax[0] = dlli; in cbr_dll2()
829 if (data & 0x2) { in cbr_dll2()
844 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) { in cbr_dll2()
847 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) { in cbr_dll2()
854 dlli += (dllmin[0] + dllmax[0]) >> 1; in cbr_dll2()
855 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16)); in cbr_dll2()
863 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr3_info()
866 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr3_info()
867 trap_AC2 = 0x00020000 + (trap << 16); in get_ddr3_info()
868 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); in get_ddr3_info()
869 trap_MRS = 0x00000010 + (trap << 4); in get_ddr3_info()
870 trap_MRS |= ((trap & 0x2) << 18); in get_ddr3_info()
872 param->reg_MADJ = 0x00034C4C; in get_ddr3_info()
873 param->reg_SADJ = 0x00001800; in get_ddr3_info()
874 param->reg_DRV = 0x000000F0; in get_ddr3_info()
876 param->rodt = 0; in get_ddr3_info()
880 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr3_info()
881 param->wodt = 0; in get_ddr3_info()
882 param->reg_AC1 = 0x22202725; in get_ddr3_info()
883 param->reg_AC2 = 0xAA007613 | trap_AC2; in get_ddr3_info()
884 param->reg_DQSIC = 0x000000BA; in get_ddr3_info()
885 param->reg_MRS = 0x04001400 | trap_MRS; in get_ddr3_info()
886 param->reg_EMRS = 0x00000000; in get_ddr3_info()
887 param->reg_IOZ = 0x00000023; in get_ddr3_info()
888 param->reg_DQIDLY = 0x00000074; in get_ddr3_info()
889 param->reg_FREQ = 0x00004DC0; in get_ddr3_info()
896 param->reg_AC2 = 0xAA007613 | trap_AC2; in get_ddr3_info()
899 param->reg_AC2 = 0xAA00761C | trap_AC2; in get_ddr3_info()
902 param->reg_AC2 = 0xAA007636 | trap_AC2; in get_ddr3_info()
908 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr3_info()
910 param->reg_AC1 = 0x33302825; in get_ddr3_info()
911 param->reg_AC2 = 0xCC009617 | trap_AC2; in get_ddr3_info()
912 param->reg_DQSIC = 0x000000E2; in get_ddr3_info()
913 param->reg_MRS = 0x04001600 | trap_MRS; in get_ddr3_info()
914 param->reg_EMRS = 0x00000000; in get_ddr3_info()
915 param->reg_IOZ = 0x00000034; in get_ddr3_info()
916 param->reg_DRV = 0x000000FA; in get_ddr3_info()
917 param->reg_DQIDLY = 0x00000089; in get_ddr3_info()
918 param->reg_FREQ = 0x00005040; in get_ddr3_info()
926 param->reg_AC2 = 0xCC009617 | trap_AC2; in get_ddr3_info()
929 param->reg_AC2 = 0xCC009622 | trap_AC2; in get_ddr3_info()
932 param->reg_AC2 = 0xCC00963F | trap_AC2; in get_ddr3_info()
938 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr3_info()
940 param->reg_AC1 = 0x33302825; in get_ddr3_info()
941 param->reg_AC2 = 0xCC009617 | trap_AC2; in get_ddr3_info()
942 param->reg_DQSIC = 0x000000E2; in get_ddr3_info()
943 param->reg_MRS = 0x04001600 | trap_MRS; in get_ddr3_info()
944 param->reg_EMRS = 0x00000000; in get_ddr3_info()
945 param->reg_IOZ = 0x00000023; in get_ddr3_info()
946 param->reg_DRV = 0x000000FA; in get_ddr3_info()
947 param->reg_DQIDLY = 0x00000089; in get_ddr3_info()
948 param->reg_FREQ = 0x000050C0; in get_ddr3_info()
956 param->reg_AC2 = 0xCC009617 | trap_AC2; in get_ddr3_info()
959 param->reg_AC2 = 0xCC009622 | trap_AC2; in get_ddr3_info()
962 param->reg_AC2 = 0xCC00963F | trap_AC2; in get_ddr3_info()
968 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr3_info()
969 param->wodt = 0; in get_ddr3_info()
970 param->reg_AC1 = 0x33302926; in get_ddr3_info()
971 param->reg_AC2 = 0xCD44961A; in get_ddr3_info()
972 param->reg_DQSIC = 0x000000FC; in get_ddr3_info()
973 param->reg_MRS = 0x00081830; in get_ddr3_info()
974 param->reg_EMRS = 0x00000000; in get_ddr3_info()
975 param->reg_IOZ = 0x00000045; in get_ddr3_info()
976 param->reg_DQIDLY = 0x00000097; in get_ddr3_info()
977 param->reg_FREQ = 0x000052C0; in get_ddr3_info()
982 ast_moutdwm(ast, 0x1E6E2020, 0x0270); in get_ddr3_info()
984 param->reg_AC1 = 0x33302926; in get_ddr3_info()
985 param->reg_AC2 = 0xDE44A61D; in get_ddr3_info()
986 param->reg_DQSIC = 0x00000117; in get_ddr3_info()
987 param->reg_MRS = 0x00081A30; in get_ddr3_info()
988 param->reg_EMRS = 0x00000000; in get_ddr3_info()
989 param->reg_IOZ = 0x070000BB; in get_ddr3_info()
990 param->reg_DQIDLY = 0x000000A0; in get_ddr3_info()
991 param->reg_FREQ = 0x000054C0; in get_ddr3_info()
996 ast_moutdwm(ast, 0x1E6E2020, 0x0290); in get_ddr3_info()
999 param->reg_AC1 = 0x33302926; in get_ddr3_info()
1000 param->reg_AC2 = 0xEF44B61E; in get_ddr3_info()
1001 param->reg_DQSIC = 0x00000125; in get_ddr3_info()
1002 param->reg_MRS = 0x00081A30; in get_ddr3_info()
1003 param->reg_EMRS = 0x00000040; in get_ddr3_info()
1004 param->reg_DRV = 0x000000F5; in get_ddr3_info()
1005 param->reg_IOZ = 0x00000023; in get_ddr3_info()
1006 param->reg_DQIDLY = 0x00000088; in get_ddr3_info()
1007 param->reg_FREQ = 0x000055C0; in get_ddr3_info()
1012 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr3_info()
1013 param->reg_MADJ = 0x00136868; in get_ddr3_info()
1014 param->reg_SADJ = 0x00004534; in get_ddr3_info()
1017 param->reg_AC1 = 0x33302A37; in get_ddr3_info()
1018 param->reg_AC2 = 0xEF56B61E; in get_ddr3_info()
1019 param->reg_DQSIC = 0x0000013F; in get_ddr3_info()
1020 param->reg_MRS = 0x00101A50; in get_ddr3_info()
1021 param->reg_EMRS = 0x00000040; in get_ddr3_info()
1022 param->reg_DRV = 0x000000FA; in get_ddr3_info()
1023 param->reg_IOZ = 0x00000023; in get_ddr3_info()
1024 param->reg_DQIDLY = 0x00000078; in get_ddr3_info()
1025 param->reg_FREQ = 0x000057C0; in get_ddr3_info()
1030 ast_moutdwm(ast, 0x1E6E2020, 0x02E1); in get_ddr3_info()
1031 param->reg_MADJ = 0x00136868; in get_ddr3_info()
1032 param->reg_SADJ = 0x00004534; in get_ddr3_info()
1035 param->reg_AC1 = 0x32302A37; in get_ddr3_info()
1036 param->reg_AC2 = 0xDF56B61F; in get_ddr3_info()
1037 param->reg_DQSIC = 0x0000014D; in get_ddr3_info()
1038 param->reg_MRS = 0x00101A50; in get_ddr3_info()
1039 param->reg_EMRS = 0x00000004; in get_ddr3_info()
1040 param->reg_DRV = 0x000000F5; in get_ddr3_info()
1041 param->reg_IOZ = 0x00000023; in get_ddr3_info()
1042 param->reg_DQIDLY = 0x00000078; in get_ddr3_info()
1043 param->reg_FREQ = 0x000058C0; in get_ddr3_info()
1048 ast_moutdwm(ast, 0x1E6E2020, 0x0160); in get_ddr3_info()
1049 param->reg_MADJ = 0x00136868; in get_ddr3_info()
1050 param->reg_SADJ = 0x00004534; in get_ddr3_info()
1053 param->reg_AC1 = 0x32302A37; in get_ddr3_info()
1054 param->reg_AC2 = 0xEF56B621; in get_ddr3_info()
1055 param->reg_DQSIC = 0x0000015A; in get_ddr3_info()
1056 param->reg_MRS = 0x02101A50; in get_ddr3_info()
1057 param->reg_EMRS = 0x00000004; in get_ddr3_info()
1058 param->reg_DRV = 0x000000F5; in get_ddr3_info()
1059 param->reg_IOZ = 0x00000034; in get_ddr3_info()
1060 param->reg_DQIDLY = 0x00000078; in get_ddr3_info()
1061 param->reg_FREQ = 0x000059C0; in get_ddr3_info()
1069 param->dram_config = 0x130; in get_ddr3_info()
1073 param->dram_config = 0x131; in get_ddr3_info()
1076 param->dram_config = 0x132; in get_ddr3_info()
1079 param->dram_config = 0x133; in get_ddr3_info()
1086 param->dram_config |= 0x00; in get_ddr3_info()
1089 param->dram_config |= 0x04; in get_ddr3_info()
1092 param->dram_config |= 0x08; in get_ddr3_info()
1095 param->dram_config |= 0x0c; in get_ddr3_info()
1103 u32 data, data2, retry = 0; in ddr3_init()
1106 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr3_init()
1107 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr3_init()
1108 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr3_init()
1109 ast_moutdwm(ast, 0x1E6E0034, 0x00000000); in ddr3_init()
1111 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr3_init()
1112 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr3_init()
1114 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr3_init()
1117 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr3_init()
1118 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr3_init()
1119 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr3_init()
1120 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr3_init()
1121 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr3_init()
1122 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr3_init()
1123 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr3_init()
1124 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr3_init()
1125 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170); in ddr3_init()
1126 ast_moutdwm(ast, 0x1E6E0018, 0x00002370); in ddr3_init()
1127 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr3_init()
1128 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444); in ddr3_init()
1129 ast_moutdwm(ast, 0x1E6E0044, 0x22222222); in ddr3_init()
1130 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr3_init()
1131 ast_moutdwm(ast, 0x1E6E004C, 0x00000002); in ddr3_init()
1132 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1133 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1134 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr3_init()
1135 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr3_init()
1136 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr3_init()
1137 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1138 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr3_init()
1139 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr3_init()
1140 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1143 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1144 } while (!(data & 0x08000000)); in ddr3_init()
1145 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1146 data = (data >> 8) & 0xff; in ddr3_init()
1147 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { in ddr3_init()
1148 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr3_init()
1149 if ((data2 & 0xff) > param->madj_max) { in ddr3_init()
1152 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr3_init()
1153 if (data2 & 0x00100000) { in ddr3_init()
1154 data2 = ((data2 & 0xff) >> 3) + 3; in ddr3_init()
1156 data2 = ((data2 & 0xff) >> 2) + 5; in ddr3_init()
1158 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr3_init()
1159 data2 += data & 0xff; in ddr3_init()
1161 ast_moutdwm(ast, 0x1E6E0068, data); in ddr3_init()
1163 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr3_init()
1165 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr3_init()
1166 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1167 data = data | 0x200; in ddr3_init()
1168 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1170 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1171 } while (!(data & 0x08000000)); in ddr3_init()
1173 data = ast_mindwm(ast, 0x1E6E001C); in ddr3_init()
1174 data = (data >> 8) & 0xff; in ddr3_init()
1176 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff); in ddr3_init()
1177 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr3_init()
1178 ast_moutdwm(ast, 0x1E6E0018, data); in ddr3_init()
1180 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr3_init()
1181 ast_moutdwm(ast, 0x1E6E000C, 0x00000040); in ddr3_init()
1184 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr3_init()
1185 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr3_init()
1186 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr3_init()
1187 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr3_init()
1188 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr3_init()
1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1190 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr3_init()
1191 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr3_init()
1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr3_init()
1194 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr3_init()
1195 data = 0; in ddr3_init()
1197 data = 0x300; in ddr3_init()
1200 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); in ddr3_init()
1202 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr3_init()
1208 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr3_init()
1211 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr3_init()
1212 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr3_init()
1214 data = ast_mindwm(ast, 0x1E6E0070); in ddr3_init()
1215 } while (!(data & 0x00001000)); in ddr3_init()
1216 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr3_init()
1217 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr3_init()
1218 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr3_init()
1228 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in get_ddr2_info()
1231 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3; in get_ddr2_info()
1233 trap_AC2 += 0x00110000; in get_ddr2_info()
1234 trap_MRS = 0x00000040 | (trap << 4); in get_ddr2_info()
1237 param->reg_MADJ = 0x00034C4C; in get_ddr2_info()
1238 param->reg_SADJ = 0x00001800; in get_ddr2_info()
1239 param->reg_DRV = 0x000000F0; in get_ddr2_info()
1241 param->rodt = 0; in get_ddr2_info()
1245 ast_moutdwm(ast, 0x1E6E2020, 0x0130); in get_ddr2_info()
1246 param->wodt = 0; in get_ddr2_info()
1247 param->reg_AC1 = 0x11101513; in get_ddr2_info()
1248 param->reg_AC2 = 0x78117011; in get_ddr2_info()
1249 param->reg_DQSIC = 0x00000092; in get_ddr2_info()
1250 param->reg_MRS = 0x00000842; in get_ddr2_info()
1251 param->reg_EMRS = 0x00000000; in get_ddr2_info()
1252 param->reg_DRV = 0x000000F0; in get_ddr2_info()
1253 param->reg_IOZ = 0x00000034; in get_ddr2_info()
1254 param->reg_DQIDLY = 0x0000005A; in get_ddr2_info()
1255 param->reg_FREQ = 0x00004AC0; in get_ddr2_info()
1260 ast_moutdwm(ast, 0x1E6E2020, 0x0190); in get_ddr2_info()
1262 param->reg_AC1 = 0x22202613; in get_ddr2_info()
1263 param->reg_AC2 = 0xAA009016 | trap_AC2; in get_ddr2_info()
1264 param->reg_DQSIC = 0x000000BA; in get_ddr2_info()
1265 param->reg_MRS = 0x00000A02 | trap_MRS; in get_ddr2_info()
1266 param->reg_EMRS = 0x00000040; in get_ddr2_info()
1267 param->reg_DRV = 0x000000FA; in get_ddr2_info()
1268 param->reg_IOZ = 0x00000034; in get_ddr2_info()
1269 param->reg_DQIDLY = 0x00000074; in get_ddr2_info()
1270 param->reg_FREQ = 0x00004DC0; in get_ddr2_info()
1276 param->reg_AC2 = 0xAA009012 | trap_AC2; in get_ddr2_info()
1279 param->reg_AC2 = 0xAA009016 | trap_AC2; in get_ddr2_info()
1282 param->reg_AC2 = 0xAA009023 | trap_AC2; in get_ddr2_info()
1285 param->reg_AC2 = 0xAA00903B | trap_AC2; in get_ddr2_info()
1291 ast_moutdwm(ast, 0x1E6E2020, 0x03F1); in get_ddr2_info()
1293 param->rodt = 0; in get_ddr2_info()
1294 param->reg_AC1 = 0x33302714; in get_ddr2_info()
1295 param->reg_AC2 = 0xCC00B01B | trap_AC2; in get_ddr2_info()
1296 param->reg_DQSIC = 0x000000E2; in get_ddr2_info()
1297 param->reg_MRS = 0x00000C02 | trap_MRS; in get_ddr2_info()
1298 param->reg_EMRS = 0x00000040; in get_ddr2_info()
1299 param->reg_DRV = 0x000000FA; in get_ddr2_info()
1300 param->reg_IOZ = 0x00000034; in get_ddr2_info()
1301 param->reg_DQIDLY = 0x00000089; in get_ddr2_info()
1302 param->reg_FREQ = 0x00005040; in get_ddr2_info()
1308 param->reg_AC2 = 0xCC00B016 | trap_AC2; in get_ddr2_info()
1312 param->reg_AC2 = 0xCC00B01B | trap_AC2; in get_ddr2_info()
1315 param->reg_AC2 = 0xCC00B02B | trap_AC2; in get_ddr2_info()
1318 param->reg_AC2 = 0xCC00B03F | trap_AC2; in get_ddr2_info()
1325 ast_moutdwm(ast, 0x1E6E2020, 0x01F0); in get_ddr2_info()
1327 param->rodt = 0; in get_ddr2_info()
1328 param->reg_AC1 = 0x33302714; in get_ddr2_info()
1329 param->reg_AC2 = 0xCC00B01B | trap_AC2; in get_ddr2_info()
1330 param->reg_DQSIC = 0x000000E2; in get_ddr2_info()
1331 param->reg_MRS = 0x00000C02 | trap_MRS; in get_ddr2_info()
1332 param->reg_EMRS = 0x00000040; in get_ddr2_info()
1333 param->reg_DRV = 0x000000FA; in get_ddr2_info()
1334 param->reg_IOZ = 0x00000034; in get_ddr2_info()
1335 param->reg_DQIDLY = 0x00000089; in get_ddr2_info()
1336 param->reg_FREQ = 0x000050C0; in get_ddr2_info()
1342 param->reg_AC2 = 0xCC00B016 | trap_AC2; in get_ddr2_info()
1346 param->reg_AC2 = 0xCC00B01B | trap_AC2; in get_ddr2_info()
1349 param->reg_AC2 = 0xCC00B02B | trap_AC2; in get_ddr2_info()
1352 param->reg_AC2 = 0xCC00B03F | trap_AC2; in get_ddr2_info()
1358 ast_moutdwm(ast, 0x1E6E2020, 0x0230); in get_ddr2_info()
1359 param->wodt = 0; in get_ddr2_info()
1360 param->reg_AC1 = 0x33302815; in get_ddr2_info()
1361 param->reg_AC2 = 0xCD44B01E; in get_ddr2_info()
1362 param->reg_DQSIC = 0x000000FC; in get_ddr2_info()
1363 param->reg_MRS = 0x00000E72; in get_ddr2_info()
1364 param->reg_EMRS = 0x00000000; in get_ddr2_info()
1365 param->reg_DRV = 0x00000000; in get_ddr2_info()
1366 param->reg_IOZ = 0x00000034; in get_ddr2_info()
1367 param->reg_DQIDLY = 0x00000097; in get_ddr2_info()
1368 param->reg_FREQ = 0x000052C0; in get_ddr2_info()
1373 ast_moutdwm(ast, 0x1E6E2020, 0x0261); in get_ddr2_info()
1376 param->reg_AC1 = 0x33302815; in get_ddr2_info()
1377 param->reg_AC2 = 0xDE44C022; in get_ddr2_info()
1378 param->reg_DQSIC = 0x00000117; in get_ddr2_info()
1379 param->reg_MRS = 0x00000E72; in get_ddr2_info()
1380 param->reg_EMRS = 0x00000040; in get_ddr2_info()
1381 param->reg_DRV = 0x0000000A; in get_ddr2_info()
1382 param->reg_IOZ = 0x00000045; in get_ddr2_info()
1383 param->reg_DQIDLY = 0x000000A0; in get_ddr2_info()
1384 param->reg_FREQ = 0x000054C0; in get_ddr2_info()
1389 ast_moutdwm(ast, 0x1E6E2020, 0x0120); in get_ddr2_info()
1392 param->reg_AC1 = 0x33302815; in get_ddr2_info()
1393 param->reg_AC2 = 0xEF44D024; in get_ddr2_info()
1394 param->reg_DQSIC = 0x00000125; in get_ddr2_info()
1395 param->reg_MRS = 0x00000E72; in get_ddr2_info()
1396 param->reg_EMRS = 0x00000004; in get_ddr2_info()
1397 param->reg_DRV = 0x000000F9; in get_ddr2_info()
1398 param->reg_IOZ = 0x00000045; in get_ddr2_info()
1399 param->reg_DQIDLY = 0x000000A7; in get_ddr2_info()
1400 param->reg_FREQ = 0x000055C0; in get_ddr2_info()
1405 ast_moutdwm(ast, 0x1E6E2020, 0x02A1); in get_ddr2_info()
1408 param->reg_AC1 = 0x43402915; in get_ddr2_info()
1409 param->reg_AC2 = 0xFF44E025; in get_ddr2_info()
1410 param->reg_DQSIC = 0x00000132; in get_ddr2_info()
1411 param->reg_MRS = 0x00000E72; in get_ddr2_info()
1412 param->reg_EMRS = 0x00000040; in get_ddr2_info()
1413 param->reg_DRV = 0x0000000A; in get_ddr2_info()
1414 param->reg_IOZ = 0x00000045; in get_ddr2_info()
1415 param->reg_DQIDLY = 0x000000AD; in get_ddr2_info()
1416 param->reg_FREQ = 0x000056C0; in get_ddr2_info()
1421 ast_moutdwm(ast, 0x1E6E2020, 0x0140); in get_ddr2_info()
1424 param->reg_AC1 = 0x43402915; in get_ddr2_info()
1425 param->reg_AC2 = 0xFF44E027; in get_ddr2_info()
1426 param->reg_DQSIC = 0x0000013F; in get_ddr2_info()
1427 param->reg_MRS = 0x00000E72; in get_ddr2_info()
1428 param->reg_EMRS = 0x00000004; in get_ddr2_info()
1429 param->reg_DRV = 0x000000F5; in get_ddr2_info()
1430 param->reg_IOZ = 0x00000045; in get_ddr2_info()
1431 param->reg_DQIDLY = 0x000000B3; in get_ddr2_info()
1432 param->reg_FREQ = 0x000057C0; in get_ddr2_info()
1440 param->dram_config = 0x100; in get_ddr2_info()
1444 param->dram_config = 0x121; in get_ddr2_info()
1447 param->dram_config = 0x122; in get_ddr2_info()
1450 param->dram_config = 0x123; in get_ddr2_info()
1457 param->dram_config |= 0x00; in get_ddr2_info()
1460 param->dram_config |= 0x04; in get_ddr2_info()
1463 param->dram_config |= 0x08; in get_ddr2_info()
1466 param->dram_config |= 0x0c; in get_ddr2_info()
1473 u32 data, data2, retry = 0; in ddr2_init()
1476 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in ddr2_init()
1477 ast_moutdwm(ast, 0x1E6E0018, 0x00000100); in ddr2_init()
1478 ast_moutdwm(ast, 0x1E6E0024, 0x00000000); in ddr2_init()
1479 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ); in ddr2_init()
1480 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ); in ddr2_init()
1482 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); in ddr2_init()
1485 ast_moutdwm(ast, 0x1E6E0004, param->dram_config); in ddr2_init()
1486 ast_moutdwm(ast, 0x1E6E0008, 0x90040f); in ddr2_init()
1487 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1); in ddr2_init()
1488 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2); in ddr2_init()
1489 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); in ddr2_init()
1490 ast_moutdwm(ast, 0x1E6E0080, 0x00000000); in ddr2_init()
1491 ast_moutdwm(ast, 0x1E6E0084, 0x00000000); in ddr2_init()
1492 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); in ddr2_init()
1493 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130); in ddr2_init()
1494 ast_moutdwm(ast, 0x1E6E0018, 0x00002330); in ddr2_init()
1495 ast_moutdwm(ast, 0x1E6E0038, 0x00000000); in ddr2_init()
1496 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000); in ddr2_init()
1497 ast_moutdwm(ast, 0x1E6E0044, 0x88848466); in ddr2_init()
1498 ast_moutdwm(ast, 0x1E6E0048, 0x44440008); in ddr2_init()
1499 ast_moutdwm(ast, 0x1E6E004C, 0x00000000); in ddr2_init()
1500 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1501 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1502 ast_moutdwm(ast, 0x1E6E0054, 0); in ddr2_init()
1503 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV); in ddr2_init()
1504 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ); in ddr2_init()
1505 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1506 ast_moutdwm(ast, 0x1E6E0074, 0x00000000); in ddr2_init()
1507 ast_moutdwm(ast, 0x1E6E0078, 0x00000000); in ddr2_init()
1508 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1512 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1513 } while (!(data & 0x08000000)); in ddr2_init()
1514 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1515 data = (data >> 8) & 0xff; in ddr2_init()
1516 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { in ddr2_init()
1517 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; in ddr2_init()
1518 if ((data2 & 0xff) > param->madj_max) { in ddr2_init()
1521 ast_moutdwm(ast, 0x1E6E0064, data2); in ddr2_init()
1522 if (data2 & 0x00100000) { in ddr2_init()
1523 data2 = ((data2 & 0xff) >> 3) + 3; in ddr2_init()
1525 data2 = ((data2 & 0xff) >> 2) + 5; in ddr2_init()
1527 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff; in ddr2_init()
1528 data2 += data & 0xff; in ddr2_init()
1530 ast_moutdwm(ast, 0x1E6E0068, data); in ddr2_init()
1532 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000); in ddr2_init()
1534 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff; in ddr2_init()
1535 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1536 data = data | 0x200; in ddr2_init()
1537 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1539 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1540 } while (!(data & 0x08000000)); in ddr2_init()
1542 data = ast_mindwm(ast, 0x1E6E001C); in ddr2_init()
1543 data = (data >> 8) & 0xff; in ddr2_init()
1545 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff); in ddr2_init()
1546 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00; in ddr2_init()
1547 ast_moutdwm(ast, 0x1E6E0018, data); in ddr2_init()
1549 ast_moutdwm(ast, 0x1E6E0034, 0x00000001); in ddr2_init()
1550 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr2_init()
1553 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); in ddr2_init()
1554 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1555 ast_moutdwm(ast, 0x1E6E0028, 0x00000005); in ddr2_init()
1556 ast_moutdwm(ast, 0x1E6E0028, 0x00000007); in ddr2_init()
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1560 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08); in ddr2_init()
1561 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS); in ddr2_init()
1562 ast_moutdwm(ast, 0x1E6E0028, 0x00000001); in ddr2_init()
1563 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); in ddr2_init()
1564 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1565 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS); in ddr2_init()
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000003); in ddr2_init()
1568 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); in ddr2_init()
1569 data = 0; in ddr2_init()
1571 data = 0x500; in ddr2_init()
1574 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); in ddr2_init()
1576 ast_moutdwm(ast, 0x1E6E0034, data | 0x3); in ddr2_init()
1577 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ); in ddr2_init()
1585 ast_moutdwm(ast, 0x1E6E007C, 0x00000000); in ddr2_init()
1586 ast_moutdwm(ast, 0x1E6E0070, 0x221); in ddr2_init()
1588 data = ast_mindwm(ast, 0x1E6E0070); in ddr2_init()
1589 } while (!(data & 0x00001000)); in ddr2_init()
1590 ast_moutdwm(ast, 0x1E6E0070, 0x00000000); in ddr2_init()
1591 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr2_init()
1592 ast_moutdwm(ast, 0x1E6E0050, 0x00000000); in ddr2_init()
1604 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1605 if ((reg & 0x80) == 0) {/* vga only */ in ast_post_chip_2300()
1606 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2300()
1607 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2300()
1608 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2300()
1611 } while (ast_read32(ast, 0x12000) != 0x1); in ast_post_chip_2300()
1613 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2300()
1616 } while (ast_read32(ast, 0x10000) != 0x1); in ast_post_chip_2300()
1619 temp = ast_read32(ast, 0x12008); in ast_post_chip_2300()
1620 temp |= 0x73; in ast_post_chip_2300()
1621 ast_write32(ast, 0x12008, temp); in ast_post_chip_2300()
1625 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2300()
1626 if (temp & 0x01000000) in ast_post_chip_2300()
1628 switch (temp & 0x18000000) { in ast_post_chip_2300()
1629 case 0: in ast_post_chip_2300()
1633 case 0x08000000: in ast_post_chip_2300()
1636 case 0x10000000: in ast_post_chip_2300()
1639 case 0x18000000: in ast_post_chip_2300()
1643 switch (temp & 0x0c) { in ast_post_chip_2300()
1645 case 0x00: in ast_post_chip_2300()
1649 case 0x04: in ast_post_chip_2300()
1653 case 0x08: in ast_post_chip_2300()
1657 case 0x0c: in ast_post_chip_2300()
1670 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2300()
1671 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2300()
1676 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2300()
1677 } while ((reg & 0x40) == 0); in ast_post_chip_2300()
1682 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in cbr_test_2500()
1683 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in cbr_test_2500()
1684 if (!mmc_test_burst(ast, 0)) in cbr_test_2500()
1686 if (!mmc_test_single_2500(ast, 0)) in cbr_test_2500()
1693 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF); in ddr_test_2500()
1694 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00); in ddr_test_2500()
1695 if (!mmc_test_burst(ast, 0)) in ddr_test_2500()
1703 if (!mmc_test_single_2500(ast, 0)) in ddr_test_2500()
1710 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in ddr_init_common_2500()
1711 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F); in ddr_init_common_2500()
1712 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF); in ddr_init_common_2500()
1713 ast_moutdwm(ast, 0x1E6E0040, 0x88448844); in ddr_init_common_2500()
1714 ast_moutdwm(ast, 0x1E6E0044, 0x24422288); in ddr_init_common_2500()
1715 ast_moutdwm(ast, 0x1E6E0048, 0x22222222); in ddr_init_common_2500()
1716 ast_moutdwm(ast, 0x1E6E004C, 0x22222222); in ddr_init_common_2500()
1717 ast_moutdwm(ast, 0x1E6E0050, 0x80000000); in ddr_init_common_2500()
1718 ast_moutdwm(ast, 0x1E6E0208, 0x00000000); in ddr_init_common_2500()
1719 ast_moutdwm(ast, 0x1E6E0218, 0x00000000); in ddr_init_common_2500()
1720 ast_moutdwm(ast, 0x1E6E0220, 0x00000000); in ddr_init_common_2500()
1721 ast_moutdwm(ast, 0x1E6E0228, 0x00000000); in ddr_init_common_2500()
1722 ast_moutdwm(ast, 0x1E6E0230, 0x00000000); in ddr_init_common_2500()
1723 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000); in ddr_init_common_2500()
1724 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000); in ddr_init_common_2500()
1725 ast_moutdwm(ast, 0x1E6E0240, 0x86000000); in ddr_init_common_2500()
1726 ast_moutdwm(ast, 0x1E6E0244, 0x00008600); in ddr_init_common_2500()
1727 ast_moutdwm(ast, 0x1E6E0248, 0x80000000); in ddr_init_common_2500()
1728 ast_moutdwm(ast, 0x1E6E024C, 0x80808080); in ddr_init_common_2500()
1735 pass = 0; in ddr_phy_init_2500()
1736 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1738 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) { in ddr_phy_init_2500()
1739 data = ast_mindwm(ast, 0x1E6E0060) & 0x1; in ddr_phy_init_2500()
1744 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000; in ddr_phy_init_2500()
1749 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr_phy_init_2500()
1751 ast_moutdwm(ast, 0x1E6E0060, 0x00000005); in ddr_phy_init_2500()
1755 ast_moutdwm(ast, 0x1E6E0060, 0x00000006); in ddr_phy_init_2500()
1760 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1761 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1762 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1763 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc; in check_dram_size_2500()
1770 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00; in check_dram_size_2500()
1772 ast_moutdwm(ast, 0xA0100000, 0x41424344); in check_dram_size_2500()
1773 ast_moutdwm(ast, 0x90100000, 0x35363738); in check_dram_size_2500()
1774 ast_moutdwm(ast, 0x88100000, 0x292A2B2C); in check_dram_size_2500()
1775 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10); in check_dram_size_2500()
1778 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) { in check_dram_size_2500()
1779 reg_04 |= 0x03; in check_dram_size_2500()
1780 reg_14 |= (tRFC >> 24) & 0xFF; in check_dram_size_2500()
1782 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) { in check_dram_size_2500()
1783 reg_04 |= 0x02; in check_dram_size_2500()
1784 reg_14 |= (tRFC >> 16) & 0xFF; in check_dram_size_2500()
1786 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) { in check_dram_size_2500()
1787 reg_04 |= 0x01; in check_dram_size_2500()
1788 reg_14 |= (tRFC >> 8) & 0xFF; in check_dram_size_2500()
1790 reg_14 |= tRFC & 0xFF; in check_dram_size_2500()
1792 ast_moutdwm(ast, 0x1E6E0004, reg_04); in check_dram_size_2500()
1793 ast_moutdwm(ast, 0x1E6E0014, reg_14); in check_dram_size_2500()
1800 reg_04 = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1801 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000); in enable_cache_2500()
1804 data = ast_mindwm(ast, 0x1E6E0004); in enable_cache_2500()
1805 while (!(data & 0x80000)); in enable_cache_2500()
1806 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400); in enable_cache_2500()
1814 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in set_mpll_2500()
1815 ast_moutdwm(ast, 0x1E6E0034, 0x00020080); in set_mpll_2500()
1816 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) { in set_mpll_2500()
1817 ast_moutdwm(ast, addr, 0x0); in set_mpll_2500()
1820 ast_moutdwm(ast, 0x1E6E0034, 0x00020000); in set_mpll_2500()
1822 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8); in set_mpll_2500()
1823 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000; in set_mpll_2500()
1826 param = 0x930023E0; in set_mpll_2500()
1827 ast_moutdwm(ast, 0x1E6E2160, 0x00011320); in set_mpll_2500()
1830 param = 0x93002400; in set_mpll_2500()
1832 ast_moutdwm(ast, 0x1E6E2020, param); in set_mpll_2500()
1838 ast_moutdwm(ast, 0x1E78505C, 0x00000004); in reset_mmc_2500()
1839 ast_moutdwm(ast, 0x1E785044, 0x00000001); in reset_mmc_2500()
1840 ast_moutdwm(ast, 0x1E785048, 0x00004755); in reset_mmc_2500()
1841 ast_moutdwm(ast, 0x1E78504C, 0x00000013); in reset_mmc_2500()
1843 ast_moutdwm(ast, 0x1E785054, 0x00000077); in reset_mmc_2500()
1844 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309); in reset_mmc_2500()
1850 ast_moutdwm(ast, 0x1E6E0004, 0x00000303); in ddr3_init_2500()
1851 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr3_init_2500()
1852 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr3_init_2500()
1853 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr3_init_2500()
1854 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr3_init_2500()
1855 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr3_init_2500()
1856 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr3_init_2500()
1857 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr3_init_2500()
1860 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE); in ddr3_init_2500()
1861 ast_moutdwm(ast, 0x1E6E0204, 0x00001001); in ddr3_init_2500()
1862 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr3_init_2500()
1863 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr3_init_2500()
1864 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr3_init_2500()
1865 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr3_init_2500()
1866 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr3_init_2500()
1867 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr3_init_2500()
1868 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr3_init_2500()
1869 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr3_init_2500()
1870 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr3_init_2500()
1871 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr3_init_2500()
1872 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr3_init_2500()
1873 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006); in ddr3_init_2500()
1876 ast_moutdwm(ast, 0x1E6E0034, 0x00020091); in ddr3_init_2500()
1881 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr3_init_2500()
1882 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr3_init_2500()
1883 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr3_init_2500()
1887 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr3_init_2500()
1888 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr3_init_2500()
1895 u32 min_ddr_vref = 0, min_phy_vref = 0; in ddr4_init_2500()
1896 u32 max_ddr_vref = 0, max_phy_vref = 0; in ddr4_init_2500()
1898 ast_moutdwm(ast, 0x1E6E0004, 0x00000313); in ddr4_init_2500()
1899 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]); in ddr4_init_2500()
1900 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]); in ddr4_init_2500()
1901 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]); in ddr4_init_2500()
1902 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */ in ddr4_init_2500()
1903 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */ in ddr4_init_2500()
1904 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */ in ddr4_init_2500()
1905 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */ in ddr4_init_2500()
1908 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE); in ddr4_init_2500()
1909 ast_moutdwm(ast, 0x1E6E0204, 0x09002000); in ddr4_init_2500()
1910 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B); in ddr4_init_2500()
1911 ast_moutdwm(ast, 0x1E6E0210, 0x20000000); in ddr4_init_2500()
1912 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]); in ddr4_init_2500()
1913 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]); in ddr4_init_2500()
1914 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]); in ddr4_init_2500()
1915 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]); in ddr4_init_2500()
1916 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]); in ddr4_init_2500()
1917 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]); in ddr4_init_2500()
1918 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]); in ddr4_init_2500()
1919 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]); in ddr4_init_2500()
1920 ast_moutdwm(ast, 0x1E6E0290, 0x00100008); in ddr4_init_2500()
1921 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C); in ddr4_init_2500()
1922 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E); in ddr4_init_2500()
1925 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991); in ddr4_init_2500()
1928 pass = 0; in ddr4_init_2500()
1930 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { in ddr4_init_2500()
1931 max_phy_vref = 0x0; in ddr4_init_2500()
1932 pass = 0; in ddr4_init_2500()
1933 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06); in ddr4_init_2500()
1934 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) { in ddr4_init_2500()
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1937 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8)); in ddr4_init_2500()
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1943 data = ast_mindwm(ast, 0x1E6E03D0); in ddr4_init_2500()
1945 data = data & 0xff; in ddr4_init_2500()
1952 } else if (pass > 0) in ddr4_init_2500()
1956 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8)); in ddr4_init_2500()
1959 pass = 0; in ddr4_init_2500()
1961 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) { in ddr4_init_2500()
1962 min_ddr_vref = 0xFF; in ddr4_init_2500()
1963 max_ddr_vref = 0x0; in ddr4_init_2500()
1964 pass = 0; in ddr4_init_2500()
1965 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) { in ddr4_init_2500()
1966 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1967 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1968 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1971 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01); in ddr4_init_2500()
1978 } else if (pass != 0) in ddr4_init_2500()
1983 ast_moutdwm(ast, 0x1E6E000C, 0x00000000); in ddr4_init_2500()
1984 ast_moutdwm(ast, 0x1E6E0060, 0x00000000); in ddr4_init_2500()
1986 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8)); in ddr4_init_2500()
1991 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]); in ddr4_init_2500()
1992 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81); in ddr4_init_2500()
1993 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93); in ddr4_init_2500()
1997 ast_moutdwm(ast, 0x1E6E001C, 0x00000008); in ddr4_init_2500()
1998 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00); in ddr4_init_2500()
2007 if (max_tries-- == 0) in ast_dram_init_2500()
2013 data = ast_mindwm(ast, 0x1E6E2070); in ast_dram_init_2500()
2014 if (data & 0x01000000) in ast_dram_init_2500()
2020 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41); in ast_dram_init_2500()
2023 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF; in ast_dram_init_2500()
2024 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000); in ast_dram_init_2500()
2035 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()
2036 if ((reg & 0x80) == 0) {/* vga only */ in ast_post_chip_2500()
2038 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); in ast_post_chip_2500()
2039 ast_moutdwm(ast, 0x1e600084, 0x00010000); in ast_post_chip_2500()
2040 ast_moutdwm(ast, 0x1e600088, 0x00000000); in ast_post_chip_2500()
2041 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); in ast_post_chip_2500()
2042 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_post_chip_2500()
2043 ast_write32(ast, 0xf000, 0x1); in ast_post_chip_2500()
2044 ast_write32(ast, 0x12000, 0x1688a8a8); in ast_post_chip_2500()
2045 while (ast_read32(ast, 0x12000) != 0x1) in ast_post_chip_2500()
2048 ast_write32(ast, 0x10000, 0xfc600309); in ast_post_chip_2500()
2049 while (ast_read32(ast, 0x10000) != 0x1) in ast_post_chip_2500()
2053 temp = ast_read32(ast, 0x12008); in ast_post_chip_2500()
2054 temp |= 0x73; in ast_post_chip_2500()
2055 ast_write32(ast, 0x12008, temp); in ast_post_chip_2500()
2058 ast_moutdwm(ast, 0x1e6e2090, 0x20000000); in ast_post_chip_2500()
2059 temp = ast_mindwm(ast, 0x1e6e2094); in ast_post_chip_2500()
2060 temp |= 0x00004000; in ast_post_chip_2500()
2061 ast_moutdwm(ast, 0x1e6e2094, temp); in ast_post_chip_2500()
2062 temp = ast_mindwm(ast, 0x1e6e2070); in ast_post_chip_2500()
2063 if (temp & 0x00800000) { in ast_post_chip_2500()
2064 ast_moutdwm(ast, 0x1e6e207c, 0x00800000); in ast_post_chip_2500()
2066 ast_moutdwm(ast, 0x1e6e2070, 0x00800000); in ast_post_chip_2500()
2072 temp = ast_mindwm(ast, 0x1e6e2040); in ast_post_chip_2500()
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40); in ast_post_chip_2500()
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_post_chip_2500()
2079 } while ((reg & 0x40) == 0); in ast_post_chip_2500()