Lines Matching refs:dpm
76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
379 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
905 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
978 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1039 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1105 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1231 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1243 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1361 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1363 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1374 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1583 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1614 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_get_acp_boot_level()
1647 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1778 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1899 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1908 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
2055 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2057 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2059 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2061 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2174 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2215 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2218 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2221 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2222 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2248 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2249 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2310 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2352 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2369 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2419 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2543 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2544 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2617 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2672 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2676 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2735 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in kv_parse_power_table()
2738 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2749 kfree(adev->pm.dpm.ps); in kv_parse_power_table()
2752 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2765 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2769 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2774 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2777 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in kv_parse_power_table()
2779 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2784 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2785 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2799 adev->pm.dpm.priv = pi; in kv_dpm_init()
2915 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2916 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2918 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2919 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2998 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3003 &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3008 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3009 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3010 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3020 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3025 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3044 flush_work(&adev->pm.dpm.thermal.work); in kv_dpm_sw_fini()
3095 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3198 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3203 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3211 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3380 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3381 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()