Lines Matching +full:0 +full:x7

51 #define DPM_NO_LIMIT 0
56 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
57 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
63 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
64 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
66 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
68 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
70 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
72 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
74 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
76 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
78 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
80 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
82 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
88 #define VRCONF_VDDC_MASK         0x000000FF
89 #define VRCONF_VDDC_SHIFT        0
90 #define VRCONF_VDDGFX_MASK       0x0000FF00
92 #define VRCONF_VDDCI_MASK        0x00FF0000
94 #define VRCONF_MVDD_MASK         0xFF000000
97 #define VR_MERGED_WITH_VDDC      0
120 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
122 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
123 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
124 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
125 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
126 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
127 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
128 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
129 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
130 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
132 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
133 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
134 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
135 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
136 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
137 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
168 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000