Lines Matching +full:event +full:- +full:deep
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
103 …epSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state…
113 …PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC S…
115 …tStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
116 …rVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
126 PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
156 …PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM state…
258 …((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIE…
287 (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_set()
293 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))); in phm_cap_unset()
299 (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1))))); in phm_cap_enabled()
302 #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
306 PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
307 PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
308 PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
395 /* variable-sized array, specify by num_of_pl. */