Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
228 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
229 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
238 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
441 uint8_t h_border;
442 uint8_t v_border;
444 uint8_t atom_mode_id;
445 uint8_t refreshrate;
484 uint8_t mem_module_id;
485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
486 uint8_t reserved1[2];
521 uint8_t mem_module_id;
522 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
523 uint8_t reserved1[2];
526 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
527 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
528 uint8_t board_i2c_feature_slave_addr;
529 uint8_t reserved3;
549 uint8_t mem_module_id;
550 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
551 uint8_t reserved1[2];
554 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
555 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
556 uint8_t board_i2c_feature_slave_addr;
557 uint8_t reserved3;
577 uint8_t mem_module_id;
578 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
579 uint8_t reserved1[2];
582 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
583 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
584 uint8_t board_i2c_feature_slave_addr;
585 uint8_t reserved3;
617 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
618 uint8_t pwr_on_de_to_vary_bl;
619 uint8_t pwr_down_vary_bloff_to_de;
620 uint8_t pwr_down_de_to_digoff;
621 uint8_t pwr_off_delay;
622 uint8_t pwr_on_vary_bl_to_blon;
623 uint8_t pwr_down_bloff_to_vary_bloff;
624 uint8_t panel_bpc;
625 uint8_t dpcd_edp_config_cap;
626 uint8_t dpcd_max_link_rate;
627 uint8_t dpcd_max_lane_count;
628 uint8_t dpcd_max_downspread;
629 uint8_t min_allowed_bl_level;
630 uint8_t max_allowed_bl_level;
631 uint8_t bootup_bl_level;
632 uint8_t dplvdsrxid;
659 uint8_t gpio_bitshift;
660 uint8_t gpio_mask_bitshift;
661 uint8_t gpio_id;
662 uint8_t reserved;
733 uint8_t record_type; //An emun to indicate the record type
734 uint8_t record_size; //The size of the whole record in byte
740 uint8_t i2c_id;
741 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
747 …uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info …
748 uint8_t plugin_pin_state;
783 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
784 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
790 uint8_t flag; // Future expnadibility
791 uint8_t number_of_pins; // Number of GPIO pins used to control the object
829 uint8_t hpd_pin_map[8];
835 uint8_t aux_ddc_map[8];
842 uint8_t maxtmdsclkrate_in2_5mhz;
843 uint8_t reserved;
849 uint8_t connector_type;
850 uint8_t position;
866 uint8_t bracketlen;
867 uint8_t bracketwidth;
868 uint8_t conn_num;
869 uint8_t reserved;
893 uint8_t priority_id;
894 uint8_t reserved;
901 uint8_t number_of_path;
902 uint8_t reserved;
925 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
926 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
927 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
928 uint8_t ss_reserved;
929 …uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable wh…
930 uint8_t reserved1[3];
933 uint8_t dceip_min_ver;
934 uint8_t dceip_max_ver;
935 uint8_t max_disp_pipe_num;
936 uint8_t max_vbios_active_disp_pipe_num;
937 uint8_t max_ppll_num;
938 uint8_t max_disp_phy_num;
939 uint8_t max_aux_pairs;
940 uint8_t remotedisplayconfig;
941 uint8_t reserved3[8];
957 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
958 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
959 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
960 uint8_t ss_reserved;
961 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
962 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
963 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
964 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
967 uint8_t dcnip_min_ver;
968 uint8_t dcnip_max_ver;
969 uint8_t max_disp_pipe_num;
970 uint8_t max_vbios_active_disp_pipe_num;
971 uint8_t max_ppll_num;
972 uint8_t max_disp_phy_num;
973 uint8_t max_aux_pairs;
974 uint8_t remotedisplayconfig;
975 uint8_t reserved3[8];
990 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
991 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
992 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
993 uint8_t ss_reserved;
994 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable wh…
995 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTa…
996 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable wh…
997 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable w…
1000 uint8_t dcnip_min_ver;
1001 uint8_t dcnip_max_ver;
1002 uint8_t max_disp_pipe_num;
1003 uint8_t max_vbios_active_disp_pipum;
1004 uint8_t max_ppll_num;
1005 uint8_t max_disp_phy_num;
1006 uint8_t max_aux_pairs;
1007 uint8_t remotedisplayconfig;
1053 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1054 uint8_t hpdlut_index; //An index into external HPD pin LUT
1056 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
1057 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
1075 …uint8_t guid[16]; // a GUID is a 16 byte long st…
1077 …uint8_t checksum; // a simple Checksum of the su…
1078 uint8_t stereopinid; // use for eDP panel
1079 uint8_t remotedisplayconfig;
1080 uint8_t edptolvdsrxid;
1081 …uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate …
1082 uint8_t reserved[3]; // for potential expansion
1093 uint8_t profile_id; // SENSOR_PROFILES
1104 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1105 uint8_t module_name[8];
1111 uint8_t flashlight_id; // 0: Rear, 1: Front
1112 uint8_t name[8];
1128 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1129 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1131 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1132 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1133 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1134 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1138 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1140 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1141 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1145 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1146 uint8_t version;
1161 uint8_t sym_clk;
1162 uint8_t dig_mode;
1163 uint8_t phy_sel;
1165 uint8_t common_seldeemph60__deemph_6db_4_val;
1166 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1167 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1168 uint8_t margin_deemph_lane0__deemph_sel_val;
1174 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1175 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1176 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1177 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1178 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1179 uint8_t reserved1;
1180 …uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1181 uint8_t reserved2;
1185 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1186 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1187 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1188 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1189 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1193 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1194 uint8_t version;
1201 uint8_t ucI2cRegIndex;
1202 uint8_t ucI2cRegVal;
1206 uint8_t HdmiSlvAddr;
1207 uint8_t HdmiRegNum;
1208 uint8_t Hdmi6GRegNum;
1231 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1232 uint8_t umachannelnumber; // number of memory channels
1233 …uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1234 uint8_t pwr_on_de_to_vary_bl;
1235 uint8_t pwr_down_vary_bloff_to_de;
1236 uint8_t pwr_down_de_to_digoff;
1237 uint8_t pwr_off_delay;
1238 uint8_t pwr_on_vary_bl_to_blon;
1239 uint8_t pwr_down_bloff_to_vary_bloff;
1240 uint8_t min_allowed_bl_level;
1241 uint8_t htc_hyst_limit;
1242 uint8_t htc_tmp_limit;
1243 uint8_t reserved1;
1244 uint8_t reserved2;
1280 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1281 uint8_t umachannelnumber; // number of memory channels
1282 …uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1283 uint8_t pwr_on_de_to_vary_bl;
1284 uint8_t pwr_down_vary_bloff_to_de;
1285 uint8_t pwr_down_de_to_digoff;
1286 uint8_t pwr_off_delay;
1287 uint8_t pwr_on_vary_bl_to_blon;
1288 uint8_t pwr_down_bloff_to_vary_bloff;
1289 uint8_t min_allowed_bl_level;
1290 uint8_t htc_hyst_limit;
1291 uint8_t htc_tmp_limit;
1292 uint8_t reserved1;
1293 uint8_t reserved2;
1390 uint8_t gfxip_min_ver;
1391 uint8_t gfxip_max_ver;
1392 uint8_t max_shader_engines;
1393 uint8_t max_tile_pipes;
1394 uint8_t max_cu_per_sh;
1395 uint8_t max_sh_per_se;
1396 uint8_t max_backends_per_se;
1397 uint8_t max_texture_channel_caches;
1410 uint8_t gfxip_min_ver;
1411 uint8_t gfxip_max_ver;
1412 uint8_t max_shader_engines;
1413 uint8_t max_tile_pipes;
1414 uint8_t max_cu_per_sh;
1415 uint8_t max_sh_per_se;
1416 uint8_t max_backends_per_se;
1417 uint8_t max_texture_channel_caches;
1426 uint8_t active_cu_per_sh;
1427 uint8_t active_rb_per_se;
1435 uint8_t gfxip_min_ver;
1436 uint8_t gfxip_max_ver;
1437 uint8_t max_shader_engines;
1438 uint8_t reserved;
1439 uint8_t max_cu_per_sh;
1440 uint8_t max_sh_per_se;
1441 uint8_t max_backends_per_se;
1442 uint8_t max_texture_channel_caches;
1451 uint8_t active_cu_per_sh;
1452 uint8_t active_rb_per_se;
1460 uint8_t gc_num_max_gs_thds;
1461 uint8_t gc_gs_table_depth;
1462 uint8_t gc_double_offchip_lds_buffer;
1463 uint8_t gc_max_scratch_slots_per_cu;
1476 uint8_t smuip_min_ver;
1477 uint8_t smuip_max_ver;
1478 uint8_t smu_rsd1;
1479 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1485 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1486 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1487 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1488 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1489 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1490 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1491 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1492 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1497 uint8_t smuip_min_ver;
1498 uint8_t smuip_max_ver;
1499 uint8_t smu_rsd1;
1500 uint8_t gpuclk_ss_mode;
1506 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1507 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1508 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1509 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1510 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1511 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1512 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1513 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1514 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1515 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1530 uint8_t smuip_min_ver;
1531 uint8_t smuip_max_ver;
1532 uint8_t waflclk_ss_mode;
1533 uint8_t gpuclk_ss_mode;
1539 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1540 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1541 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1542 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1543 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1544 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1545 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1546 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1547 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1548 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1576 uint8_t liquid1_i2c_address;
1577 uint8_t liquid2_i2c_address;
1578 uint8_t vr_i2c_address;
1579 uint8_t plx_i2c_address;
1581 uint8_t liquid_i2c_linescl;
1582 uint8_t liquid_i2c_linesda;
1583 uint8_t vr_i2c_linescl;
1584 uint8_t vr_i2c_linesda;
1586 uint8_t plx_i2c_linescl;
1587 uint8_t plx_i2c_linesda;
1588 uint8_t vrsensorpresent;
1589 uint8_t liquidsensorpresent;
1594 uint8_t vddgfxvrmapping;
1595 uint8_t vddsocvrmapping;
1596 uint8_t vddmem0vrmapping;
1597 uint8_t vddmem1vrmapping;
1599 uint8_t gfxulvphasesheddingmask;
1600 uint8_t soculvphasesheddingmask;
1601 uint8_t padding8_v[2];
1604 uint8_t gfxoffset;
1605 uint8_t padding_telemetrygfx;
1608 uint8_t socoffset;
1609 uint8_t padding_telemetrysoc;
1612 uint8_t mem0offset;
1613 uint8_t padding_telemetrymem0;
1616 uint8_t mem1offset;
1617 uint8_t padding_telemetrymem1;
1619 uint8_t acdcgpio;
1620 uint8_t acdcpolarity;
1621 uint8_t vr0hotgpio;
1622 uint8_t vr0hotpolarity;
1624 uint8_t vr1hotgpio;
1625 uint8_t vr1hotpolarity;
1626 uint8_t padding1;
1627 uint8_t padding2;
1629 uint8_t ledpin0;
1630 uint8_t ledpin1;
1631 uint8_t ledpin2;
1632 uint8_t padding8_4;
1634 uint8_t pllgfxclkspreadenabled;
1635 uint8_t pllgfxclkspreadpercent;
1638 uint8_t uclkspreadenabled;
1639 uint8_t uclkspreadpercent;
1642 uint8_t socclkspreadenabled;
1643 uint8_t socclkspreadpercent;
1646 uint8_t acggfxclkspreadenabled;
1647 uint8_t acggfxclkspreadpercent;
1650 uint8_t Vr2_I2C_address;
1651 uint8_t padding_vr2[3];
1664 uint8_t liquid1_i2c_address;
1665 uint8_t liquid2_i2c_address;
1666 uint8_t vr_i2c_address;
1667 uint8_t plx_i2c_address;
1669 uint8_t liquid_i2c_linescl;
1670 uint8_t liquid_i2c_linesda;
1671 uint8_t vr_i2c_linescl;
1672 uint8_t vr_i2c_linesda;
1674 uint8_t plx_i2c_linescl;
1675 uint8_t plx_i2c_linesda;
1676 uint8_t vrsensorpresent;
1677 uint8_t liquidsensorpresent;
1682 uint8_t vddgfxvrmapping;
1683 uint8_t vddsocvrmapping;
1684 uint8_t vddmem0vrmapping;
1685 uint8_t vddmem1vrmapping;
1687 uint8_t gfxulvphasesheddingmask;
1688 uint8_t soculvphasesheddingmask;
1689 uint8_t externalsensorpresent;
1690 uint8_t padding8_v;
1693 uint8_t gfxoffset;
1694 uint8_t padding_telemetrygfx;
1697 uint8_t socoffset;
1698 uint8_t padding_telemetrysoc;
1701 uint8_t mem0offset;
1702 uint8_t padding_telemetrymem0;
1705 uint8_t mem1offset;
1706 uint8_t padding_telemetrymem1;
1708 uint8_t acdcgpio;
1709 uint8_t acdcpolarity;
1710 uint8_t vr0hotgpio;
1711 uint8_t vr0hotpolarity;
1713 uint8_t vr1hotgpio;
1714 uint8_t vr1hotpolarity;
1715 uint8_t padding1;
1716 uint8_t padding2;
1718 uint8_t ledpin0;
1719 uint8_t ledpin1;
1720 uint8_t ledpin2;
1721 uint8_t padding8_4;
1723 uint8_t pllgfxclkspreadenabled;
1724 uint8_t pllgfxclkspreadpercent;
1727 uint8_t uclkspreadenabled;
1728 uint8_t uclkspreadpercent;
1731 uint8_t fclkspreadenabled;
1732 uint8_t fclkspreadpercent;
1735 uint8_t fllgfxclkspreadenabled;
1736 uint8_t fllgfxclkspreadpercent;
1760 uint8_t vddgfxvrmapping;
1761 uint8_t vddsocvrmapping;
1762 uint8_t vddmem0vrmapping;
1763 uint8_t vddmem1vrmapping;
1765 uint8_t gfxulvphasesheddingmask;
1766 uint8_t soculvphasesheddingmask;
1767 uint8_t externalsensorpresent;
1768 uint8_t padding8_v;
1771 uint8_t gfxoffset;
1772 uint8_t padding_telemetrygfx;
1775 uint8_t socoffset;
1776 uint8_t padding_telemetrysoc;
1779 uint8_t mem0offset;
1780 uint8_t padding_telemetrymem0;
1783 uint8_t mem1offset;
1784 uint8_t padding_telemetrymem1;
1787 uint8_t acdcgpio;
1788 uint8_t acdcpolarity;
1789 uint8_t vr0hotgpio;
1790 uint8_t vr0hotpolarity;
1792 uint8_t vr1hotgpio;
1793 uint8_t vr1hotpolarity;
1794 uint8_t padding1;
1795 uint8_t padding2;
1798 uint8_t ledpin0;
1799 uint8_t ledpin1;
1800 uint8_t ledpin2;
1801 uint8_t padding8_4;
1804 uint8_t pllgfxclkspreadenabled;
1805 uint8_t pllgfxclkspreadpercent;
1809 uint8_t uclkspreadenabled;
1810 uint8_t uclkspreadpercent;
1814 uint8_t fclkspreadenabled;
1815 uint8_t fclkspreadpercent;
1819 uint8_t fllgfxclkspreadenabled;
1820 uint8_t fllgfxclkspreadpercent;
1866 uint8_t Enabled;
1867 uint8_t Speed;
1868 uint8_t Padding[2];
1870 uint8_t ControllerPort;
1871 uint8_t ControllerName;
1872 uint8_t ThermalThrotter;
1873 uint8_t I2cProtocol;
1887 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1888 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1889 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1890 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1892 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1893 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1894 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1895 uint8_t Padding8_V;
1899 uint8_t GfxOffset; // in Amps
1900 uint8_t Padding_TelemetryGfx;
1902 uint8_t SocOffset; // in Amps
1903 uint8_t Padding_TelemetrySoc;
1906 uint8_t Mem0Offset; // in Amps
1907 uint8_t Padding_TelemetryMem0;
1910 uint8_t Mem1Offset; // in Amps
1911 uint8_t Padding_TelemetryMem1;
1914 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1915 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1916 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1917 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1919 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
1920 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
1921 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1922 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1925 uint8_t LedPin0; // GPIO number for LedPin[0]
1926 uint8_t LedPin1; // GPIO number for LedPin[1]
1927 uint8_t LedPin2; // GPIO number for LedPin[2]
1928 uint8_t padding8_4;
1931 uint8_t PllGfxclkSpreadEnabled; // on or off
1932 uint8_t PllGfxclkSpreadPercent; // Q4.4
1936 uint8_t DfllGfxclkSpreadEnabled; // on or off
1937 uint8_t DfllGfxclkSpreadPercent; // Q4.4
1941 uint8_t UclkSpreadEnabled; // on or off
1942 uint8_t UclkSpreadPercent; // Q4.4
1946 uint8_t SoclkSpreadEnabled; // on or off
1947 uint8_t SocclkSpreadPercent; // Q4.4
1970 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
1971 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
1972 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
1973 uint8_t boardvrmapping; // use vr_mapping* bitfields
1975 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1976 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
1977 uint8_t padding8_v[2];
1981 uint8_t gfxoffset; // in amps
1982 uint8_t padding_telemetrygfx;
1985 uint8_t socoffset; // in amps
1986 uint8_t padding_telemetrysoc;
1989 uint8_t memoffset; // in amps
1990 uint8_t padding_telemetrymem;
1993 uint8_t boardoffset; // in amps
1994 uint8_t padding_telemetryboardinput;
1997 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
1998 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
1999 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2000 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2003 uint8_t pllgfxclkspreadenabled; // on or off
2004 uint8_t pllgfxclkspreadpercent; // q4.4
2008 uint8_t uclkspreadenabled; // on or off
2009 uint8_t uclkspreadpercent; // q4.4
2013 uint8_t fclkspreadenabled; // on or off
2014 uint8_t fclkspreadpercent; // q4.4
2019 uint8_t fllgfxclkspreadenabled; // on or off
2020 uint8_t fllgfxclkspreadpercent; // q4.4
2029 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2030 uint8_t paddingmem[3];
2037 uint8_t xgmilinkspeed[4];
2038 uint8_t xgmilinkwidth[4];
2058 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2059 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2060 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2061 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2063 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2064 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2065 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2066 uint8_t Padding8_V;
2070 uint8_t GfxOffset; // in Amps
2071 uint8_t Padding_TelemetryGfx;
2073 uint8_t SocOffset; // in Amps
2074 uint8_t Padding_TelemetrySoc;
2077 uint8_t Mem0Offset; // in Amps
2078 uint8_t Padding_TelemetryMem0;
2081 uint8_t Mem1Offset; // in Amps
2082 uint8_t Padding_TelemetryMem1;
2085 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2086 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2087 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2088 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2090 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2091 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2092 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2093 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2096 uint8_t LedPin0; // GPIO number for LedPin[0]
2097 uint8_t LedPin1; // GPIO number for LedPin[1]
2098 uint8_t LedPin2; // GPIO number for LedPin[2]
2099 uint8_t padding8_4;
2102 uint8_t PllGfxclkSpreadEnabled; // on or off
2103 uint8_t PllGfxclkSpreadPercent; // Q4.4
2107 uint8_t DfllGfxclkSpreadEnabled; // on or off
2108 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2112 uint8_t UclkSpreadEnabled; // on or off
2113 uint8_t UclkSpreadPercent; // Q4.4
2117 uint8_t SoclkSpreadEnabled; // on or off
2118 uint8_t SocclkSpreadPercent; // Q4.4
2129 uint8_t GpioI2cScl; // Serial Clock
2130 uint8_t GpioI2cSda; // Serial Data
2134 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2135 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2139 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2141 uint8_t MvddUlvPhaseSheddingMask;
2142 uint8_t VddciUlvPhaseSheddingMask;
2143 uint8_t Padding8_Psi1;
2144 uint8_t Padding8_Psi2;
2151 uint8_t Enabled;
2152 uint8_t Speed;
2153 uint8_t SlaveAddress;
2154 uint8_t ControllerPort;
2155 uint8_t ControllerName;
2156 uint8_t ThermalThrotter;
2157 uint8_t I2cProtocol;
2158 uint8_t PaddingConfig;
2171 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2172 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2173 …uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when enter…
2174 uint8_t I2cSpare;
2177 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2178 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2179 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2180 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2182 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2183 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2184 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2185 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2189 uint8_t GfxOffset; // in Amps
2190 uint8_t Padding_TelemetryGfx;
2193 uint8_t SocOffset; // in Amps
2194 uint8_t Padding_TelemetrySoc;
2197 uint8_t Mem0Offset; // in Amps
2198 uint8_t Padding_TelemetryMem0;
2201 uint8_t Mem1Offset; // in Amps
2202 uint8_t Padding_TelemetryMem1;
2207 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2208 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2209 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2210 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2212 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2213 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2214 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2215 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2218 uint8_t LedPin0; // GPIO number for LedPin[0]
2219 uint8_t LedPin1; // GPIO number for LedPin[1]
2220 uint8_t LedPin2; // GPIO number for LedPin[2]
2221 uint8_t LedEnableMask;
2223 uint8_t LedPcie; // GPIO number for PCIE results
2224 uint8_t LedError; // GPIO number for Error Cases
2225 uint8_t LedSpare1[2];
2230 uint8_t PllGfxclkSpreadEnabled; // on or off
2231 uint8_t PllGfxclkSpreadPercent; // Q4.4
2235 uint8_t DfllGfxclkSpreadEnabled; // on or off
2236 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2240 uint8_t UclkSpreadEnabled; // on or off
2241 uint8_t UclkSpreadPercent; // Q4.4
2245 uint8_t FclkSpreadEnabled; // on or off
2246 uint8_t FclkSpreadPercent; // Q4.4
2252 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2253 uint8_t PaddingMem1[3];
2260 uint8_t XgmiLinkSpeed [4];
2261 uint8_t XgmiLinkWidth [4];
2301 uint8_t enable_gb_vdroop_table_cksoff;
2302 uint8_t enable_gb_vdroop_table_ckson;
2303 uint8_t enable_gb_fuse_table_cksoff;
2304 uint8_t enable_gb_fuse_table_ckson;
2306 uint8_t enable_apply_avfs_cksoff_voltage;
2307 uint8_t reserved;
2345 uint8_t enable_gb_vdroop_table_cksoff;
2346 uint8_t enable_gb_vdroop_table_ckson;
2347 uint8_t enable_gb_fuse_table_cksoff;
2348 uint8_t enable_gb_fuse_table_ckson;
2350 uint8_t enable_apply_avfs_cksoff_voltage;
2351 uint8_t reserved;
2370 uint8_t enable_acg_gb_vdroop_table;
2371 uint8_t enable_acg_gb_fuse_table;
2394 uint8_t uvdip_min_ver;
2395 uint8_t uvdip_max_ver;
2396 uint8_t vceip_min_ver;
2397 uint8_t vceip_max_ver;
2422 uint8_t umcip_min_ver;
2423 uint8_t umcip_max_ver;
2424 uint8_t vram_type; //enum of atom_dgpu_vram_type
2425 uint8_t umc_config;
2449 uint8_t umcip_min_ver;
2450 uint8_t umcip_max_ver;
2451 uint8_t vram_type; //enum of atom_dgpu_vram_type
2452 uint8_t umc_config;
2469 uint8_t umcip_min_ver;
2470 uint8_t umcip_max_ver;
2471 uint8_t vram_type; //enum of atom_dgpu_vram_type
2472 uint8_t umc_config;
2493 uint8_t ext_memory_id; // Current memory module ID
2494 uint8_t memory_type; // enum of atom_dgpu_vram_type
2495 uint8_t channel_num; // Number of mem. channels supported in this module
2496 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2497 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2498 uint8_t tunningset_id; // MC phy registers set per.
2499 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2500 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2501 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2502 uint8_t vram_rsd2; // reserved
2516 uint8_t vram_module_num; // indicate number of VRAM module
2517 uint8_t umcip_min_ver;
2518 uint8_t umcip_max_ver;
2519 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2571 uint8_t ext_memory_id; // Current memory module ID
2572 uint8_t memory_type; // enum of atom_dgpu_vram_type
2573 uint8_t channel_num; // Number of mem. channels supported in this module
2574 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2575 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2576 uint8_t tunningset_id; // MC phy registers set per
2577 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2578 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2579 uint8_t vram_flags; // bit0= bankgroup enable
2580 uint8_t vram_rsd2; // reserved
2598 uint8_t vram_module_num; // indicate number of VRAM module
2599 uint8_t umcip_min_ver;
2600 uint8_t umcip_max_ver;
2601 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2611 uint8_t ext_memory_id; // Current memory module ID
2612 uint8_t memory_type; // enum of atom_dgpu_vram_type
2613 uint8_t channel_num; // Number of mem. channels supported in this module
2614 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2615 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2616 uint8_t tunningset_id; // MC phy registers set per.
2618 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2619 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2620 uint8_t vram_flags; // bit0= bankgroup enable
2621 uint8_t vram_rsd2; // reserved
2634 uint8_t RL;
2635 uint8_t WL;
2636 uint8_t tRAS;
2637 uint8_t tRC;
2640 uint8_t tRFC;
2641 uint8_t tRFCpb;
2643 uint8_t tRREFD;
2644 uint8_t tRCDRD;
2645 uint8_t tRCDWR;
2646 uint8_t tRP;
2648 uint8_t tRRDS;
2649 uint8_t tRRDL;
2650 uint8_t tWR;
2651 uint8_t tWTRS;
2653 uint8_t tWTRL;
2654 uint8_t tFAW;
2655 uint8_t tCCDS;
2656 uint8_t tCCDL;
2658 uint8_t tCRCRL;
2659 uint8_t tCRCWL;
2660 uint8_t tCKE;
2661 uint8_t tCKSRE;
2663 uint8_t tCKSRX;
2664 uint8_t tRTPS;
2665 uint8_t tRTPL;
2666 uint8_t tMRD;
2668 uint8_t tMOD;
2669 uint8_t tXS;
2670 uint8_t tXHP;
2671 uint8_t tXSMRS;
2675 uint8_t tPD;
2676 uint8_t tXP;
2677 uint8_t tCPDED;
2678 uint8_t tACTPDE;
2680 uint8_t tPREPDE;
2681 uint8_t tREFPDE;
2682 uint8_t tMRSPDEN;
2683 uint8_t tRDSRE;
2685 uint8_t tWRSRE;
2686 uint8_t tPPD;
2687 uint8_t tCCDMW;
2688 uint8_t tWTRTR;
2690 uint8_t tLTLTR;
2691 uint8_t tREFTR;
2692 uint8_t VNDR;
2693 uint8_t reserved[9];
2708 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
2722 uint8_t vram_module_num; // indicate number of VRAM module
2723 uint8_t umcip_min_ver;
2724 uint8_t umcip_max_ver;
2725 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2741 uint8_t voltage_type; //enum atom_voltage_type
2742 uint8_t voltage_mode; //enum atom_voltage_object_mode
2760 uint8_t regulator_id; //Indicate Voltage Regulator Id
2761 uint8_t i2c_id;
2762 uint8_t i2c_slave_addr;
2763 uint8_t i2c_control_offset;
2764 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
2765 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
2766 uint8_t reserved[2];
2787 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
2788 …uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value L…
2789 uint8_t phase_delay_us; // phase delay in unit of micro second
2790 uint8_t reserved;
2798 …uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and…
2799 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
2800 uint8_t psi0_enable; //
2801 uint8_t maxvstep;
2802 uint8_t telemetry_offset;
2803 uint8_t telemetry_gain;
2810 uint8_t merged_powerrail_type; //enum atom_voltage_type
2811 uint8_t reserved[3];
2956 uint8_t voltagetype; /* enum atom_voltage_type */
2957 …uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_…
3005 uint8_t pll_ss_enable;
3006 uint8_t reserved;
3021 uint8_t reserved;
3022 uint8_t bitslen;
3040 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3041 …uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLO…
3042 uint8_t command; // enum of atom_get_smu_clock_info_command
3043 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
3180 uint8_t ucode_func_id;
3181 uint8_t ucode_reserved[3];
3196 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
3197 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
3199 uint8_t encoder_mode; // Encoder mode:
3200 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
3201 uint8_t crtc_id; // enum of atom_crtc_def
3202 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
3203 uint8_t reserved1[2];
3242 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
3243 …uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK …
3244 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
3245 …uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use on…
3289 uint8_t crtc_id; // enum atom_crtc_def
3290 uint8_t blanking; // enum atom_blank_crtc_command
3306 uint8_t crtc_id; // enum atom_crtc_def
3307 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3308 uint8_t padding[2];
3317 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
3318 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
3319 uint8_t padding[2];
3342 uint8_t h_border;
3343 uint8_t v_border;
3344 uint8_t crtc_id; // enum atom_crtc_def
3345 uint8_t encoder_mode; // atom_encode_mode_def
3346 uint8_t padding[2];
3355 uint8_t i2cspeed_khz;
3357 uint8_t regindex;
3358 uint8_t status; /* enum atom_process_i2c_flag */
3361 uint8_t flag; /* enum atom_process_i2c_status */
3362 uint8_t trans_bytes;
3363 uint8_t slave_addr;
3364 uint8_t i2c_id;
3392 uint8_t channelid;
3394 uint8_t reply_status;
3395 uint8_t aux_delay;
3397 uint8_t dataout_len;
3398 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
3408 uint8_t crtc_id; // enum atom_crtc_def
3409 uint8_t encoder_id; // enum atom_dig_def
3410 uint8_t encode_mode; // enum atom_encode_mode_def
3411 uint8_t dst_bpc; // enum atom_panel_bit_per_color
3461 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3462 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
3463 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3464 uint8_t lanenum; // Lane number
3466 uint8_t bitpercolor;
3467 …uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz…
3468 uint8_t reserved[2];
3473 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3474 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
3475 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
3476 uint8_t lanenum; // Lane number
3477 uint8_t symclk_10khz; // Symbol Clock in 10Khz
3478 uint8_t hpd_sel;
3479 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3480 uint8_t reserved[2];
3485 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3486 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
3487 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
3488 uint8_t reserved1;
3494 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
3495 uint8_t action; // = rest of generic encoder command which does not carry any parameters
3496 uint8_t reserved1[2];
3515 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
3516 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3518 uint8_t digmode; // enum atom_encode_mode_def
3519 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
3521 uint8_t lanenum; // Lane number 1, 2, 4, 8
3523 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3524 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3525 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3526 uint8_t reserved;
3604 …uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENAB…
3605 uint8_t action; //
3606 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3607 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3608 …uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPU…
3609 uint8_t hpd_id;
3657 uint8_t revision;
3658 uint8_t checksum;
3659 uint8_t oemId[6];
3660 uint8_t oemTableId[8]; //UINT64 OemTableId;
3668 uint8_t tableUUID[16]; //0x24
3689 uint8_t vbioscontent[1];
3694 uint8_t lib1content[1];