Lines Matching +full:ati +full:- +full:target
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
518 ULONG ulClock:24; //Input= target clock, output = actual clock
520 ULONG ulClock:24; //Input= target clock, output = actual clock
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
598 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
606 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
611 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
958 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1011 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
1064 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1566 …UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP…
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1901 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1916 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1930 // =1: other external clock source, which is pre-defined
1950 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1953 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1978 // =1: other external clock source, which is pre-defined
2017 …ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 1…
2046 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: D…
2047 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO:…
2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO:…
2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO:…
2054 …ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequ…
2076 …ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, retur…
2097 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE:…
2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATI…
2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATI…
2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATI…
2132 USHORT usPixelClock; // target pixel clock
2156 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
2157 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
2203 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2312 // Bit[1]: 1-Ext. 0-Int.
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2337 // Bit[1]: 1-Ext. 0-Int.
2532 // bit1=0: non-coherent mode
2816 …_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2842 ULONG ulSignature; // HW info table signature string "$ATI"
2859 …UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on produ…
3009 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3046 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3084 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3123 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
3234 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3310 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3315 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3316 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3317 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
3320 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3321 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
3339 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
3341 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3342 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
3345 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
3346 …[7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station…
3349 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
3351 [15:8] - Lane configuration attribute;
3352 [23:16]- Connector type, possible value:
3358 [31:24]- Reserved
3366 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
3380 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3409 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3630 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3631 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3632 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3633 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3634 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3635 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3636 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3637 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3638 // Bit 8 = 0 - no CV support= 1- CV is supported
3639 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3640 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3641 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3649 // [7:0] - I2C LINE Associate ID
3650 // = 0 - no I2C
3651 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3653 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3655 // = 3-7 Reserved for future I2C engines
3656 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3761 // usModeMiscInfo-
3773 //usRefreshRate-
3958 // 0 0 0 - Color bit depth is undefined
3959 // 0 0 1 - 6 Bits per Primary Color
3960 // 0 1 0 - 8 Bits per Primary Color
3961 // 0 1 1 - 10 Bits per Primary Color
3962 // 1 0 0 - 12 Bits per Primary Color
3963 // 1 0 1 - 14 Bits per Primary Color
3964 // 1 1 0 - 16 Bits per Primary Color
3965 // 1 1 1 - Reserved
4014 // Bit7-3: Reserved
4052 // 0 0 0 - Color bit depth is undefined
4053 // 0 0 1 - 6 Bits per Primary Color
4054 // 0 1 0 - 8 Bits per Primary Color
4055 // 0 1 1 - 10 Bits per Primary Color
4056 // 1 0 0 - 12 Bits per Primary Color
4057 // 1 0 1 - 14 Bits per Primary Color
4058 // 1 1 0 - 16 Bits per Primary Color
4059 // 1 1 1 - Reserved
4076 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4077 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
4222 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4236 … (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4294 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
4318 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4322 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4324 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4368 //ucGPIO_ID pre-define id for multiple usage
4380 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; u…
4382 // Thermal interrupt output->system thermal chip GPIO pin
4459 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4476 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recov…
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4844 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4850 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4864 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
4874 …USHORT usReserved:12; // Bit4-15 may be defined for other capability in fu…
5019 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
5117 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
5118 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
5119 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
5120 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
5122 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5123 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5124 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5272 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5276 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5282 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5286 … // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5791 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5816 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5817 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5819 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5822 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5825 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5836 Bit[1]=0: DDR-DLL shut-down feature disabled.
5837 1: DDR-DLL shut-down feature enabled.
5838 Bit[2]=0: DDR-PLL Power down feature disabled.
5839 1: DDR-PLL Power down feature enabled.
5858 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5859 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6011 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6045 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6046 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6048 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6051 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6054 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6065 Bit[1]=0: DDR-DLL shut-down feature disabled.
6066 1: DDR-DLL shut-down feature enabled.
6067 Bit[2]=0: DDR-PLL Power down feature disabled.
6068 1: DDR-PLL Power down feature enabled.
6089 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
6090 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6111 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6114 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6118 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6122 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6213 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
6247 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
6248 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
6250 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6253 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
6256 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
6266 Bit[1]=0: DDR-DLL shut-down feature disabled.
6267 1: DDR-DLL shut-down feature enabled.
6268 Bit[2]=0: DDR-PLL Power down feature disabled.
6269 1: DDR-PLL Power down feature enabled.
6290 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
6318 … default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6322 …efault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6326 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6330 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6349 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
6350 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6351 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6352 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
7128 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
7130 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
7131 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
7133 …ieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeo…
7135 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
7136 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
7559 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7597 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7598 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7615 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7624 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7625 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7633 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
7669 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
7705 … ulClkRange; // memory clock in 10kHz unit, when target memory clock is be…
7742 …ULONG ulDllDisClock; // memory DLL will be disable when target memory cl…
7751 … ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for…
7776 … ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7797 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7799 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7802 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7807 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7839 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7841 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7844 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7849 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7858 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7871 … // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7873 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7876 …; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlengt…
7881 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7890 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7906 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7909 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7911 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7920 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7950 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
8211 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8212 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8231 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
8555 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8556 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8557 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8564 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8565 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8566 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8576 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
8577 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
8578 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
8583 …fset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Lin…
8584 …t of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8585 … of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8586 …set of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Lin…
8587 …f PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Lin…
8588 …TING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Lin…
8755 // [7:4] - connector type
8756 // = 1 - VGA connector
8757 // = 2 - DVI-I
8758 // = 3 - DVI-D
8759 // = 4 - DVI-A
8760 // = 5 - SVIDEO
8761 // = 6 - COMPOSITE
8762 // = 7 - LVDS
8763 // = 8 - DIGITAL LINK
8764 // = 9 - SCART
8765 // = 0xA - HDMI_type A
8766 // = 0xB - HDMI_type B
8767 // = 0xE - Special case1 (DVI+DIN)
8769 // [3:0] - DAC Associated
8770 // = 0 - no DAC
8771 // = 1 - DACA
8772 // = 2 - DACB
8773 // = 3 - External DAC
8838 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8948 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
8958 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
8968 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …
9205 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )