439 		return sysfs_show_str_val(buffer, offs, dev->node_props.name);  in node_show()
447 			      dev->node_props.cpu_cores_count);  in node_show()
449 			      dev->gpu ? dev->node_props.simd_count : 0);  in node_show()
451 			      dev->node_props.mem_banks_count);  in node_show()
453 			      dev->node_props.caches_count);  in node_show()
455 			      dev->node_props.io_links_count);  in node_show()
457 			      dev->node_props.cpu_core_id_base);  in node_show()
459 			      dev->node_props.simd_id_base);  in node_show()
461 			      dev->node_props.max_waves_per_simd);  in node_show()
463 			      dev->node_props.lds_size_in_kb);  in node_show()
465 			      dev->node_props.gds_size_in_kb);  in node_show()
467 			      dev->node_props.num_gws);  in node_show()
469 			      dev->node_props.wave_front_size);  in node_show()
471 			      dev->node_props.array_count);  in node_show()
473 			      dev->node_props.simd_arrays_per_engine);  in node_show()
475 			      dev->node_props.cu_per_simd_array);  in node_show()
477 			      dev->node_props.simd_per_cu);  in node_show()
479 			      dev->node_props.max_slots_scratch_cu);  in node_show()
481 			      dev->node_props.vendor_id);  in node_show()
483 			      dev->node_props.device_id);  in node_show()
485 			      dev->node_props.location_id);  in node_show()
487 			      dev->node_props.domain);  in node_show()
489 			      dev->node_props.drm_render_minor);  in node_show()
491 			      dev->node_props.hive_id);  in node_show()
493 			      dev->node_props.num_sdma_engines);  in node_show()
495 			      dev->node_props.num_sdma_xgmi_engines);  in node_show()
497 			      dev->node_props.num_sdma_queues_per_engine);  in node_show()
499 			      dev->node_props.num_cp_queues);  in node_show()
501 			      dev->node_props.unique_id);  in node_show()
508 			dev->node_props.capability |=  in node_show()
511 			dev->node_props.capability |=  in node_show()
518 			dev->node_props.capability |=  in node_show()
522 			dev->node_props.max_engine_clk_fcompute);  in node_show()
529 				      dev->node_props.capability);  in node_show()
883 		if (dev->node_props.cpu_cores_count &&  in kfd_debug_print_topology()
884 				dev->node_props.simd_count) {  in kfd_debug_print_topology()
886 				dev->node_props.device_id,  in kfd_debug_print_topology()
887 				dev->node_props.vendor_id);  in kfd_debug_print_topology()
888 		} else if (dev->node_props.cpu_cores_count)  in kfd_debug_print_topology()
890 		else if (dev->node_props.simd_count)  in kfd_debug_print_topology()
892 				dev->node_props.device_id,  in kfd_debug_print_topology()
893 				dev->node_props.vendor_id);  in kfd_debug_print_topology()
974 		if (dev->node_props.cpu_cores_count &&  in kfd_is_acpi_crat_invalid()
975 			dev->node_props.simd_count)  in kfd_is_acpi_crat_invalid()
1143 		    dev->node_props.cpu_cores_count)  in kfd_assign_gpu()
1146 		if (!dev->gpu && (dev->node_props.simd_count > 0)) {  in kfd_assign_gpu()
1312 	strncpy(dev->node_props.name, gpu->device_info->asic_name,  in kfd_topology_add_device()
1315 	dev->node_props.simd_arrays_per_engine =  in kfd_topology_add_device()
1318 	dev->node_props.vendor_id = gpu->pdev->vendor;  in kfd_topology_add_device()
1319 	dev->node_props.device_id = gpu->pdev->device;  in kfd_topology_add_device()
1320 	dev->node_props.capability |=  in kfd_topology_add_device()
1324 	dev->node_props.location_id = pci_dev_id(gpu->pdev);  in kfd_topology_add_device()
1325 	dev->node_props.domain = pci_domain_nr(gpu->pdev->bus);  in kfd_topology_add_device()
1326 	dev->node_props.max_engine_clk_fcompute =  in kfd_topology_add_device()
1328 	dev->node_props.max_engine_clk_ccompute =  in kfd_topology_add_device()
1330 	dev->node_props.drm_render_minor =  in kfd_topology_add_device()
1333 	dev->node_props.hive_id = gpu->hive_id;  in kfd_topology_add_device()
1334 	dev->node_props.num_sdma_engines = gpu->device_info->num_sdma_engines;  in kfd_topology_add_device()
1335 	dev->node_props.num_sdma_xgmi_engines =  in kfd_topology_add_device()
1337 	dev->node_props.num_sdma_queues_per_engine =  in kfd_topology_add_device()
1339 	dev->node_props.num_gws = (dev->gpu->gws &&  in kfd_topology_add_device()
1342 	dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);  in kfd_topology_add_device()
1343 	dev->node_props.unique_id = gpu->unique_id;  in kfd_topology_add_device()
1352 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<  in kfd_topology_add_device()
1363 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<  in kfd_topology_add_device()
1378 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<  in kfd_topology_add_device()
1392 		dev->node_props.capability |= HSA_CAP_ATS_PRESENT;  in kfd_topology_add_device()
1394 		dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;  in kfd_topology_add_device()
1402 		dev->node_props.simd_count =  in kfd_topology_add_device()
1404 		dev->node_props.max_waves_per_simd = 10;  in kfd_topology_add_device()
1409 	dev->node_props.capability |=  in kfd_topology_add_device()
1412 	dev->node_props.capability |= ((adev->ras_features & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?  in kfd_topology_add_device()
1416 		dev->node_props.capability |= (adev->ras_features != 0) ?  in kfd_topology_add_device()
1531 		if (dev->node_props.cpu_cores_count &&  in kfd_double_confirm_iommu_support()
1532 		    dev->node_props.simd_count &&  in kfd_double_confirm_iommu_support()