Lines Matching refs:pr_debug
195 pr_debug("DIQ Created with queue id: %d\n", qid); in dbgdev_register_diq()
262 pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask); in dbgdev_address_watch_set_registers()
263 pr_debug("\t\t%20s %08x\n", "set reg add high :", in dbgdev_address_watch_set_registers()
265 pr_debug("\t\t%20s %08x\n", "set reg add low :", in dbgdev_address_watch_set_registers()
305 pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_address_watch_nodiq()
306 pr_debug("\t\t%20s %08x\n", "register index :", i); in dbgdev_address_watch_nodiq()
307 pr_debug("\t\t%20s %08x\n", "vmid is :", pdd->qpd.vmid); in dbgdev_address_watch_nodiq()
308 pr_debug("\t\t%20s %08x\n", "Address Low is :", in dbgdev_address_watch_nodiq()
310 pr_debug("\t\t%20s %08x\n", "Address high is :", in dbgdev_address_watch_nodiq()
312 pr_debug("\t\t%20s %08x\n", "Address high is :", in dbgdev_address_watch_nodiq()
314 pr_debug("\t\t%20s %08x\n", "Control Mask is :", in dbgdev_address_watch_nodiq()
316 pr_debug("\t\t%20s %08x\n", "Control Mode is :", in dbgdev_address_watch_nodiq()
318 pr_debug("\t\t%20s %08x\n", "Control Vmid is :", in dbgdev_address_watch_nodiq()
320 pr_debug("\t\t%20s %08x\n", "Control atc is :", in dbgdev_address_watch_nodiq()
322 pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_address_watch_nodiq()
400 pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_address_watch_diq()
401 pr_debug("\t\t%20s %08x\n", "register index :", i); in dbgdev_address_watch_diq()
402 pr_debug("\t\t%20s %08x\n", "vmid is :", vmid); in dbgdev_address_watch_diq()
403 pr_debug("\t\t%20s %p\n", "Add ptr is :", in dbgdev_address_watch_diq()
405 pr_debug("\t\t%20s %08llx\n", "Add is :", in dbgdev_address_watch_diq()
407 pr_debug("\t\t%20s %08x\n", "Address Low is :", in dbgdev_address_watch_diq()
409 pr_debug("\t\t%20s %08x\n", "Address high is :", in dbgdev_address_watch_diq()
411 pr_debug("\t\t%20s %08x\n", "Control Mask is :", in dbgdev_address_watch_diq()
413 pr_debug("\t\t%20s %08x\n", "Control Mode is :", in dbgdev_address_watch_diq()
415 pr_debug("\t\t%20s %08x\n", "Control Vmid is :", in dbgdev_address_watch_diq()
417 pr_debug("\t\t%20s %08x\n", "Control atc is :", in dbgdev_address_watch_diq()
419 pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_address_watch_diq()
607 pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_wave_control_diq()
609 pr_debug("\t\t mode is: %u\n", wac_info->mode); in dbgdev_wave_control_diq()
610 pr_debug("\t\t operand is: %u\n", wac_info->operand); in dbgdev_wave_control_diq()
611 pr_debug("\t\t trap id is: %u\n", wac_info->trapId); in dbgdev_wave_control_diq()
612 pr_debug("\t\t msg value is: %u\n", in dbgdev_wave_control_diq()
614 pr_debug("\t\t vmid is: N/A\n"); in dbgdev_wave_control_diq()
616 pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid); in dbgdev_wave_control_diq()
617 pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd); in dbgdev_wave_control_diq()
618 pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id); in dbgdev_wave_control_diq()
619 pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id); in dbgdev_wave_control_diq()
620 pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode); in dbgdev_wave_control_diq()
621 pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id); in dbgdev_wave_control_diq()
622 pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id); in dbgdev_wave_control_diq()
624 pr_debug("\t\t ibw is : %u\n", in dbgdev_wave_control_diq()
626 pr_debug("\t\t ii is : %u\n", in dbgdev_wave_control_diq()
628 pr_debug("\t\t sebw is : %u\n", in dbgdev_wave_control_diq()
630 pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index); in dbgdev_wave_control_diq()
631 pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index); in dbgdev_wave_control_diq()
632 pr_debug("\t\t sbw is : %u\n", in dbgdev_wave_control_diq()
635 pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_wave_control_diq()
725 pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_wave_control_nodiq()
727 pr_debug("\t\t mode is: %u\n", wac_info->mode); in dbgdev_wave_control_nodiq()
728 pr_debug("\t\t operand is: %u\n", wac_info->operand); in dbgdev_wave_control_nodiq()
729 pr_debug("\t\t trap id is: %u\n", wac_info->trapId); in dbgdev_wave_control_nodiq()
730 pr_debug("\t\t msg value is: %u\n", in dbgdev_wave_control_nodiq()
732 pr_debug("\t\t vmid is: %u\n", pdd->qpd.vmid); in dbgdev_wave_control_nodiq()
734 pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid); in dbgdev_wave_control_nodiq()
735 pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd); in dbgdev_wave_control_nodiq()
736 pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id); in dbgdev_wave_control_nodiq()
737 pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id); in dbgdev_wave_control_nodiq()
738 pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode); in dbgdev_wave_control_nodiq()
739 pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id); in dbgdev_wave_control_nodiq()
740 pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id); in dbgdev_wave_control_nodiq()
742 pr_debug("\t\t ibw is : %u\n", in dbgdev_wave_control_nodiq()
744 pr_debug("\t\t ii is : %u\n", in dbgdev_wave_control_nodiq()
746 pr_debug("\t\t sebw is : %u\n", in dbgdev_wave_control_nodiq()
748 pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index); in dbgdev_wave_control_nodiq()
749 pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index); in dbgdev_wave_control_nodiq()
750 pr_debug("\t\t sbw is : %u\n", in dbgdev_wave_control_nodiq()
753 pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *"); in dbgdev_wave_control_nodiq()
778 pr_debug("Killing all process wavefronts\n"); in dbgdev_wave_reset_wavefronts()
790 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n", in dbgdev_wave_reset_wavefronts()