Lines Matching refs:uint8_t
54 uint8_t revision;
55 uint8_t checksum;
56 uint8_t oem_id[CRAT_OEMID_LENGTH];
57 uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
63 uint8_t reserved[CRAT_RESERVED_LENGTH];
97 uint8_t type;
98 uint8_t length;
109 uint8_t wave_front_size;
110 uint8_t num_banks;
112 uint8_t array_count;
113 uint8_t num_cu_per_array;
114 uint8_t num_simd_per_cu;
115 uint8_t max_slots_scatch_cu;
116 uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
130 uint8_t type;
131 uint8_t length;
140 uint8_t visibility_type; /* for virtual (dGPU) CRAT */
141 uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
157 uint8_t type;
158 uint8_t length;
162 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
164 uint8_t cache_level;
165 uint8_t lines_per_tag;
167 uint8_t associativity;
168 uint8_t cache_properties;
170 uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];
186 uint8_t type;
187 uint8_t length;
191 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
193 uint8_t data_tlb_associativity_2mb;
194 uint8_t data_tlb_size_2mb;
195 uint8_t instruction_tlb_associativity_2mb;
196 uint8_t instruction_tlb_size_2mb;
197 uint8_t data_tlb_associativity_4k;
198 uint8_t data_tlb_size_4k;
199 uint8_t instruction_tlb_associativity_4k;
200 uint8_t instruction_tlb_size_4k;
201 uint8_t data_tlb_associativity_1gb;
202 uint8_t data_tlb_size_1gb;
203 uint8_t instruction_tlb_associativity_1gb;
204 uint8_t instruction_tlb_size_1gb;
205 uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];
217 uint8_t type;
218 uint8_t length;
222 uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
224 uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
263 uint8_t type;
264 uint8_t length;
269 uint8_t io_interface_type;
270 uint8_t version_major;
277 uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
278 uint8_t num_hops_xgmi;
288 uint8_t type;
289 uint8_t length;
303 uint8_t revision;
304 uint8_t checksum;
305 uint8_t oem_id[CDIT_OEMID_LENGTH];
306 uint8_t oem_table_id[CDIT_OEMTABLEID_LENGTH];
312 uint8_t entry[1];