Lines Matching +full:0 +full:x5400
26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
30 #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */
33 #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c)
34 #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c)
35 #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c)
36 #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c)
37 #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c)
38 #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c)
39 #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c)
42 #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00)
43 #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00)
44 #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00)
45 #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00)
46 #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00)
47 #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00)
48 #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00)
49 #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00)
50 #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00)
53 #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8)
54 #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8)
55 #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8)
56 #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8)
57 #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8)
58 #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8)
59 #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8)
60 #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8)
63 #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898)
64 #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
65 #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
66 #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
67 #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
68 #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
70 #define PIPEID(x) ((x) << 0)
75 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
76 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
77 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
78 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
79 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
80 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
81 #define MC_SEQ_MISC0__MT__HBM 0x60000000
82 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
87 #define PACKET_TYPE0 0
93 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
94 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
95 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
97 ((reg) & 0xFFFF) | \
98 ((n) & 0x3FFF) << 16)
99 #define CP_PACKET2 0x80000000
100 #define PACKET2_PAD_SHIFT 0
101 #define PACKET2_PAD_MASK (0x3fffffff << 0)
106 (((op) & 0xFF) << 8) | \
107 ((n) & 0x3FFF) << 16)
112 #define PACKET3_NOP 0x10
113 #define PACKET3_SET_BASE 0x11
114 #define PACKET3_BASE_INDEX(x) ((x) << 0)
116 #define PACKET3_CLEAR_STATE 0x12
117 #define PACKET3_INDEX_BUFFER_SIZE 0x13
118 #define PACKET3_DISPATCH_DIRECT 0x15
119 #define PACKET3_DISPATCH_INDIRECT 0x16
120 #define PACKET3_ATOMIC_GDS 0x1D
121 #define PACKET3_ATOMIC_MEM 0x1E
122 #define PACKET3_OCCLUSION_QUERY 0x1F
123 #define PACKET3_SET_PREDICATION 0x20
124 #define PACKET3_REG_RMW 0x21
125 #define PACKET3_COND_EXEC 0x22
126 #define PACKET3_PRED_EXEC 0x23
127 #define PACKET3_DRAW_INDIRECT 0x24
128 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
129 #define PACKET3_INDEX_BASE 0x26
130 #define PACKET3_DRAW_INDEX_2 0x27
131 #define PACKET3_CONTEXT_CONTROL 0x28
132 #define PACKET3_INDEX_TYPE 0x2A
133 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
134 #define PACKET3_DRAW_INDEX_AUTO 0x2D
135 #define PACKET3_NUM_INSTANCES 0x2F
136 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
137 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
138 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
139 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
140 #define PACKET3_DRAW_PREAMBLE 0x36
141 #define PACKET3_WRITE_DATA 0x37
143 /* 0 - register
153 /* 0 - LRU
157 /* 0 - me
161 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
162 #define PACKET3_MEM_SEMAPHORE 0x39
163 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
164 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
165 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
166 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
167 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
168 #define PACKET3_WAIT_REG_MEM 0x3C
169 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
170 /* 0 - always
179 /* 0 - reg
183 /* 0 - wait_reg_mem
187 /* 0 - me
190 #define PACKET3_INDIRECT_BUFFER 0x3F
194 /* 0 - LRU
199 #define PACKET3_COPY_DATA 0x40
200 #define PACKET3_PFP_SYNC_ME 0x42
201 #define PACKET3_SURFACE_SYNC 0x43
202 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
225 #define PACKET3_COND_WRITE 0x45
226 #define PACKET3_EVENT_WRITE 0x46
227 #define EVENT_TYPE(x) ((x) << 0)
229 /* 0 - any non-TS event
237 #define PACKET3_EVENT_WRITE_EOP 0x47
245 /* 0 - LRU
250 /* 0 - discard
257 /* 0 - none
258 * 1 - interrupt only (DATA_SEL = 0)
262 /* 0 - MC
265 #define PACKET3_EVENT_WRITE_EOS 0x48
266 #define PACKET3_RELEASE_MEM 0x49
267 #define PACKET3_PREAMBLE_CNTL 0x4A
270 #define PACKET3_DMA_DATA 0x50
273 * 3. SRC_ADDR_LO or DATA [31:0]
274 * 4. SRC_ADDR_HI [31:0]
275 * 5. DST_ADDR_LO [31:0]
276 * 6. DST_ADDR_HI [7:0]
277 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
280 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
281 /* 0 - ME
285 /* 0 - LRU
291 /* 0 - DST_ADDR using DAS
296 /* 0 - LRU
302 /* 0 - SRC_ADDR using SAS
311 /* 0 - none
317 /* 0 - none
323 /* 0 - memory
327 /* 0 - memory
333 #define PACKET3_ACQUIRE_MEM 0x58
334 #define PACKET3_REWIND 0x59
335 #define PACKET3_LOAD_UCONFIG_REG 0x5E
336 #define PACKET3_LOAD_SH_REG 0x5F
337 #define PACKET3_LOAD_CONFIG_REG 0x60
338 #define PACKET3_LOAD_CONTEXT_REG 0x61
339 #define PACKET3_SET_CONFIG_REG 0x68
340 #define PACKET3_SET_CONFIG_REG_START 0x00002000
341 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
342 #define PACKET3_SET_CONTEXT_REG 0x69
343 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
344 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
345 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
346 #define PACKET3_SET_SH_REG 0x76
347 #define PACKET3_SET_SH_REG_START 0x00002c00
348 #define PACKET3_SET_SH_REG_END 0x00003000
349 #define PACKET3_SET_SH_REG_OFFSET 0x77
350 #define PACKET3_SET_QUEUE_REG 0x78
351 #define PACKET3_SET_UCONFIG_REG 0x79
352 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
353 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
354 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
355 #define PACKET3_SCRATCH_RAM_READ 0x7E
356 #define PACKET3_LOAD_CONST_RAM 0x80
357 #define PACKET3_WRITE_CONST_RAM 0x81
358 #define PACKET3_DUMP_CONST_RAM 0x83
359 #define PACKET3_INCREMENT_CE_COUNTER 0x84
360 #define PACKET3_INCREMENT_DE_COUNTER 0x85
361 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
362 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
363 #define PACKET3_SWITCH_BUFFER 0x8B
364 #define PACKET3_FRAME_CONTROL 0x90
367 * x=0: tmz_begin
370 #define PACKET3_SET_RESOURCES 0xA0
373 * 3. QUEUE_MASK_LO [31:0]
374 * 4. QUEUE_MASK_HI [31:0]
375 * 5. GWS_MASK_LO [31:0]
376 * 6. GWS_MASK_HI [31:0]
377 * 7. OAC_MASK [15:0]
378 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
380 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
383 #define PACKET3_MAP_QUEUES 0xA2
387 * 4. MQD_ADDR_LO [31:0]
388 * 5. MQD_ADDR_HI [31:0]
389 * 6. WPTR_ADDR_LO [31:0]
390 * 7. WPTR_ADDR_HI [31:0]
405 #define PACKET3_UNMAP_QUEUES 0xA3
414 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
415 /* 0 - PREEMPT_QUEUES
424 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
430 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
435 #define PACKET3_QUERY_STATUS 0xA4
439 * 4. ADDR_LO [31:0]
440 * 5. ADDR_HI [31:0]
441 * 6. DATA_LO [31:0]
442 * 7. DATA_HI [31:0]
445 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
449 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
455 #define VCE_CMD_NO_OP 0x00000000
456 #define VCE_CMD_END 0x00000001
457 #define VCE_CMD_IB 0x00000002
458 #define VCE_CMD_FENCE 0x00000003
459 #define VCE_CMD_TRAP 0x00000004
460 #define VCE_CMD_IB_AUTO 0x00000005
461 #define VCE_CMD_SEMAPHORE 0x00000006
463 #define VCE_CMD_IB_VM 0x00000102
464 #define VCE_CMD_WAIT_GE 0x00000106
465 #define VCE_CMD_UPDATE_PTB 0x00000107
466 #define VCE_CMD_FLUSH_TLB 0x00000108
469 #define HEVC_ENC_CMD_NO_OP 0x00000000
470 #define HEVC_ENC_CMD_END 0x00000001
471 #define HEVC_ENC_CMD_FENCE 0x00000003
472 #define HEVC_ENC_CMD_TRAP 0x00000004
473 #define HEVC_ENC_CMD_IB_VM 0x00000102
474 #define HEVC_ENC_CMD_WAIT_GE 0x00000106
475 #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107
476 #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108
479 #define RB_MAP_PKR0(x) ((x) << 0)
480 #define RB_MAP_PKR0_MASK (0x3 << 0)
482 #define RB_MAP_PKR1_MASK (0x3 << 2)
484 #define RB_XSEL2_MASK (0x3 << 4)
488 #define PKR_MAP_MASK (0x3 << 8)
490 #define PKR_XSEL_MASK (0x3 << 10)
492 #define PKR_YSEL_MASK (0x3 << 12)
494 #define SC_MAP_MASK (0x3 << 16)
496 #define SC_XSEL_MASK (0x3 << 18)
498 #define SC_YSEL_MASK (0x3 << 20)
500 #define SE_MAP_MASK (0x3 << 24)
502 #define SE_XSEL_MASK (0x3 << 26)
504 #define SE_YSEL_MASK (0x3 << 28)
507 #define SE_PAIR_MAP(x) ((x) << 0)
508 #define SE_PAIR_MAP_MASK (0x3 << 0)
510 #define SE_PAIR_XSEL_MASK (0x3 << 2)
512 #define SE_PAIR_YSEL_MASK (0x3 << 4)